Logic design and implementation of FPGA for a high frame rate ultrasound imaging system

Recently, a method has been developed for high frame rate medical imaging [Jian‐yu Lu, ‘‘2D and 3D high frame rate imaging with limited diffraction beams,’’ IEEE Trans. Ultrason. Ferroelectr. Freq. Control 44(4), 839–856 (1997)]. To realize this method, a complicated system [multiple‐channel simultaneous data acquisition, large memory in each channel for storing up to 16 seconds of data at 40 MHz and 12‐bit resolution, time‐variable‐gain (TGC) control, Doppler imaging, harmonic imaging, as well as coded transmissions] is designed. Due to the complexity of the system, field programmable gate array (FPGA) (Xilinx Spartn II) is used. In this presentation, the design and implementation of the FPGA for the system will be reported. This includes the synchronous dynamic random access memory (SDRAM) controller and other system controllers, time sharing for auto‐refresh of SDRAMs to reduce peak power, transmission and imaging modality selections, ECG data acquisition and synchronization, 160 MHz delay locked loop (DLL) for accurate timing, and data transfer via either a parallel port or a PCI bus for post image processing. [Work supported in part by Grant 5RO1 HL60301 from NIH.]