Hybrid CMOS detectors for high-speed X-ray imaging

This article reviews advances and future directions in the development of hybrid-pixel array detectors for experiments in the fields of Inertial Confinement Fusion (ICF) and High Energy Density Physics (HEDP). These high-speed digital cameras build upon tremendous advances dating from the 1980s in microelectronics design and fabrication along with the foundational research in the high energy physics community in developing this technology for particle detection, most impressively at the Large Hadron Collider (LHC).^1–4 The hybrid-pixel technology also has wide and growing application at synchrotron and free-electron laser light sources around the world.⁵ Application to ICF and HEDP diagnostics requires adapting this technology to enable nanosecond time gating, asynchronous triggering for single-shot experiments, and operation in the intense prompt neutron and gamma radiation environments created by ignition and near-ignition scale fusion experiments⁶ that are now achievable.

Hybrid-pixel array detectors, also known as hybrid CMOS or hCMOS cameras in the ICF community, provide a microelectronics design architecture that enables independent optimization of the sensor array and the pixel electronics functionality. Large sensor arrays with high Quantum Efficiency (QE), nearly 100% fill factor, high spatial resolution, and fast time response can be optimized for the detection of x rays, particles, and visible light. The pixel electronics can be tailored to desired imaging and measurement performance metrics, such as time response, number of frames, dynamic range, radiation tolerance, read off rate, and in-pixel detection logic.

For ICF/HEDP research, the current generation of hCMOS cameras has a time resolution approaching 1 ns and 4 frames of in-pixel image storage with high sensitivity to x rays in the 1–6 keV spectral range. The ability to record multiple time-resolved, two-dimensional images along a single line-of-sight has enabled new measurement possibilities. hCMOS cameras are now in widespread use at the major ICF research facilities around the world as described in several accompanying articles in this special issue. Research teams are actively working to extend camera performance for sensitivity to higher energy x rays, faster time response, increased number of frames, larger detection area, greater radiation tolerance, and application to neutron detection. Many of the advances in industrial microelectronics fabrication and assembly processes have yet to be exploited in hCMOS cameras for ICF/HEDP research, which gives high confidence that the camera technology will continue to evolve for the next several decades. This enables a continuous rollout of more capable and specialized devices every few years, just as has come to be expected with consumer electronics and personal computing devices.

Hybrid-pixel array detectors are composed of a pixelated semiconductor sensor array and a separate pixelated readout integrated circuit (ROIC) that are interconnected at each pixel, creating a composite detector with electrical connections between each sensor and corresponding ROIC pixels. This is illustrated in Fig. 1.

“Hybrid” refers to using two semiconductor devices that can be fabricated from different materials and by different microelectronics technology nodes. The term “technology node” is commonly used to refer to the size scale of the smallest structure that can be fabricated on an integrated circuit; from micrometer scale in the 1980s to less than 10 nm today for the most advanced technology node.

The ability to interconnect two devices on a small pitch is a key enabling technology to realize this type of detector. A bump bond is the most common interconnect and is analogous to using a miniature solder ball for each pixel connection. Other more advanced interconnect technologies are also available that utilize chemical bonds between the two semiconductor devices, effectively creating a monolithic structure that is mechanically robust.

Photodiodes are typically the sensor of choice for hybrid-pixel detectors. They are readily created by common fabrication techniques, easily segmented into small pixels to provide fine spatial resolution, offer relatively high QE by direct detection of radiation, and directly interface with a ROIC by electronic signaling.

Photodiodes directly detect radiation by the creation of several electron–hole pairs proportional to the absorbed energy. For ionizing radiation in silicon, an average of 3.65 eV is necessary to generate one electron–hole pair.⁷ Optical radiation produces one electron–hole pair per absorbed photon. The basic structure of a planar photodiode is illustrated in Fig. 2.

The radiation-generated charge carriers are observed by moving them in an applied electric field to generate signal current. Photodiode regions with non-zero field magnitude are cleared, or “depleted,” of mobile charge carriers. A fully depleted photodiode has a depletion region extending throughout the entire volume. This is more easily achieved with high-resistivity material, where full depletion can be attained at a lower bias with a more uniform electric field distribution. An electric field magnitude of 10 kV/cm gives carrier velocities of ∼5 × 10⁶ cm/s in Si. In principle, <1 ns transit time is achievable for sensor thickness up to 50 µm, and such field magnitudes are achievable with 50 V bias. Further increases in electric field yield decreasing returns in carrier velocity and bring an increased risk of electrical breakdown.

Pixelated high-speed x-ray photodiodes can be fabricated using a variety of semiconducting materials, including silicon, gallium arsenide, germanium, and cadmium telluride. Each of these materials has optimum x-ray absorption in different regions of the x-ray spectrum, as shown in Fig. 3.

Materials with a higher atomic number generally have higher x-ray absorption. The increase is primarily driven by a higher photoelectric cross section, which can be advantageous in detectors because the radiation energy is deposited locally. Silicon (Z = 14) is a widely used sensor material, though low in atomic number, primarily due to decades of fabrication development and a stable native oxide. Germanium (Z = 32) also has a long history but suffers from material limitations, such as a narrow bandgap (associated with high leakage current) and a water-soluble oxide, making surface passivation more difficult. GaAs (Z = 31, 33) is an attractive alternative, with substantial processing development and a relatively high bandgap (∼1.4 eV), though compound semiconductors often bring more complex integration challenges. CdTe (Z = 48, 52), InP (Z = 49, 15), and TlBr (Z = 81, 35) are example material systems with even higher atomic numbers, albeit with lower overall fabrication maturity.

For fast time response, the active absorbing thickness of the diodes must be limited to no more than a few 10s of micrometers due to the finite drift velocity of electrons and holes and the practical limits on the maximum electric field that can be applied. This limit on the thickness of the photodiode constrains the maximum x-ray absorption that can be achieved for high-energy x rays.

Photodiodes with high QE and fast time response to x rays can also be used to detect visible light, electrons with energies up to 10s of keV, protons with energies up to several MeV, and neutrons with energies up to 10s of MeV, which greatly expands the measurement options for ICF/HEDP experiments.

Discrete silicon photodiodes with high QE to soft x rays and sub-nanosecond time response became commercially available⁸ in the late 1980s and utilized on z-pinch experiments at Sandia in the late 1990s by a team from Los Alamos National Laboratory led by Idzorek and Bartlett.⁹ A key advantage of these diodes for plasma x-ray diagnostics was their small size, low-voltage operation, predictable x-ray response, and low cost. However, recording signals from more than a few devices was problematic due to the cost and complexity of GHz transient digitizers. This experience led Porter in the mid-2000s to propose developing a custom integrated circuit and hybrid-pixel array detector at Sandia’s newly established Microsystems Engineering, Science and Applications (MESA) microelectronics design and fabrication facility to capture signals from a large number of x-ray photodiodes and optimized for ICF/HEDP experiments and ns x-ray imaging applications. That initial idea evolved into the Ultrafast X-ray Imager (UXI) program at Sandia. A similar microelectronics camera project was independently started about the same time by researchers at MIT Lincoln Laboratory and Lawrence Livermore National Laboratory but was eventually canceled before realizing a practical x-ray detector.¹⁰ The UXI family of hybrid-pixel cameras created over the past nearly two decades is described in Secs. IV and V.

The electronic circuitry to provide signal processing, time-gating, local storage, image read off, and user configuration is built into a Readout Integrated Circuit (ROIC), a type of Application Specific Integrated Circuit (ASIC) that incorporates common functionalities generally needed by most types of digital cameras.

ROICs have been developed with in-pixel circuitry to enable either photon counting or gated integration of the signal produced in each sensor pixel. For photon or particle counting, each pixel performs signal conditioning and contains a counter to record the total number of times the sensor pixel exceeds or falls within a specified signal level. Photon counting ROICs require many tens of ns to count each incident photon and are ideally suited for applications using long integration times and continuous illumination to build up an image with a high dynamic range.

For high-speed imaging typically required for ICF/HEDP experiments, in-pixel transistors are used as electronic shutters to set the integration time of the photodiode current. Transistor switching time depends on the technology node and is typically in the range of 10–100 ps with faster switching in the smaller and more advanced technology nodes. This is fast enough to make it feasible to design circuitry for gated imaging on a ns time scale, but not fast enough to digitize the integrated charge in each pixel with high resolution on the ns time scale between successive images.

The key time-gating, local storage, and reset circuitry for each sensor pixel must be contained in a corresponding ROIC pixel of about the same spatial size as each sensor element. A small number of transistors in each pixel are used as electronic shutters to control the integration of the sensor diode current over a small time interval. This integrated charge is stored in-pixel, on a analog storage element. A transistor is also used to control resetting the circuit to be ready to integrate the diode current again for another subsequent time interval. An illustration of the basic pixel circuitry for high-speed imaging is shown in Fig. 4.

Timing for the electronic shutters is generated globally by a common clock having a frequency on the order of GHz. This clock is then distributed to each pixel to synchronize the pixel integration times over the entire sensor area, something referred to as a global Shutter. For the highest speed imaging, the integrated sensor charge is stored on capacitors within each pixel element, with the number of capacitors determining how many sensor time samples can be acquired before reading off and resetting all the pixel stored values.

The input impedance of the ROIC pixel circuit that connects to each photodiode sensor element must also be kept small enough so that the RC time constant does not limit the time response. This typically requires a ROIC input impedance of a few kΩ or less for ns imaging.

The ROIC also contains circuitry to provide global functions common to all pixels and to enable communication and control between external electronics and the pixel array. This circuitry is typically implemented on the periphery of the pixel array and includes clock generation and distribution, pixel read off, ROIC and pixel initialization, chip monitoring, power and analog bias distribution, external trigger detection and handling, and read/write communication with external electronics components.

Reading out the stored analog pixel signals for each image frame takes times of order ms for megapixel scale images. So the only practical way to implement ns scale imaging is in a “burst mode,” where a fast image sequence is captured and stored in-pixel and then slowly read out before resetting the camera to be ready to acquire another image sequence. Analog to digital conversion of the pixel integrated charge can either be included in the ROIC or provided by specialized integrated circuits off-chip. Since the shot rates at ICF/HEDP facilities are relatively low, slower readouts for the detector images generally do not pose any operational challenges.

The high-speed timing (HST) circuitry is very challenging to implement for imaging applications with nanosecond shutter times. This requires generating and distributing shutter control signals with sub-nanosecond timing synchronization across the entire pixel array that can be of centimeter scale involving a large fraction of a million pixels. Small timing differences in these control signals can result in the pixel integration start and stop times varying across the array. One generally wants the pixel shutter times to be the same to better than 10% of the integration time, which requires better than 100 ps synchronization for all the shutter control signals for a 1 ns integration time.

Another unique challenge of x-ray and high-energy particle imaging with nanosecond time response is mitigating effects from the large instantaneous photocurrent flowing from the sensor array to the ROIC. For good dynamic range, each pixel needs to be able to record the photocurrent from up to 1000 x-ray photons. This also ensures that the signal-to-noise is not dominated by photon counting statistics. For a few keV x rays, this results in of order 1 × 10⁶ electrons of charge delivered in as short as 1 nanosecond. This level of x-ray flux striking a large fraction of a cm² sensor area can generate many amperes of photocurrent. This large transient current can induce voltage changes in electronic circuitry on the ROIC, potentially corrupting the integrated charge measurements and resulting image. These large transient effects are difficult to accurately model with available software used for custom integrated circuit design and verification. Careful attention to circuit layout and the use of isolated ground planes has been empirically shown to largely mitigate these transient effects, a somewhat surprising but fortunate outcome.

There are numerous commercial technologies available to interconnect the ROIC and sensor pixels with extremely high reliability. This process is referred to as hybridization and is described in detail in Ref. 3. In addition to having good electrical and mechanical properties, hybrid-pixel detectors require interconnects with low capacitance on a fine pitch. The interconnects can be fabricated either at the wafer-to-wafer level or with individual ROIC and sensor dice. Die-to-die bonding provides added flexibility while wafer-to-wafer bonding benefits from economies of scale for producing large numbers of detectors. The electrical contact pads are located on only one side of the wafer requiring one of the wafers to be flipped to align the ROIC and sensor pixel interconnect pads. This results in the few hundred micrometer thick handle wafer material being on the outside of the hybridized sensor photodiode array. This material is removed after hybridization by a back-thinning process using mechanical grinding and chemical etching to allow incident x-ray and particle radiation to directly interact with the collection volume of the photodiode array.

Bump bonding with solder or indium balls is the most widely available and cost-effective hybridization process. It can be used for either die-to-die or wafer-to-wafer bonding with a minimum pitch of ∼50 µm now standard and even finer pitches down to nominally 20 µm available for research devices. In this process, tiny droplets of metal are applied to the pixel pads on either the ROIC or sensor devices by electroplating or vapor deposition. The mating device is flipped, precisely aligned, and then pressed together. A combination of pressure and heat followed by epoxy underfill create a reliable and permanent electrical contact and strong mechanical bond.

More advanced metal-to-metal or oxide-to-oxide processes are available to directly bond the ROIC and sensor wafers. These processes require specialized surface preparation techniques and equipment to make each mating surface very flat and clean to ensure the chemical bonds form reliably. These direct bonding techniques can be applied for very fine pixel pitches approaching 10 µm. These processes work best for high volume production environments due to the time and effort required to achieve high bonding yields for a specific IC wafer design and can be problematic for small quantities of wafer bonding typical of R&D science projects.

A custom-designed electronics system is needed to operate a hybrid-pixel detector. The electronics system uses commercial off-the-shelf (COTS) electronics components to provide the functionality to configure, power, trigger, and read off the detector. They are often tailored to unique requirements and fielding infrastructure at each of the large science facilities.

A Field Programmable Gate Array (FPGA) is generally used to coordinate the discrete COTS components that perform specialized system functions. Other commonly used electronic components are power conditioning, voltage regulators, analog-to-digital converters (ADC), digital-to-analog converters (DAC), digital memory, signal conditioning, and computer communication interface.

A custom software package with a graphical user interface (GUI) completes the camera system. This software instructs a computer to send configuration and control commands to the FPGA. Custom firmware is the low-level software that determines how the FPGA responds to specific computer commands.

The user experience can be determined as much by the camera electronics and computer software as the performance of the hybrid-pixel detector. And the engineering resources and time for realizing and integrating a reliable electronics, firmware, and software camera system is often comparable to the time and cost to design and fabricate the detector ROIC.

The radiation tolerance of electronics and integrated circuits is an important consideration for reliable operation at particle accelerator and ICF facilities. The total ionizing dose (TID) is the main concern for particle accelerators due to steady-state continuous operation with equipment needing to function for many years before needing to be replaced. TID degrades the performance of integrated circuits primarily by accumulating charge in oxide layers near the critical structures that create transistors inside the device. Commercial ICs designed for radiation environments such as space applications have TID tolerance in the range of 50–300 krad.^11–13 Custom ICs designed for use at the LHC now report TID tolerance up to Grad levels.³ 

The prompt short-time-duration gamma and neutron radiation produced from fusion experiments is the main concern for ICF facilities. X rays are more readily attenuated with shielding so tend not to be nearly as big of an issue. TID is usually very modest at ICF facilities due to the low repetition rate of fusion experiments, which tends to be in the range of a few 10 s of shots per year with the highest fusion yields.

The prompt radiation dose can cause large transient currents due to localized interactions with atoms inside the IC device and resulting energy deposition. The effects of prompt radiation can range from changes in logic states or memory values to localized shorting of sensitive transistors that can require power cycling to reset or, in the worst case, physical and permanent damage to the device from excessive current in the shorted region.

Ignition-level experiments⁶ on the NIF produce yields of 1 MJ, a total of 4 × 10¹² 14 MeV DT neutrons, and a fluence of nominally 10¹¹ neutrons/cm² at a distance of 5 m and 10¹² neutrons/cm² at a distance of 1.5 m. This is by far the highest neutron fluence of any ICF facility.

Extensive neutron testing at close to these fluence levels has been reported for a variety of common COTS electronics components, including sensitive FPGAs.¹⁴ They find that the parts did not suffer permanent damage at the maximum fluence levels tested of 3 × 10¹² neutrons/cm² for 1 MeV equivalent neutron energies. They did observe soft errors in FPGAs, such as changes in digital memory values, at several orders of magnitude lower fluence levels. Some of these soft errors required resetting the chip configuration or firmware. The electronics development team at NIF also report testing an FPGA at a fluence level of 2 × 10¹² neutrons/cm² without observing any permanent damage.¹³ 

Custom ROICs designed for high radiation tolerance should be able to operate at much higher neutron fluence than COTS components by utilizing well-understood design and fabrication practices. These include large integrated circuit feature size, a silicon-on-insulator (SOI) CMOS fabrication process, storing pixel images in analog memory, and quickly putting the ROIC in an idle state after the x-ray image has been recorded but before the slower moving neutrons impinge on the camera. The custom photodiode array should also be robust to high neutron fluences. The primary effect is typically elevated dark current, which can be problematic for longer integration times or low-noise applications. At ICF/HEDP facilities, however, these issues are often avoided by observing high fluences for very short periods. Other photodiode changes include charge-induced surface channels,¹⁵ degraded charge carrier transport,¹⁶ and electrically active defects that change the electric field distribution.¹⁷ 

There are a large number of specialized digital cameras using custom ROICs that have been developed for scientific and industrial x-ray imaging to provide capabilities not possible with traditional and widely available CCD or CMOS cameras. Much of this development was driven by a diverse set of experimental needs at synchrotron light sources around the world.

Although fast-gated detector technologies have existed for decades, we differentiate here those based on semiconductor microelectronics. Gated microchannel plates, intensified CCDs, and streak cameras are amply covered elsewhere in the literature. The imagers covered in this article are based on a different technological approach with qualitatively different sizes/weight/power and offer greater scalability.

For application to ICF/HEDP research, it is helpful to divide these cameras into two categories: slow and fast frame rates. A brief survey and description of these two types of cameras are given below.

The Medipix family of sensors is the most mature and widely used hybrid-pixel x-ray imager.^4,18 Medipix grew out of research collaborations at CERN developing hybrid-pixel strip detectors for particle trackers¹⁹ and has grown into a very large multi-institutional collaboration. Medipix is a photon-counting device that emphasizes x-ray imaging applications. The Medipix ROIC utilizes in-pixel circuitry and logic to enable single photon detection and attain the highest spatial resolution and contrast by correcting for charge sharing between adjacent pixels. It is designed for long integration times and uses in-pixel counters with the option of hybridizing a variety of photodetector arrays, including Si, GaAs, CdTe, and CdZnTe, to maximize detection efficiency in different parts of the x-ray spectrum. It has also been hybridized to microchannel plates for direct electron detection.²⁰ Medipix started as a 64 × 64 element ROIC on a 170 µm pitch. Later versions were expanded to 256 × 256 pixels on a 55 µm pitch. The latest Medipix4 device uses through silicon via (TSV) technology to create a detector that is abuttable on four sides. Multiple Medipix4 detectors can be tiled together to construct multi-element detectors of arbitrarily large size with minimal gaps between sensors.

The Timepix family of sensors^21,22 is based on the Medipix ROIC design but modifies the in-pixel circuitry to enable registering the amount of charge produced from a detected photon for x-ray spectroscopy applications. The in-pixel logic also has a time-of-arrival mode for time-tagging in the nanosecond range.

Other examples of hybrid-pixel x-ray detectors that are widely used in the synchrotron and light source communities are CS-PAD,²³ XPAD,²⁴ PILATUS,²⁵ JUNGFRAU,²⁶ and ePix/tPix.²⁷ All of these cameras have long integration times and are optimized for single x-ray photon sensitivity and high dynamic range with most being two- and three-side abuttable for tiling multiple devices to produce detectors with very large areas.

Keck-PAD²⁸ is a hybrid-pixel array detector designed for high-speed burst-mode x-ray imaging and based on the PAD⁷³ family of x-ray detectors and ROICs. It has a minimum integration time of 50 ns, a minimum frame-to-frame time of 100 ns, eight frames of image storage, a 256 × 128 element pixel array on a 150 µm pitch, is three-side abuttable, and a fast readout speed of nominally 10 ms for a sequence of eight images.

Teledyne Imaging developed high-speed three-frame and 10-frame hCMOS optical cameras²⁹ for use on the Proton Radiography (pRAD) facility at Los Alamos National Laboratory. The second-generation ten-frame camera has a 50 ns minimum integration time, a 250 ns minimum inter-frame time, and an 1100 × 1100 element pixel array on a 40 µm pitch.

Kraken³⁰ is a high-speed 8-frame optical imager based on the UXI family of x-ray framing cameras and ROICs described in Sec. IV. It has a minimum integration time of 50 ns, a minimum frame-to-frame time of 100 ns, an 800 × 800 element pixel array on a 30 µm pitch, and is two-side abuttable. A four-detector tiled camera system is planned that will have an overall image area of 49 × 49 mm² and 1600 × 1600 pixels.

The Backside-Illuminated Multi-Collection-Gate (BSI MCG) family^31–33 of high-speed burst-mode optical imager combines CCD and CMOS design elements. The current generation sensor³⁴ has demonstrated 10-ns gate times with 576 × 512 pixels, 12.7 µm pixel pitch, and five full frames of image storage. Higher speed versions of this family of detectors³⁵ are under development with a goal of ultimately achieving a temporal resolution of 50 ps.

In 2004, Sandia began a project to develop a high-speed hybrid-pixel array detector, the Ultra-fast X-ray Imager or UXI, utilizing Sandia’s newly expanded Microsystems Engineering, Science and Applications (MESA) complex and upgraded 350-nm CMOS integrated circuit fabrication facility. The original UXI project goals were to develop a camera to enable multi-frame radiography³⁶ of ICF experiments on the Z Pulsed Power facility.³⁷ Z is the largest and most powerful x-ray source in the world. This application required a large area sensor with a pixel pitch of 25 μm, ≤2 nanosecond shutter time, two or more image frames with minimal dead time between frames, high QE for imaging 6-keV x rays, asynchronous operation, and external triggering with small trigger latency to synchronize to within a nanosecond of the final stages of current delivery on Z. One of the most challenging requirements was that the final camera system function reliably in the harsh electromagnetic interference (EMI) and radiation environment that exists in the Z target chamber within a meter of the multi-megajoule z-pinch implosion.

The Phoenix test chip was produced in 2009 and successfully demonstrated the key ROIC design elements for UXI cameras. It was followed in 2010 with the Harpi test chip that demonstrated the hybridization of 2 photodiode pixels and the detection of 6 keV x rays from the ZBL x-ray backlighting source. The first fully integrated hybrid-pixel imager, Griffin, was produced and tested in 2011 and had a 15 × 128 photodiode array on a 25 µm pitch. The first full-scale x-ray imager, Furi,^38,39 became available in 2013 and was followed in 2014 by the Hippogriff detector that incorporated an interlacing option to enable additional frames by gating adjacent pixel rows at different times. Today, Icarus⁴⁰ is the third-generation full-scale UXI camera and is routinely used at major ICF facilities around the world. Several of the articles in this special issue describe applications of the Icarus sensor in specialized ICF diagnostics. Daedalus⁴¹ is the most recent UXI detector and is in the final stages of performance testing. The evolution of UXI cameras’ performance is summarized in Table I. All of these cameras have a 25 µm pixel pitch and were designed to achieve a minimum integration time of 1–2 ns. The remainder of this section provides a detailed description of the design and performance of the Icarus device. The Daedalus and next-generation Tantalus ROICs are described in Sec. VI.

The unique imaging capability of the UXI detector family begins with the radiation sensor. Each imager to date has incorporated a two-dimensional array of Si photodiodes as the radiation sensing element for x rays, visible light, and energetic particles. An array of p–n junctions is fabricated on the same pitch and overall size as the targeted ROIC, and individual sensor elements are bonded mechanically and electrically to the corresponding readout during the hybridization process. The resulting hybrid-pixel sensor is a backside-illuminated CMOS imager with a fully depleted photodiode sensor and one-to-one correspondence of a sensor pixel to readout pixel. The high-level sensor design was dictated by a few key constraints, such as QE, speed, and imaging performance.

A requirement for high QE drove the need for a hybrid-pixel structure and backside-illuminated sensor to accommodate ∼100% fill factor. Additionally, the sensor thickness must be in the optimal range to facilitate sufficient x-ray interactions for high QE, yet avoid excessive charge collection time. A frontside-illuminated design would suffer a low fill factor and the photodiode thickness would be tied to the CMOS process, leaving them ill-suited to x-ray detection. Backside-illuminated devices on the same wafer as the readout electronics are possible,⁴² but this was deemed infeasible because the sensor would be too thick (see discussion below) and double-sided wafer processing was not practical.

The imager temporal response is the convolution of the ROIC’s gate opening and the sensor’s signal current.⁴³ If the sensor’s temporal impulse response is comparable to or greater than the exposure time, the imager temporal response is broadened and its utility is reduced. Ideally, for an imager targeting ∼1 ns exposure times, the sensor temporal impulse response would be <1 ns. The signal current lasts as long as charge carriers (electrons or holes) are moving within the sensor volume,⁷⁴ so the thickness should be minimized to reduce charge collection time. Assuming both carrier velocities could attain 5 × 10⁶ cm/s throughout the sensor volume,^44,45 a maximum thickness of 50 µm is allowable to achieve <1 ns collection time. However, this is in direct conflict with the goal of increasing x-ray QE, since transmission through the detector layer is the dominant loss mechanism for x-ray energies above ∼2 keV. Figure 5 shows the x-ray absorption for energies in the range of interest and the corresponding electron–hole collection time for various thicknesses of the Si sensor. A standard sensor thickness of 25 µm was chosen to balance the needs of temporal response and x-ray QE. This thickness has a nominal x-ray absorption factor of 0.5 at 6 keV and a theoretical charge collection time of ∼0.5 ns.

The high QE and large array size of Icarus can produce very high photocurrents in the photodiode array. This is of particular concern for backlighting applications where a high x-ray fluence is used to maximize dynamic range. An incident fluence of 1000 photons at 6 keV generates 6 MeV/pixel (9.6 pJ/pixel). This corresponds to 2.6 × 10⁻¹³ C/pixel, collected over 2 ns, for an instantaneous current of 132 µA/pixel. This level of illumination over the entire array will produce a peak current of 69 A. To date, testing of Icarus detectors at high single-shot illumination levels has not ended up damaging the detectors or significantly compromising the images.

Icarus and newer generations use the sensor pixel structure shown in Fig. 6 with n-type bulk Si material. A n⁺ region at the top provides a common electrode for holding one side of the junction at a high potential. A metal grid electrode in contact with this common implant ensures a robust, low-impedance connection across the array. Pixels are defined by a series of smaller p⁺ implant regions on the buried side, shown in green in Fig. 6. The metal feature below the pixel implant is extended laterally past the implant edges in a “field plate” configuration⁴⁶ to increase breakdown voltage. A common n⁺ implant grid between pixel implants forms a channel stop to ensure pixel electrical isolation. The channel stop is contacted by a common electrode so it could also serve as a common bias point, though this configuration was never successfully adopted.

The photodiodes must be reverse-biased for fast charge collection, and the ROIC is designed for CMOS voltage levels, so the common n⁺ implant must be at high potential (usually +50 V). Electrons drift to the common cathode and holes are collected to the segmented pixels. Though previous imagers had opposite polarity to minimize hole contribution to signal current, Icarus uses this hole-collecting scheme to allow positive signal current to the ROIC. Additionally, the dead layer (surface material not contributing to signal) can be reduced by taking advantage of the segregation behavior differences between n- and p-type dopants.⁴⁷ The electric field profile near the illuminated surface can be made more favorable to efficient charge collection of carriers created near the surface. The additional focus on the dead layer also led to some sensors with alternative surface treatments. Most notably, several wafers have included a nitride passivation layer to reduce the dead layer at the illuminated surface.

Various sensor thicknesses have been incorporated into UXI imagers. Both Hippogriff and Icarus sensors were created with 100 µm thickness (in addition to the standard 25 µm) for increased x-ray absorption at the cost of increased temporal response,⁴³ ∼10 ns. Icarus sensors with 8 µm thickness were fabricated for applications where few keV electrons are efficiently absorbed in the thinner layer while reducing the impact of nuisance hard x rays. These have a slightly shorter temporal impulse response.

The Icarus sensor arrays have been extensively characterized in terms of detection efficiency and temporal response. Surrogate devices following the same construction methodology, but with direct electrode readout, have been used to measure x-ray QE⁴⁸ and electron QE.⁴⁹ The 6-keV x-ray detection efficiency of an Icarus imager was verified in single-photon detection,⁵⁰ and the electron responsivity was measured.⁵¹ 

The temporal response of surrogate devices has been measured, and it is likely limiting the overall imager response.⁴³ The standard 25 µm sensor should have ∼0.5 ns collection time, yet gate profile edges and measurements with current-mode readout indicate 1–2 ns collection time. All sensor thickness variants have longer than expected charge collection time, indicating that charge carrier velocity saturation is not achieved throughout the sensor volume. At high flux, the photodiode current demonstrably slows the response even more than standard operation,⁵² due to the plasma effect.⁵³ 

The UXI family of ROICs operate in a global shutter, burst-mode configuration,⁵⁴ where multiple images are acquired at a very high speed (∼ns) and stored locally.⁵⁵ After the image sequence is acquired, a relatively slow (∼ms) read off sequence is initiated to digitize the stored pixel exposure values. During the intense radiation/EMI environment of a facility shot, only high-speed digital image acquisition electronics are necessary. The more noise-sensitive read off components are enabled after the shot is complete and background effects have subsided.

The overall architectural concept of the ROIC was unchanged from the first Harpi/Furi ROIC prototypes³⁹ through the third-generation Icarus ROIC,⁴⁰ but significant circuit-level improvements were made along the way.

The burst-mode pixel concept relies on in-pixel capacitors that serve as in-pixel analog memory. Each capacitor represents one frame and is controlled by an electronic shutter switch as shown in Fig. 7. Storing data in-pixel displaces the readout bottleneck to a later time after data acquisition has concluded. There is an inherent trade-off between pixel size and number of frames due to the physical size of the storage capacitor structures.

The following description will focus on the widely deployed and mature Icarus ROIC. Icarus has a 1024 × 512 pixel array on a 25 µm pitch and can record four frames of data with 1.5 ns minimum integration and interframe times.

The UXI ROICs use Metal–Insulator–Metal (MIM) capacitors for the analog memory element. This yields the fastest possible integration time, limited only by the RC time constant of the global shutter Metal–Oxide–Semiconductor Field-Effect Transistor (MOSFET) channel resistance and the storage capacitor. MIM capacitors reside within the metal stack and exhibit linear operation. In comparison with Metal–Oxide–Semiconductor Capacitors (MOSCAPs), MIM capacitors conserve transistor footprint, exhibit improved linearity, and have less charge leakage.

The Icarus and Daedalus ROICs use a single NMOS global shutter switch. NMOSFETs offer roughly twice the saturation current, for an equivalent-size PMOSFET. Larger shutter FET size will reduce on-resistance, allowing for faster RC charging of the storage capacitor memory, but is traded with an associated larger gate capacitance that slows down global shutter distribution. The single NMOS shutter switch was a development over the first-generation Furi/Hippogriff designs, which used a complementary N/PMOS Transfer gate (T-gate) to maximize dynamic range. A single shutter switch transistor simplified shutter distribution and increased the attainable number of frames.

Off-state or subthreshold leakage is present in all MOSFET devices and can be a significant consequence when using analog memory. The single frame unit pixel has three possible leakage paths (MIM, channel/bulk subthreshold leakage, and quantum gate tunneling), with the shutter MOSFET channel leakage being dominant. This leakage determines the maximum read-off time before an unacceptable amount of image information is lost.

An anti-bloom transistor was introduced in Icarus to protect the unit pixel from damage due to over-voltage. This transistor provides a shunt path to ground for excess photocurrent, extending the range of photodiode current where the pixel node can be kept from developing a damaging over-voltage well above the 3.3 V supply. Anti-bloom helps the sensor’s stored pixel charge demonstrate >80 dB rejection when exposed to photocurrent 10× full-well photocurrent after an image sequence acquisition.

Pixel readout is accomplished via a traditional in-pixel source follower, tied to a column line via a row access MOSFET. This method is how most active pixel sensors have been read out for decades.⁵⁶ However, the transistor footprint was allocated to an independent source-follower/access MOSFET per frame. This allows multiple, non-destructive reads of each frame to average broadband read noise. A PMOS source follower was chosen because it mates well with a ground-referenced signal in addition to PMOS having an order of magnitude lower 1/f noise.⁵⁷ 

Total pixel noise is a quadrature sum square of Johnson–Nyquist thermal noise from the sample and holds operation and the white noise of the source-follower/readout electronics. A significant portion of this noise is due to unchanging pixel-to-pixel variation or Fixed Pattern Non-Uniformity (FPNU). FPNU is resolved by taking “dark” images prior to data acquisition and subtracting these pixel-level fixed offsets from each “bright” image. Thermal noise is dictated by the channel resistance of the reset transistor and is present in all CMOS image sensors. Traditional CMOS imagers typically reduce this effect through Correlated Double Sampling (CDS). That approach, however, is impractical on the time scales necessary for ns-gated imaging.

Due to the low charge gain required to achieve a large full well, read noise is by far the dominant noise source. Icarus operates with a nominal 100 fF unit capacitance that equates to 45 e−thermal noise at room temperature. Total read noise, including thermal, for Icarus has been measured at 300 e−. This translates to 296 e−attributed to read noise or 6.6× thermal noise.

Global shutters are necessary to prevent motional artifacts and the ability to tune and adjust these shutters is critical to support a wide variety of experiments. The speed of hCMOS operation requires shutters to be generated on-chip. To achieve this, a digitally programmable high-speed timing (HST) generator was developed. The user pre-programs the shutter pattern desired into a serial shift register, allowing for independent shutter times and inter-frame times for each frame as illustrated in Fig. 8.

Once this timing has been programmed, the ROIC awaits an external, asynchronous trigger provided by the ICF/HEDP facility. This trigger enables an on-chip oscillator tuned to operate at a specific frequency. These pre-programmed shutters are integer units of this clock frequency.

Dual-edged flip flops act as a frequency doubler so the ROIC can be operated with an oscillator tuned to nominally 500 MHz with a 1-ns base unit of time. The doubled oscillator frequency serves as a time base for the pre-programmed shutter pattern. The shutter pattern output from the shift register is de-serialized for global distribution. Figure 9 shows a block diagram of the Icarus high-speed-timing generation.

Once the shutters have been generated, they are distributed to the unit pixels with high precision across ∼10 mm of signal trace length. Shutter distribution is treated like a microprocessor clock distribution problem, which is a rich field of research in ASIC design.⁵⁸ For all UXI ROICs to date, a binary replication tree was selected. This tree replicates the shutter signals from the single output of the high-speed-timing generator to each of the 1024 rows. Shutter distribution is split into left and right halves of the ROIC. This allows for eight independently timed frames, each with a reduced image size of 1024 × 256 pixels. Splitting timing distribution on the ROIC also reduces row-wise shutter load.

Row-wise shutter capacitive load ultimately dictates the minimum integration time achievable on the ROIC. The gate capacitance of each shutter MOSFET, combined with interconnect parasitic capacitance, creates a distributed RC load that reduces the rise/fall time of the global shutter gate voltage in addition to introducing a small, ∼1 ps/pixel, column-wise timing skew as shown in Fig. 10. Each row drives 256 column shutters distributed across 6.4 mm of interconnect.

Due to the low repetition rate of large ICF/HEDP facilities, image data readout can occur on a slow timescale, only constrained by leakage of the analog charge storage. As such, the readout was kept intentionally simple and relatively slow to a ROIC constrained readout rate of ∼7.5 Hz for the 2.1 M pixel equivalent image data. The array is segmented into 32 column by 512 row regions, each selectively coupled to an output buffer as shown in Fig. 11. These amplifiers have been measured to have less than 300 µV rms noise and dominate the noise floor due to the low overall charge gain required to achieve a large full well.

For hybrid-pixel detectors, the hybridization methodology is a key technology discriminator for imager specifications. Although indium bump bonding is a mature technology, the post-bonding steps in handle wafer removal significantly increase the difficulty for UXI imagers. Therefore, the Direct Bond Interconnect (DBI) wafer-to-wafer (w2w) bond⁵⁹ was adopted as the hybridization method for nearly all UXI imagers. An overview of the processing steps is shown in Fig. 12.

The process begins with the independent creation of a sensor wafer and ROIC wafer, each using Silicon-On-Insulator (SOI) wafer technology. The device layers can be tailored to electrical needs, while the overall mechanical stability is provided by a handle wafer several hundred micrometers thick. The necessary in-pixel connections are terminated at exposed vias on the top surface. These starting wafers are sent to a commercial vendor for the Ni DBI w2w process. The vendor adds an ultra-flat, chemically prepared oxide interface with interspersed metal interconnects. The metal connectors are electroplated on seed metal features to create Ni cylinders of 5 µm diameter and ∼1 µm height. For UXI detectors, there is one interconnect per pixel to route the sensor signal current to the ROIC front-end. Encapsulating oxide over the ROIC bond pads is removed at this stage to facilitate their opening after bonding. The wafers are then bonded via plasma-activation and anneal process with a mechanical strength near the fracture strength of Si. The top side handle wafer is then removed by backgrinding and chemical etch to reveal the buried dielectric adjacent to the sensor. The dielectric is chemically removed, or for the special case of nitride-passivated sensors, the dielectric is instead patterned. A top side electrode of ∼0.5 µm Al is added for the sensor bias. A wide metal ring surrounds the periphery of the sensor for electrical connection to the bias supply. A metal grid extends throughout the sensor’s active region to ensure low-resistivity contact throughout the sensor area. Finally, the sensor Si layer is removed at the periphery to reveal the bond pads. Figure 13 shows a cross section Scanning Electron Microscope (SEM) micrograph of the wafer interface with embedded interconnect.

The primary advantage of the DBI w2w process is in alleviating the difficulty of the top handle wafer removal. A die-level indium-bump process, though perhaps more readily implemented for the interconnect, leaves a more challenging part to process in handle removal.

The package is a significant component in detector performance, reliability, and fieldability. An evolution in packaging for UXI detectors has seen the outline shrink substantially and has progressively incorporated modern packaging techniques. Figure 14 shows example detector modules among the various ROIC generations, culminating in the Icarus Small Outline Package (SOP).

The Icarus SOP design was intended to provide maximum flexibility in detector deployment by minimizing the size of the pluggable module. The core of the package is a multi-layer printed circuit board (PCB) substrate constructed using high-density interconnect technology. The top of the board includes a die pad for the Icarus detector die and ∼700 wire bondable pads. The nodes are routed internally to a 160-pin, high-density connector on the bottom of the board. Passive components are also located on the bottom for local supply bypassing and fixed resistance values. The detector die is mounted to the top die pad using standard semiconductor die mounting techniques. Al wedge wire bonds connect the ROIC bond pads to the package bond pads. Additional wire bonds carry the sensor bias from the PCB to the top side electrode ring. Finally, a dam-and-fill technique is used to encapsulate all bond wires while leaving the sensor’s active area exposed. The package dimensions are 33.15 × 21.81 mm² and is 7.8 mm tall. It is mechanically robust and does not require expert handling.

Camera electronics systems have been developed by several engineering teams to operate Icarus sensors on the Z and NIF facilities.¹³ The camera designs have evolved over nearly a decade to be more robust and compact, to integrate with a variety of existing diagnostics, and to utilize the available infrastructure at each of the facilities. Different versions of these electronic systems can operate in a vacuum, high EMI environments, and at neutron fluences^60,61 up to 10¹² n/cm².

The Icarus detector requires initialization of the high-speed-timing parameters prior to imaging. Once initialized, a fast trigger initiates the burst-mode image capture sequence. A 50 V bias is required for the photodiode array and 3.3 V to power the ROIC. The ROIC digital IO is 3.3 V Low-Voltage Complementary Metal Oxide Semiconductor (LVCMOS) compatible. The ROIC analog input bias voltages range from 0.0 to 3.3 V. There are 32 parallel read-off channels for digitizing the analog pixel values that range from 0.7 to 3.0 V with typical values of 0.9–2.5 V. UXI pixel data analog output is selected by the array frame, row, and column address. The pixel array is 1024 rows by 512 columns by 4 frames creating 2 Megapixels of data. The analog output settling time for each UXI pixel address is nominally 2 µs, resulting in a total read-off time of 131 ms, which is sufficient to avoid image degradation due to pixel storage capacitor leakage. To date, camera systems have digitized and stored pixel data in digital memory for transfer to a host computer at a later time. Shutter monitor outputs are available to indicate the start and stop times of each frame. Figure 15 shows a block diagram for a typical Icarus camera electronics system.

Both single-board and multi-board systems have been successfully designed and operated. Figure 16 shows three generations of Icarus camera electronics developed for use on the Z and Z-Beamlet Laser facilities.

Key performance specifications of UXI systems based on the Icarus detector are listed in Table II.

The timing characteristics at 2-ns integration time and 2-ns inter-frame time have been demonstrated in multiple articles.^43,50,62,63 Example shutter profiles are shown for a standard Icarus sensor at various exposure times in Fig. 17.

The minimum exposure time is documented as low as 0.7 ns FWHM in certain circumstances,⁶² though ∼1.5 ns is more typical. An example of the shutter profile for 1 ns integration time and 3 ns interframe time for an Icarus detector with a thin 8-μm-thick sensor is shown in Fig. 18.

The relative linearity at the low end of the sensitivity range was studied in Refs. 50 and 62 and over the entire sensitivity range in Ref. 52. The absolute sensitivity for single photons⁵⁰ was measured to be 1.24 and 1.82 µV/e⁻ over the full range. The pulsed x-ray response was found to be linear⁵² to ∼700 ke⁻. Pixel-to-pixel coupling (cross-talk) was measured at 0.1%, and uniformity of x-ray response across the array varied <5%.⁵² 

hCMOS ROICs use a combination of hardening by process and hardening by design to enhance radiation tolerance and enable operation on fusion ignition experiments. Sandia’s CMOS7 foundry uses Silicon-On-Insulator (SOI) CMOS technology. SOI processes are hardened to a Total Ionizing Dose (TID) > 1 M rad(Si).⁶⁴ Additionally, SOI eliminates the Single-Event-Latchup mechanism of bulk CMOS processes^65,66 where a parasitic pnpn device can be triggered and create a low impedance path between power and ground, causing potentially catastrophic damage to the integrated circuit.

Other Single Event Effects (SEEs) of concern include Single Event Upset (SEU), Single Event Snapback,⁶⁷ and Single Event Gate Rupture. Snapback effects are resolved by process hardening⁶⁸ and could present an issue with a commercial SOI technology process. SEU is a concern with dense memories or arrays of flip-flops where an energetic ionizing particle can strike a sensitive node within the memory cell or flip-flop and change the state of the stored binary value, corrupting the memory. hCMOS ROICs have been intentionally designed to have few flip flops in the critical shutter path. A small number of lip flops reside in the High Speed Timing Generator and present a small cross-sectional area. Additionally, due to insertion and propagation delay, the sensor has been triggered and shutters generated prior to radiation (photons or neutrons) being incident on the sensor. Finally, the large capacitive nature of the shutter lines inherently slows down the RC time constant of the global shutter that could be sensitive to a Single Event Transient charge deposition, rendering it insensitive to these effects.

Dose rate effects due to the large gamma/x-ray emission of an ICF/HEDP facility can cause photocurrent generation in the parasitic reverse-biased PN junction diodes inherent to CMOS processes. The consequences of this effect are a transient photocurrent conduction path between the power supply to ground, collapsing the power supply. This effect is mitigated through strong on-chip power supply distribution and power supply bypass capacitance.

hCMOS detectors are in the early stages of testing for radiation tolerance at the level of 10¹² neutrons/cm² needed to operate on fusion ignition experiments on the NIF [MacPhee 2022]. Initial observations are encouraging for reliably operating UXI cameras in these high-radiation environments. The weak link is presently believed to be the COTS ICs used in the current generation of camera electronics systems. Work is underway on new electronic systems using a combination of more radiation tolerant COTS chip sets and a strategy of idling the COTS ICs during the time of the highest radiation fluence.

The Icarus UXI sensor is routinely used for x-ray backlighting, spectroscopy, and imaging on the Z, NIF, and Omega facilities. Several of these diagnostics are described in detail in the accompanying articles of this special issue.

An example x-ray image at 6.15 keV from the bent-crystal-imaging (BCI) backlighter³⁶ on Z of an imploding z-pinch liner is shown in Fig. 19. The Icarus integration time is 10 ns for this image and is used to gate out high levels of x-ray self-emission that occur more than 10 ns after the radiograph when the pinch stagnates on axis. Time-gating the backlighter image produces cleaner images with a higher dynamic range compared with previous data recorded with time-integrating image plate detectors. The backlighter x-ray source time duration is nominally 1.5 ns for this image. A longer Icarus integration time was used for this radiograph to simplify synchronizing the Icarus sensor to the z-pinch implosion.

An Icarus image sequence of x-ray spectra taken on the Z opacity spectrometer⁶⁹ is shown in Fig. 20. This image sequence shows x-ray absorption features in the 1.3–1.9 keV spectral range from an iron plasma and is used to determine iron opacity at high temperatures and densities. For each image frame, the spectrum is in the horizontal direction and is spatially imaged in the vertical direction. The integration time of each image is 2 ns and the frames are at 2 ns intervals. The Icarus independent-halves timing option was used to acquire eight frames of data (without any temporal gap between the frames) on this experiment with the five frames shown in the figure capturing the plasma emission of interest.

An Icarus image of the axial x-ray emission from a laser-heated MagLIF gas-cell target⁷⁰ using a pinhole camera is shown in Fig. 21. This eight-image sequence was taken using the independent timing option on Icarus for each of the 1024 × 256 halves of the detector. The integration time for these images was 2 ns and the frame separation time was 3 ns. The images show the plasma dynamics of the 4 ns duration heating laser propagating into the gas-filled target. Icarus sensors have also been used to record time-resolved axial images of laser heated hohlraums on NIF using the Gated-LEH (GLEH) diagnostic.⁷¹ 

A perennial constraint for UXI imagers has been low sensitivity to hard x rays with photon energy above about 10 keV. Increasing the pixel size would add collection area, but it would negatively impact spatial resolution and increase sensor unit pixel capacitance. Increasing the sensor thickness comes at the cost of temporal resolution. Sensor pixels constructed from higher atomic number material can maintain a similar size to the Si standard, but benefit from increased photoelectric absorption that scales as the atomic number to the fourth power.⁷² Fast GaAs current-mode detectors have been demonstrated with sub-ns impulse response and enhanced hard x-ray absorption in comparison to similarly sized Si detectors.⁴⁸ GaAs sensor arrays have been fabricated and bonded to Icarus imagers, which are currently in testing. GaAs, Ge, or CdTe sensor arrays may be future options for Gen 3+ ROICs.

The existing Si photodiode design has a sufficiently long temporal impulse response to impact imager gate times.⁴³ The 25 µm thick Si sensor design has a significantly longer charge collection time than the expected ∼0.5 ns. With future ROIC generations predicted to have 0.5 ns or 0.25 ns minimum gate times, there is a strong incentive to reduce sensor charge collection time. A variety of strategies could reduce the sensor’s temporal impulse response. Altering the sensor pixel layout could reduce low-field regions and create more uniform charge induction efficiency throughout the volume. A thinner sensor layer would reduce charge collection time, though at the cost of reduced QE for some radiation types. Efforts to date have been hampered by low-field regions common to all sensor thicknesses. Finally, cooling the sensor could have a modest effect by increasing carrier velocity.

Two new ROICs, Daedalus and Tantalus, are in the development and fabrication pipeline. The fourth generation Daedalus ROIC contains significant improvements in timing distribution to increase timing uniformity and shutter adjustability. Frame count has been reduced to three in order to accommodate a >1 M e−full well. A shorter minimum integration time of 1 ns timing is expected and increased programmable timing functionality has been developed as well. Additional timing modes include “Zero-Dead-Time” (ZDT), “High Full Well” (HFW), and row-wise interlacing. ZDT allows the user to interlace two rows spatially while offsetting their shutters temporally. This timing provides image coverage with one row while the other row is being reset. HFW mode asserts all shutters simultaneously. This delivers a single frame but with a 3× larger full well than in multi-frame operation. Interlacing allows the user to program subsequent rows to be triggered after the prior row, trading spatial resolution for an increased number of image frames. Daedalus has been hybridized and is undergoing performance testing and imaging characterization.

The latest ROIC design, Tantalus, is the first ROIC targeting a commercial 130 nm foundry. Commercial foundries do not offer the extreme radiation hardening of Sandia’s 350 nm CMOS7 process; however, they offer a design path to shorter sub-ns gate times due to the lower capacitance of each frame’s transistor switch encountered along the row. Tantalus is primarily a test and evaluation ROIC with many circuit variations to determine the performance of this commercial foundry both electrically and for operation in high radiation environments. Seven oscillator variants and 5 pixel variants have been designed to establish baseline performance and to evaluate the radiation tolerance of different circuit architectures. Tantalus has a primary baseline pixel equivalent to the Icarus pixel of four frames and a 25 µm pitch. There are three additional variations of this design using different transistor types and hardening techniques. The ROIC was designed for 500 ps minimum integration time and incorporates a similar timing generation and distribution concept as Daedalus, with independently programmed and timed quadrants. Finally, Tantalus has been designed for a significantly faster readout to better facilitate operation in high repetition rate facilities such as synchrotrons and X-Ray Free Electron Lasers (XFELs). All prior ROIC readout has been limited to 7.6 frames per second. This is equivalent to 16 M pixels per second. Tantalus is designed for ∼20× faster operation with 152 frames per second readout. This equates to ∼318 M pixels per second. Tantalus has completed fabrication and is currently undergoing functional electrical testing.

Hybrid CMOS detectors are a new class of high-speed x-ray imager being used in a growing number of ICF and HEDP experiments. They are burst-mode digital framing cameras that can capture multiple images along a single line-of-sight. The pixelated photodiode sensor arrays have high QE for x ray, particle, and optical detection. The UXI Icarus detector has a minimum integration time of 1.5 ns. New and more capable UXI detectors are under development that are expected to reduce the minimum integration time to nearly 0.5 ns. UXI detectors with GaAs photodiode arrays will soon be available that extend high QE x-ray detection to 30 keV. These detectors have high radiation tolerance and have successfully operated on MJ fusion experiments on the NIF. An active area of development is to enhance radiation tolerance to enable the reliable operation of cameras on higher yield fusion experiments approaching 10 MJ. The hCMOS design architecture is very flexible and offers opportunities for innovation and performance improvements well into the future building on advances in the microelectronics industry.

We would like to thank our many colleagues and friends at Sandia who helped create the UXI camera technology and develop techniques to utilize it in ICF and HEDP experiments on the Z Machine and the Z-Beamlet laser. Among them are Larry Ruggles, John Stahoviak, Mark Kimmel, Tony Colombo, Joel Long, Aaron Edens, Doug Trotter, Lu Fang, Marcos Sanchez, Rex Kay, and Gideon Robertson.

Sandia National Laboratories is a multimission laboratory managed and operated by the National Technology and Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under Contract No. DE-NA0003525.

This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy or the United States Government.

The authors have no conflicts to disclose.

J. L. Porter: Conceptualization (lead); Formal analysis (equal); Funding acquisition (lead); Investigation (equal); Methodology (equal); Supervision (lead); Validation (equal); Writing – original draft (lead). Q. Looker: Formal analysis (equal); Investigation (equal); Methodology (equal); Validation (equal); Writing – original draft (equal). L. Claus: Formal analysis (equal); Investigation (equal); Methodology (equal); Validation (equal); Writing – original draft (equal).

The data that support the findings of this study are available from the corresponding author upon reasonable request.