An inexpensive yet versatile transducer controller for non-contact scanning probe microscopy (SPM) based on a PIC32 microcontroller from Microchip Technology, Inc is described. In addition to feedback control using the amplitude or phase of the signal from the non-contact transducer, the controller includes a phase-locked loop for frequency-shift feedback, as well as fixed-amplitude, quality factor (Q) control, and self-excitation modes. Apart from the input amplifiers, output buffers, and the Q-control circuit, all other functions of the controller are instantiated in software on the microchip, enabling rapid changes in operating parameters if needed. The controller communicates with a host personal computer via a simple serial connection. The controller has been tested with a quartz tuning-fork transducer but can be used with any oscillating non-contact transducer.

Non-contact scanning probe microscopy (SPM) is widely used to investigate the properties of samples near their surfaces with nanometer scale precision.1 In non-contact SPM, a force transducer (typically with a tip) is driven at its mechanical resonance frequency. As it approaches the surface of the sample, interactions between the tip and sample modify the oscillation amplitude, oscillation frequency, and the phase difference between the drive and response of the transducer. Any one of these signals can be used as a feedback signal to control the distance between the tip and sample, and each has its advantages.

Amplitude mode is perhaps the easiest to implement. The transducer is driven on resonance, and as the tip approaches within a few nanometers of the surface, the amplitude decreases in a monotonic fashion. However, amplitude mode SPM is not suitable for non-contact transducers with high quality (Q) factors. This is because it takes a time of order Q/f0 (where f0 is the resonant frequency of the transducer) for the amplitude of the system to relax to its steady-state value after a transient, such as that caused by a change in the height of the sample during a scan. The Q factors of transducers can be very large, of the order of 105, particularly in vacuum and at low temperatures, leading to relaxation times of the order of seconds and very long scan times to obtain an image. Using the phase of the signal at a fixed frequency does not suffer from this problem, as the phase responds on a time scale ∼1/f0. However, the frequency will also shift, and if the Q of the transducer is large, the frequency shift may be greater than the envelope of the resonance. These problems can be avoided if the Q of the transducer can be artificially reduced by feeding some fraction of the signal from the transducer response back into the transducer drive with appropriate phase. This is called Q control.2 

For some applications, maintaining a large Q has advantages in terms of the sensitivity of the transducer, as the force sensitivity scales as Q. For these applications, tracking the shift in the resonant frequency of the transducer using a phase-locked loop (PLL) provides a solution.3 As with phase-mode feedback, the resonant frequency changes on short time scales of order 1/f0, but once locked to the resonant frequency of the transducer, the PLL can track changes in frequency many times the width of the transducer resonance. The shift in frequency as the tip approaches the surface provides a direct measure of the tip–sample interaction. In such frequency-shift mode SPM, one also frequently maintains constant the amplitude of the transducer using a secondary feedback loop.

As one might want to use different feedback modes in different situations, we describe below a relatively inexpensive SPM controller based on a Microchip PIC32 microcontroller that enables amplitude mode feedback, phase mode feedback, frequency-shift feedback, oscillation amplitude control, Q control, and transducer self-excitation, all in one package. The input to the controller is an electrical signal corresponding to the amplitude of the transducer oscillation, and its output is an electrical signal for driving the transducer. Parameters for modifying the various modes can be changed nearly instantaneously through software. The controller interfaces well with our custom SPM controller4 and home-made microscope, which uses a tuning-fork transducer requiring only two electrical leads for self-excitation and self-detection, but should work with any non-contact transducer with appropriate interface electronics up to a frequency of 2.5 MHz with a only a minor change in components.

Figure 1 shows a schematic of the transducer controller. At the center of the instrument is a Microchip PIC32HMZ144 microcontroller unit (MCU).5 operating at a frequency of 200 MHz. It is equipped with a number of peripheral modules that are useful for our application, including multiple counter/timers, serial peripheral interface (SPI) modules that talk to different digital chips, and a Universal Asynchronous Receiver/Transmitter (UART) interface for serial communication with a host computer. The analog inputs and outputs are all buffered with operational amplifier (op-amp) followers (not shown) in order to isolate the internal electronics from outside fluctuations and to prevent loading of the digital to analog converter (DAC) outputs. The instrument is constructed inside a shielded box with custom printed circuit boards (PCBs). The MCU itself comes packaged as a board (PIC32HMZ144) from Olimex6 with a programming interface and two 50 pin connectors. This configuration enables plugging the board into our custom PCB and programming it in place. Below we describe first the overall design of the instrument and then describe in detail the design and operation of key sections, including the software algorithms, using a quartz crystal tuning fork oscillator as transducer.

FIG. 1.

Overall schematic of the PIC32 based SPM transducer excitation controller.

FIG. 1.

Overall schematic of the PIC32 based SPM transducer excitation controller.

Close modal

The input to the controller is an electrical signal corresponding to the motion of the transducer. In our tuning-fork SPM, this is the output of a home-made current preamplifier that translates the current through the tuning fork into a voltage. The gain of the preamplifier is approximately 10 V/nA at the frequency of oscillation of the tuning fork. For our tuning forks, typical input voltages are 5 V rms at frequencies of ∼30 kHz, corresponding to oscillation amplitudes in the sub-nm range. Of course, the input signal could be an electrical signal from any transducer such as from a photodiode detector of a conventional optically detected cantilever.

After buffering, this input signal feeds three separate circuits. The first is an analog rms-to-dc converter chip (Analog Devices AD6377) that provides a dc output proportional to the amplitude of the input signal (and hence the transducer oscillation amplitude). This dc output is made available externally through a buffer and is also fed to the input of a 14 bit analog-to-digital converter (ADC, Analog Devices AD7367) that is interfaced to the MCU via a SPI.

The input signal is also fed to a phase-frequency detector that compares the phase of the input signal to the phase of the drive frequency and gives the difference in phase between the two signals in degrees.8 This phase detector is the heart of the digital PLL and spans discrete components on the PCB as well as counter/timers in the MCU. The amplitude and phase inputs to the MCU serve as the inputs to digital proportional/integral/differential (PID) controllers encoded in software in the MCU that determine the amplitude and phase of the drive signal if engaged. The MCU generates an ac drive signal via a Direct Digital Synthesis (DDS) chip9 (Analog Devices AD9832) with which it communicates through a SPI. The AD9832 has 32 bits of frequency resolution (1 part in 4 × 109). With a clock frequency of 1 MHz, determined by a required external crystal oscillator, this corresponds to roughly 0.25 mHz resolution, more than sufficient for our purposes. The MCU operates the DDS at a user-selectable fixed frequency or by continuously updating the frequency if the PLL is engaged. The AD9832 gives a clean output sine wave up to frequencies of order 1/10 the external oscillator frequency (100 kHz for the 1 MHz crystal in our case). However, the frequency of the crystal can also be increased to a maximum of 25 MHz for the AD9832, allowing sine wave excitations at frequencies up to 2.5 MHz, so the PLL can be used for transducers operating at higher frequencies with minor changes in circuit components.

Finally, the input signal is also fed to the Q control circuit, which is a simple analog circuit that can modify the input signal amplitude and phase before subtracting it from the DDS drive signal using a unity-gain subtractor. The output of this difference amplifier is fed into one input of a multiplier (Analog Devices AD632). The second input to the multiplier is provided by the MCU so that one can operate in fixed drive amplitude (excitation) mode or in fixed transducer response amplitude mode if the amplitude PID is engaged.

Two digital switches under control of the MCU (Analog Devices ADG453) determine whether the Q control circuit is engaged and whether the transducer can be self-excited. If both the Q control select switch and the self-excitation switch shown in Fig. 1 are closed, Q control is engaged. If the Q control switch is open and the input of the amplifier is connected to ground, Q control is disabled. On the other hand, if the self-excitation switch is open and the Q control switch is closed, the transducer is no longer driven by the DDS, but only by the Q control circuit. By appropriately adjusting the amplitude and phase of the Q control circuit, one can get the transducer to self-oscillate, although getting it to oscillate at its fundamental frequency is non-trivial. Even in self-excitation mode, however, the amplitude of the oscillation can be controlled by engaging the amplitude PID.

The overall operation of the instrument is controlled by a program on a host computer that communicates with the MCU over a conventional serial port using the UART interface of the MCU. This program was written on a Windows 10 computer in open source Free Pascal10 with the Lazarus IDE11 due to the personal preference of the author, but any computer program that is able to send and receive alphanumeric data over a serial interface can be used to control the instrument. The advantage of Free Pascal and Lazarus is that the same program can be immediately compiled on any operating system. In particular, the program can be compiled on computers running Linux and easily incorporated as a module in our real-time scanning probe microscopy (RTSPM) program.4 

We now describe the design of key elements of the controller in more detail.

The phase detector measures the phase difference between the transducer response and the transducer drive.12 The simplest means to detect the phase difference between two sinusoidal signals is to multiply them using a four-quadrant analog multiplier. In our case, the drive is provided by the DDS chip. If As cos(2πfst + ϕ) is the input signal and ADDS cos(2πfDDSt) is the signal from the DDS, then the output of the multiplier will be a signal of the amplitude proportional to the product AsADDS with contributions at the sum and difference frequencies,

cos(2π(fsfDDS)t+ϕ)+cos(2π(fs+fDDS)t+ϕ).

One is interested in the component at the difference frequency, so the output of the multiplier is filtered using a low-pass filter with a cutoff well below the sum frequency. After this so-called loop filter, the output can be used to directly drive a voltage controlled oscillator (VCO). If the loop and VCO parameters are correct, the system will “lock” onto the input signal so that the DDS frequency and input signal frequency are the same and have a fixed phase relationship, regardless of small changes in the input signal frequency. In the lock condition, the voltage controlling the oscillator is a direct measure of the difference between the VCO’s central frequency and the frequency of the input signal and can be used as a feedback signal for frequency-shift mode SPM. If the loop filter is only a low-pass filter, however, this voltage is also a measure of the phase difference under lock conditions—in order to obtain frequency lock, one needs to maintain a specific phase difference between the input and drive. Unfortunately, this phase difference may not be the correct one in order to lock on to a nonlinear element like a resonant oscillator. To circumvent this problem, one can use a proportional/integral (PI) or a PID controller as the loop filter. The input to a PI or PID controller is an error signal (in this case, the low-pass filtered output of the multiplier) that it tries to set to 0 by controlling the voltage input of the VCO. By introducing an offset into the input of the PI or PID controller, one can set the phase difference between the input signal and the drive under lock condition to any desired value. This is the type of controller that was used in our hybrid analog–digital PLL.13 The hybrid analog–digital PLL still suffers from a limited lock range that depends on the characteristics of the overall loop filter.

Another problem associated with the multiplier-based phase detector is that the phase difference signal changes as a function of the amplitude of the input signals. While one can keep the DDS reference voltage amplitude constant, the input signal might change while scanning. Consequently, the output of the phase detector will change, indicating a change in phase difference even though the actual phase difference has not changed. One can use a feedback circuit to keep the amplitude of the input signal constant. However, in practice, this results in an interaction between the amplitude feedback and the PLL frequency feedback, with potentially undesirable consequences.

In order to get around these problems, we decided to use a so-called phase-frequency detector for the current instrument.8 A phase-frequency detector can be constructed from two positive-edge triggered D type flip-flops and an AND gate, as shown in Fig. 2. The sinusoidal signals from the transducer and the DDS are first converted to transistor-transistor logic (TTL) level square wave pulse trains with corresponding input frequencies and phases using two separate Schmitt trigger circuits with trigger thresholds of about 100 mV (not shown in the figure). These pulse trains are then connected to their respective inputs as marked in Fig. 2. To understand the operation of the phase-frequency detector, consider the case when the phase (or frequency) of the transducer signal leads the phase of the DDS signal, with both Q outputs of the D flip-flops being initially low. As the signal input transitions from low to high, the Q output of the upper flip-flop will go high and will remain high even if the input signal goes low, unless a signal is applied to its reset (R) port. This happens when the DDS input to the lower flip-flop transitions from low to high, sending its Q port high, which, in turn, triggers the AND gate to reset both flip-flops. Thus, the time that the Q output from the upper flip-flop is high divided by the period of the input signal is a direct measure of the phase difference between the two signals. Conversely, if the DDS signal leads the transducer signal in phase, the Q output of the lower flip-flop will remain high for a time corresponding to the phase difference between the two signals. In usual practice, the Q outputs from the two flip flops drive a charge pump circuit that takes the difference between the time that the upper and lower flip flops remain in the high stage, which is then low-pass filtered to provide a measure of the phase difference between the two signals. The advantage of the phase-frequency detector is that the measured phase does not depend on the duty cycle of the pulse trains, and since the sinusoidal signals have been converted to TTL level square waves by the Schmitt triggers, the measured phase also does not depend on the amplitude of the input signals, so long as they are sufficiently above the threshold of the Schmitt triggers. Finally, the phase-frequency detector enables rapid locking of the PLL even when the frequencies of the input signal and the reference signal are initially far apart. In the actual instrument, we use a legacy commercial phase-frequency detector chip (NTE Electronics NTE97414) because it was at hand. This chip is itself is a clone of the venerable Motorola MC4044 chip.

FIG. 2.

Schematic of the phase-frequency detector.

FIG. 2.

Schematic of the phase-frequency detector.

Close modal

The NTE974 provides pins to access the up and down counter outputs shown in Fig. 2 as well as an integral charge pump to which they can be connected. Instead of using the charge pump, however, we utilize the counter/timers in the MCU to determine the phase difference between the two input signals to the phase-frequency detector. To do this, one counter/timer in the MCU is connected to the “timer” output in Fig. 2 and is configured to count the number of periods of the DDS signal, triggering on every tenth period of this clock. During this time, two other counters/timers are configured to determine the period of time the up counter and down counter are high with a resolution of the MCU clock, which is 5 ns. To calculate the phase difference, the MCU calculates the difference between the up counts and down counts and divides it by the total time elapsed during 10 clock periods. Scaling this by 360 gives a direct measure of the phase difference in degrees. One characteristic of the phase-frequency detector is that it is supposed to track the phase difference over ±2π. In reality, we have found that the phase difference varies only between −360° and 0°. Since we prefer that the measured phase difference be between ±180°, we add or subtract 360° in the MCU code if the initial calculation falls outside this range.

Our typical tuning forks have resonant frequencies in the range of 30 kHz, corresponding to a period of approximately 30 µs, so the calculation of phase occurs roughly every 300 µs. This also then defines the time interval of both the amplitude and PLL PID loops, discussed in more detail below. The sampling period can, of course, be changed in software for transducers with different oscillation frequencies. In addition, due to noise associated with the sampling time, we also apply a software low-pass filter with a cutoff at about half the sampling frequency or about 1.5 kHz. With these parameters, our phase noise is about a few tens of millidegrees. This was tested by using two phase-locked Agilent 33500B15 waveform synthesizers as the signal and DDS inputs of the Schmitt triggers. When the controller is in fixed-frequency mode, the phase information is also available as an appropriately scaled analog signal through one output of a dual-output 14 bit digital-to-analog converter (DAC, Analog Devices AD5732R).

The software output of the phase-frequency detector is used as the error input to the PID controller that acts as the loop filter of the phase-locked loop. Since the phase-frequency detector locks to a zero phase difference between the transducer response and transducer drive, and one might need to lock to a different phase differential (e.g., 90° for an ideal forced harmonic oscillator20), a user selectable phase offset can be added to the error signal before it is presented to the PLL PID. The software PID algorithm then calculates the required change from the center frequency of the DDS in terms of a voltage, given the conversion factor (Hz/V) selected by the user. The corresponding voltage is also made available as an external output using the same DAC channel as for the phase, since it is not anticipated that the frequency deviation (significant when the PLL is engaged) and the phase information (significant in fixed frequency mode) would be required at the same time. The PID parameters, such as the proportional gain k and the integral and differential time constants τi and τd, can be changed on the fly from the host personal computer (PC) program. The software PID algorithm is based on the discussion of Aström and Murray.16 This is an incremental PID algorithm that implements a bumpless output so that transitions in and out of feedback do not result in large changes in the control signal. It also includes an anti-windup feature that limits the output so that a large error signal that persists for an extended period of time does not overwhelm the response of the PID. The algorithm that we use for the PLL loop filter as well as for amplitude control (discussed below) is identical to the PID algorithm that is used to control the z-piezo in our real-time SPM (RTSPM)4 controller. As the algorithm is discussed in detail in that paper (including a snippet of the critical code), we will not discuss it here.

The rms value of the input signal is read by the MCU through a 14-bit ADC (Analog Devices AD7367). If amplitude control is chosen, a software PID identical in form to the one discussed above is engaged to control the output drive so that the amplitude of the transducer response remains constant at a value specified by the user. The output of the amplitude PID is converted to a voltage through the second channel of the DAC; the output of the DAC multiplies the sinusoidal signal from the DDS to produce the drive signal for the transducer. This voltage is also made available as an output, as its varying value during a scan contains information about the dissipative forces between the tip and sample. If the amplitude PID is not engaged, the amplitude DAC channel outputs a user-selectable fixed dc voltage that controls the amplitude of the drive.

Q control is implemented as a simple analog circuit that can be taken in and out of the transducer drive circuit by the MCU at the option of the user. As shown in Fig. 1, its input is the transducer response and its output is summed or subtracted from the DDS drive before the amplitude multiplier. Figure 3 shows a schematic of the analog Q control circuit. It consists of two inexpensive op-amps (Texas Instruments LF35617) in series. The first op-amp, which is fed directly by the signal from the transducer, is configured as a variable gain inverting amplifier, with the gain controlled by a ten-turn potentiometer on the front panel of the instrument. Since the amplitude of the transducer response for our microscope is much larger than the amplitude of the drive, the maximum gain of this first stage amplifier is limited to be unity, but this, of course, can be changed easily for other experimental configurations. The second op-amp is configured as a so-called all-pass filter,18 which simply shifts the phase of its input signal with unity gain over a limited range of frequencies determined by the component values of the resistors and capacitor in the circuit. The phase change is controlled by varying the 10-turn potentiometer on the front panel, which is connected to the non-inverting input of the op-amp. Two configurations of this all-pass circuit can be used: one shifts the relative phase of the input and output from −180° to 0° and the other, obtained by switching the potentiometer and capacitor connected to the non-inverting input of the op-amp of the all-pass filter, shifts the relative phase between 0° and 180°. For our application, we are primarily interested in reducing the Q factor of our tuning-fork transducers, so we have implemented only one all-pass configuration. If the capability of both decreasing and increasing the Q factor is desired, one can simply switch the input amplifier of the Q control from an inverting configuration to a non-inverting configuration by means of either an electronic switch under control of the MCU or a front panel mechanical switch.

FIG. 3.

Schematic of the analog Q control circuit.

FIG. 3.

Schematic of the analog Q control circuit.

Close modal

When the instrument is turned on, the program on the MCU starts by configuring the input and output digital ports, initializing all the timers and counters, the UART interface, and the SPI, and then initializes the ADC, the DAC, and the DDS through the SPI. One channel of the DAC that is used for the amplitude output is configured for unipolar output over the range of 0–10 V, while the other one, used for the phase or frequency-shift output, is configured for bipolar output over the range ±10 V. It then goes into an infinite loop, where it first checks if the phase calculation timer interrupt has been triggered, and if it has, it calculates the phase difference, any incremental changes to the drive amplitude and DDS frequency if the respective PIDs are engaged, and it updates the respective DACs. It then checks to see if any commands from the host PC have come over the serial port, and if they have, it responds to them. For example, to change the DDS frequency, the host computer sends a command “FR;” followed by a numeric value, and it can also query the MCU for the amplitude, frequency, and phase. The speed of the MCU is fast enough that such interactions do not affect the performance of the instrument, yet enable changing parameters such as PID constants or the PLL center frequency on the fly.

When the amplitude control and PLL are not engaged, the instrument outputs a sinusoidal drive signal whose frequency and amplitude can be set from the user interface of the host program and measures the transducer response amplitude and phase difference on each timer interrupt cycle, which is roughly every 300 µs as mentioned above. For amplitude mode or phase mode SPM, one can then simply set the appropriate frequency and transducer drive amplitude and use either the amplitude or the phase analog output as the feedback signal for a SPM control program. In order determine the appropriate drive frequency and amplitude, the host PC program can scan a range of frequencies while measuring the amplitude and phase. An example of such a measurement performed on a quartz tuning fork transducer with this instrument is shown in Fig. 4. One can then easily identify the resonant frequency of the transducer and set the DDS frequency accordingly. Note that the phase in Fig. 4 jumps from −180° to 180° at f ∼ 32 766 Hz. This is an artifact due to the MCU code restricting the measured phase to be between ±180° as mentioned above.

FIG. 4.

Amplitude of oscillation and phase difference between the drive and response as a function of frequency for a commercial packaged quartz tuning fork. The Q of the tuning fork is about 30 000.

FIG. 4.

Amplitude of oscillation and phase difference between the drive and response as a function of frequency for a commercial packaged quartz tuning fork. The Q of the tuning fork is about 30 000.

Close modal

For frequency-shift mode SPM, the transducer controller should be run in PLL mode. The PC host program allows one to choose parameters of the PID algorithm that serves as the PLL loop filter. These are the proportional gain k and the integral and differential time constants τi and τd. These should be chosen to give the required response time without significant overshoot or oscillations. In order to get an idea of the value of these parameters, let us model the response of a PLL with only a PI controller for simplicity.

In order to analyze the performance of the phase-locked loop, it is useful to consider the entire PLL feedback loop.12 A PLL feedback loop in terms of Laplace transforms is shown schematically in Fig. 5. Here, the phase-frequency detector gives the difference in phase between the input signal θi and the DDS reference signal θDDS with gain kp. The PI controller acts on the phase detector output to give a sum of two terms, a proportional component with a gain of k, and an integral component with gain k/τi. The output of the PI controller is in terms of a voltage that serves as an input to a voltage controlled oscillator (VCO, the DDS in our case). A VCO can be thought of as an integrator, which takes a frequency and converts it to a phase to complete the loop. The gain k0 (Hz/V) of the VCO is set by the user from the host PC user interface. In the time domain, the feedback loop can be represented by the equation

θDDS(t)=kk0kptdt(θiθDDS)+kk0kpτitdttdt(θiθDDS),
(1)

where the first term represents the proportional contribution and the second term represents the integral contribution of the PI loop filter. Converting to Laplace transforms, and considering changes in the frequency of the input signal Δfi and DDS reference ΔfDDS, we have

ΔFDDS(s)=KΔFi(s)ks+k/τis2+kKs+kK/τi.
(2)

Here, K = k0kp, and ΔFDDS(s) and ΔFi(s) are the Laplace transforms of ΔfDDS(t) and Δfi(t), respectively.

FIG. 5.

Schematic of the phase-locked loop feedback.

FIG. 5.

Schematic of the phase-locked loop feedback.

Close modal

The response of the PLL to a step change in the input frequency Δfi(t) = Θ(t) is determined by the poles of the RHS of Eq. (2), which are

α,β=kK±kK1γ22,
(3)

where γ=21/kKτi. For a critically damped response, we would expect γ2 ∼ 1. Under these conditions, the DDS frequency changes exponentially to its new value in response to the change in input frequency with a time constant of 2/kK.

Now, kp is fixed by the gain of the phase-frequency detector, and k0 is determined by the PLL conversion factor (Hz/V) input by the user. Hence, the only free parameter determining the time constant is the proportional gain k. Consequently, we choose k to give the desired time constant and then determine τi from the requirement that γ2 = 1.

As an example, suppose we consider a time constant of 5 ms for the PLL to respond to a change in input frequency. Since the software phase detector gives its output directly in degrees, we take kp to be unity. The VCO (DDS) takes an input in volts and provides its output in Hz; hence, k0 has the units Hz/V or 360°/V-s. With a user selected VCO gain of 1 Hz/V, k0 = 360 and hence K = k0kp is also 360°/V-s. If we want the time constant 2/kK to be 5 ms, we then obtain k ∼ 1.11. This value of k and the requirement that γ2 ∼ 1 for critical damping then give us τi = 10 ms.

Figure 6 shows the analog output of the PLL to a step change of 1 Hz in the input frequency for the parameters calculated above. In addition, the differential time was set to 1 µs and so it did not affect the response. These data were obtained by using a frequency modulated Agilent 33 500B waveform synthesizer as the input signal, with a center frequency of 32 768 Hz. It can be seen that the time constant of the response is indeed around 5 ms, with a minimum amount of overshoot. However, there is a trade-off between the response time of the PLL and the noise level of the output. The noise level in Fig. 6 is roughly 200 mV pp or 40 mV rms, corresponding to a rms frequency noise of 40 mHz. For comparison, Fig. 7 shows data similar to those of Fig. 6, except that k has been changed from 1.11 to 0.55. As can be seen, the noise level is reduced, but the response time is also increased. For this demonstration, no special precautions were taken regarding noise: obviously, the best way to reduce the frequency noise and yet maintain the response time is to reduce the input noise from the transducer, which would reduce the phase jitter.

FIG. 6.

Response of the frequency shift of the DDS drive to a step change of 1 Hz in the input frequency, with the frequency PI parameters set to k = 1.11 and τi = 10 ms.

FIG. 6.

Response of the frequency shift of the DDS drive to a step change of 1 Hz in the input frequency, with the frequency PI parameters set to k = 1.11 and τi = 10 ms.

Close modal
FIG. 7.

Response of the frequency shift of the DDS drive to a step change of 1 Hz in the input frequency, with τi being the same as in Fig. 6, but with k = 0.55, showing the reduction in noise, but an increase in the rise time.

FIG. 7.

Response of the frequency shift of the DDS drive to a step change of 1 Hz in the input frequency, with τi being the same as in Fig. 6, but with k = 0.55, showing the reduction in noise, but an increase in the rise time.

Close modal

As expected from the characteristics of the phase-frequency detector, the PLL in our circuit rapidly locks on to the input frequency from the waveform generator even if the frequency of the input is far from the initial center frequency of the DDS. For a resonant transducer such as a quartz tuning fork, which has a strong phase dependence as well as a strong, non-monotonic amplitude dependence, getting the PLL to lock is not trivial, particularly for transducers with high Q. The characteristics of our transducer controller, however, make locking on to a resonant transducer fairly simple. One first uses the host PC program to acquire a resonance curve similar to the one shown in Fig. 4. This gives two important pieces of information: the frequency corresponding to the resonance (maximum in amplitude) and the phase shift corresponding to this frequency. For the curve in Fig. 4, these values are f0 = 32 765 Hz and θ ∼ −120°. One then enters f0 as the center frequency of the DDS on the user interface and −θ as the phase offset (note the negative sign), and the PLL will then lock immediately on the tuning fork resonance. No accuracy is required in entering these numbers, as the PLL will lock for a small range around these values. Indeed, one can choose at which point along the resonance the PLL locks by modifying the phase offset accordingly.

1. PID parameters for a resonant transducer

The determination of the PID parameters for the PLL discussed above is perhaps not directly relevant to controlling a resonant transducer because we have not considered the response of the transducer itself. In the terminology of feedback control, the transducer would be called the “plant.”16 Clearly, if the transducer responds on much longer time scales, this will affect the response of the PLL. In order to take into account, the usual procedure is to model the plant dynamics. Our focus here is to make approximations to obtain an understanding of how the transducer characteristics, particularly the Q, affect the PLL response. A more accurate model would require numerical modeling and would not necessarily improve our physical intuition. We will consider a quartz crystal tuning fork in our analysis as that is the transducer we use in our experiments, although the analysis can be extended to any resonant transducer.

The quartz tuning fork transducer can be modeled as a series LCR circuit with a capacitor Cpar in parallel that takes into account line capacitance and other effects, as shown in Fig. 8.19 The contribution of Cpar can be taken into account by a suitable capacitive compensation circuit, which, in our microscope, is incorporated into the current-to-voltage preamp. Consequently, for simplicity, we shall simply consider the series LCR circuit. The complex impedance of this circuit is given by

Z=R+iωL1ω02ω2,
(4)

where ω0=1/LC is the resonant frequency of the tuning fork and ω = ωDDS is the drive frequency. The phase difference between the applied voltage and the current through the tuning fork is given by

tanϕ=L(ω02ω2)ωR=Q(ω02ω2)ω0ω2Q(ω0ω)ω0,
(5)

where the quality factor of the tuning fork Q = ω0(L/R), and in the last step, we have made the approximation ωω0, i.e., the drive frequency is close to the resonant frequency. Note that the phase difference between the drive and response is 0 on resonance, which is different from what one expects from a forced harmonic oscillator (90°).20 This is because we are measuring current instead of charge. The phase difference is therefore a function of the drive frequency, the resonant frequency, and the Q, ϕ(ω, ω0, Q).

FIG. 8.

Equivalent LCR circuit of a quartz crystal tuning fork. Cpar is the parallel line capacitance.

FIG. 8.

Equivalent LCR circuit of a quartz crystal tuning fork. Cpar is the parallel line capacitance.

Close modal

The phase difference replaces the corresponding quantity in Eq. (1),

θ(t)=kKtdtϕ(ω,ω0,Q)+kKτitdttdtϕ(ω,ω0,Q),
(6)

where we have replaced θDDS with just θ to simplify the notation. Taking two derivatives of this equation gives

dωdt=kKϕωωt+kKτiϕ(ω,ω0,Q)

under the assumption that ω0 is a constant. Here, ω = /dt. The derivative of ϕ with respect to ω is given by

ϕω2Qω04Q2(ωω0)2+ω02.

If Q is small (∼1000) with respect to ω0 (∼200 000 Hz for a typical tuning fork), and we are close to resonance, we can then ignore the first term in the denominator above in comparison to the second term. Thus,

ϕω2Qω0.

With this, our differential equation becomes

dωdt1+2kKQω0=kKτitan12Q(ω0ω)ω0

so that we have

ωiω(t)dωtan12Q(ω0ω)ω0=tkKτiω0ω0+2kKQdt.

For small arguments of the arctan function in the denominator of the LHS of the equation above, i.e., when we are close to resonance, we can approximate the integral to obtain

lnω(t)ω0ωiω0=2QkKtτi(ω0+2QkK).

Hence, starting at a frequency ωi, the PLL drive frequency relaxes toward the resonant frequency of the transducer ω0 as

ωDDS=ω(t)=ω0+(ωiω0)etτ,

where the relaxation time τ is given by

τ=τiω0+2QkK2QkK.
(7)

Note that the relaxation time depends not only on the PID parameters but also on the characteristics of the transducer (Q, ω0). Consequently, the same parameters that give the desired response when the input to the PLL is from a linear oscillator such as a waveform synthesizer will not, in general, give the desired response when applied to a resonant transducer, particularly when the resonant transducer is a custom assembled tuning fork with an etched tip, whose characteristics will change from one transducer to another. For very high Qs, the response is determined solely by the integral time constant of the PID controller. More realistically, say, we have a Q of 1000 with a resonant frequency of f0 = 32 kHz (ω0 ∼ 200 000). With a conversion factor of 1 Hz/V, K ∼ 360, and putting k ∼ 1, 2QkK ∼ 360 000, which is comparable to ω0, so that the response time is determined by the PID parameters as well as the characteristics of the transducer. Because it is difficult to determine the characteristics of a hand-built tuning fork transducer a priori, we have implemented a PID tuning algorithm in the host PC program user interface that enables the user to tune PID parameters for a specific tuning fork to obtain the desired response. This can be seen in the lower left side of the user interface shown in Fig. 9. To do this, we simply modulate the center frequency of the DDS periodically at a relatively low frequency (1 Hz or so) and monitor the analog frequency shift output when in PLL mode on an oscilloscope, adjusting the PID parameters to obtain the desired response time, starting with estimates based on Eq. (7).

FIG. 9.

Screenshot of the user interface of the control program on the host PC.

FIG. 9.

Screenshot of the user interface of the control program on the host PC.

Close modal

The control algorithm for the amplitude of oscillation of the transducer is identical to the PID controller for the PLL with similar adjustable parameters. The analysis in terms of controlling a resonant transducer is similar to the discussion for the PLL above, and we will not discuss it here. Amplitude control is usually employed when using either the phase or the frequency shift as the feedback signal for controlling the z-piezo of a SPM. For our earlier hybrid analog–digital PLL,13 which utilized an analog multiplier as the phase detector, changes in the amplitude of the transducer response manifest themselves as unwanted signatures in the phase signal (and hence the frequency shift when in PLL mode). Consequently, there is an interaction between the amplitude PID and the phase signal. The current instrument does not suffer from this problem, as it uses a phase-frequency detector that is insensitive to the amplitude of the transducer response. Adjustment of the amplitude PID is, therefore, less critical. In practice, we have identified PID parameters that work by trial and error; more accurate tuning can be done by modulating the amplitude set point as discussed for the PLL above.

The instrument that we have developed has the capability of engaging or disengaging active Q control from the host PC panel. Once engaged, Q control is tuned using two 10 turn potentiometers on the front panel, one for controlling the amplitude and the other for the phase (see Fig. 3). As we noted earlier, we have only implemented Q control for reducing the Q of our tuning forks, since that is what we usually need to do in our experiments, but the circuit for increasing Q is easily realized as discussed above. In order to adjust the Q, we first fix the frequency of the DDS at the resonant frequency of the tuning fork. We then set the amplitude potentiometer somewhere in the middle of its range and then adjust the phase potentiometer to obtain a minimum in the amplitude of the tuning fork response. We can then use the amplitude potentiometer to adjust the Q to the desired value. Figure 10 shows the results of adding two different levels of Q control. The red curve is the same curve for the commercial packaged tuning fork shown in Fig. 4 (i.e., without Q control), and the two other curves show two different levels of Q control, obtained by adjusting the amplitude potentiometer as described above. Note that for smaller Q values, there is an apparent shift in the resonance frequency that is accompanied by an asymmetry in the resonance curve, both of which can be compensated by appropriately adjusting the capacitive compensation in the tuning fork current preamp. One can easily go from initially very high Qs to Qs of a few hundreds. This is particularly useful when scanning in amplitude mode but can also be used when using the PLL.

FIG. 10.

Demonstration of Q control. The red curve is the resonance curve of the commercial packaged tuning fork shown in Fig. 4 without Q control; the other curves are with varying levels of Q control. Curves are scaled to their respective maxima.

FIG. 10.

Demonstration of Q control. The red curve is the resonance curve of the commercial packaged tuning fork shown in Fig. 4 without Q control; the other curves are with varying levels of Q control. Curves are scaled to their respective maxima.

Close modal

As an example of the PLL in operation, Fig. 11 shows an image of a part of a regular array of permalloy disks fabricated by electron-beam lithography. This image was taken with the new PLL in amplitude mode on our home built scanning probe microscope with our custom RTSPM4 control program.

FIG. 11.

Image of a patterned permalloy disk array taken with the new PLL in amplitude mode with the RTSPM4 control software and our home-built scanning probe microscope. The scan range is 5 μm × 5 μm, the full z range is 96 nm, and the spacing of the disks is about 1 μm.

FIG. 11.

Image of a patterned permalloy disk array taken with the new PLL in amplitude mode with the RTSPM4 control software and our home-built scanning probe microscope. The scan range is 5 μm × 5 μm, the full z range is 96 nm, and the spacing of the disks is about 1 μm.

Close modal

In summary, we have demonstrated a relatively inexpensive resonant transducer controller for non-contact scanning probe microscopy applications that enables amplitude mode, phase mode, and frequency shift mode SPM with Q control. The instrument can easily be controlled by any computer program through a serial interface and provides analog outputs for important parameters that can be used by SPM control programs.

The author thanks Aaveg Aggarwal for help with some of the electronics, Dr. Zhifu Liu for obtaining the image in Fig. 11, and Professor Udo Schwarz and Dr. Omur Erdinc of Yale University for providing suggestions about Q control. This research was supported by the U.S. Department of Energy, Basic Energy Sciences, under Grant No. DE-FG02-06ER46346.

1.
Scanning Probe Microscopy
, edited by
S. V.
Kalinin
and
A.
Gruverman
(
Springer
,
2007
).
2.
O. E.
Dagdeviren
,
J.
Gštzen
,
H.
Hšlscher
,
E. I.
Altman
, and
U. D.
Schwarz
,
Nanotechnology
27
,
065703
(
2016
).
3.
F. J.
Giessibl
,
Appl. Phys. Lett.
76
,
1470
(
2000
).
4.
V.
Chandrasekhar
and
M. M.
Mehta
,
Rev. Sci. Instrum.
84
,
013705
(
2013
).
5.
See http://www.microchip.com for Microchip Technology, Inc.
6.
See http://www.olimex.com for information about PIC32 evaluation boards..
7.
See http://www.analog.com for information about the various Analog Devices chips used in this instrument.
8.
See https://www.analog.com/media/en/training-seminars/tutorials/MT-086.pdf for Fundamentals of Phase Locked Loops (PLLs), MT-086 Tutorial.
9.
See http://www.analog.com/static/imported-files/tutorials/MT-085.pdf for Fundamentals of Direct Digital Synthesis (DDS), Analog Devices MT-085 Tutorial.
10.
See http://www.freepascal.org for Free Pascal: Advanced open source Pascal compiler for Pascal and Object Pascal.
11.
See http://www.lazarus.freepascal.org for the Lazarus Integrated Development Environment for Free Pascal.
12.
P.
Horowitz
and
W.
Hill
,
The Art of Electronics
, 2nd ed. (
Cambridge University Press
,
1989
).
13.
M. M.
Mehta
and
V.
Chandrasekhar
,
Rev. Sci. Instrum.
85
,
013707
(
2014
).
14.
See http://www.nteinc.com for information about the NTE974 chip.
15.
See http://www.keysight.com for further information about the Agilent waveform generator.
16.
K. J.
Aström
and
M. R.
Murray
,
Feedback Systems: An Introduction for Scientists and Engineers
(
Princeton University Press
,
Princeton
,
2008
).
17.
See http://www.ti.com for information about the Texas Instruments chips used in this instrument.
18.
Operational Amplifiers, Design and Applications
, edited by
J. G.
Graeme
,
G. E.
Tobey
, and
L. P.
Huelsman
(
McGraw-Hill Book Company
,
New York
,
1971
).
19.
A detailed discussion of tuning fork sensors for scanning probe microscpy, and in particular in the so-called qPlus configuration can be found in a recent review article by
F.
Giessibl
,
Rev. Sci. Instrum.
90
,
011101
(
2019
).
20.
D.
Kleppner
and
R. J.
Kolenkow
,
An Introduction to Mechanics
(
McGraw-Hill
,
1973
).