An open-source high-frequency lock-in amplifier

The lock-in amplifier (LIA) is an invaluable tool in scientific instrumentation¹ allowing the extraction of weak signals from noisy backgrounds, even where the amplitude of the noise is much greater than the signal.² First described in 1941, early LIAs were based on heaters, thermocouples, and transformers.³ More modern LIAs have been fully digital^4–7 or implemented on field programmable gate array (FPGA) devices,^8–14 which are able to exceed the performance of their analog counterparts.¹⁵ However, the cost of modern LIAs may prove prohibitive, particularly in cases where large numbers of input channels are required. By employing Red Pitaya hardware, we are able to define an open-source LIA solution that is comparable with considerably more costly approaches.

Characterized by a wide dynamic range and the ability to extract signal from noisy environments,¹⁶ LIAs are phase sensitive detectors¹⁷ due to their operating principles. A reference signal in the form of a sinusoidal wave is generated either internally by the LIA itself, along with a cosinusoidal wave, or externally by some other sources that can also be manipulated to form a cosinusoidal reference. This reference is multiplied by the input signal¹⁸ that carries the desired data modulated at the reference frequency.¹⁹ A low pass filter is then used before outputting the signal. In this way, the LIA amplifies and outputs the component of the input signal that is at the reference frequency, attenuating noise at other frequencies.²⁰ Components out of phase with the sine reference will also be attenuated due to orthogonality of the sine and cosine functions of equal frequency,²¹ and hence, the LIA is considered phase sensitive.²² Components in phase with the sine function will result in a nonzero value in the X output, while those in phase with the cosine function will produce a nonzero value in the Y output. X and Y can be combined by $R=X2+Y2$ to provide a magnitude value,²³ while phase $ϕ=arctanYX$⁠.

FPGAs offer easily implementable microcircuitry design via the use of hardware description language (HDL) such as Verilog or VHDL. A broad range of applications can be realized using these devices,²⁴ including LIAs without recourse to detailed knowledge of microelectronics.²⁵ 

The Red Pitaya STEMlab 125-14 is a single board computer (SBC) with an integrated FPGA in the form of a Xilinx Zynq 7010 SoC,²⁶ allowing for the implementation of reprogrammable microarchitecture that would otherwise necessitate dedicated hardware. The reprogrammability²⁷ of this FPGA makes it applicable for the LIA functionality described here and allows for further expansion and modification by end users. Two DC coupled analog inputs are available in the form of user selectable ±1 V or ±20 V, 125 MS/s analog-to-digital converters (ADCs—Linear Technologies LTC2145CUP-14²⁸) with an input impedance/capacitance of 1 MΩ/10 pF.

In this article, we detail an LIA which we have implemented on the STEMlab’s FPGA chip, along with open source²⁹ operational and data transfer software developed specifically for this application. We demonstrate that this device shares many capabilities with more expensive alternatives such as a sweepable internal signal generator, single or dual input/output modes, wave form control, and the ability to increase the number of available inputs and outputs by interfacing across multiple STEMlab units.

Comparison is made with the Zurich Instruments HF2LI LIA, which is specified for operation up to 50 MHz demodulation frequency.³⁰ While an extensive software application is provided with the HF2LI, the open source nature and readily available software and hardware of the LIA presented here allow for an attractive option where cost is a consideration. Research into low-cost FPGA based LIAs has produced a number of alternatives,²⁵ including high resolution designs operating at up to 6 MHz demodulation,^31,32 and simulations have been presented for a high frequency LIA based on the Red Pitaya STEMlab.³³ Typically, FPGA LIAs have been developed with specific experimental objectives.^13,14,34 The STEMlab is the basis for a range of related measurement instrumentation from PyRPL, including an LIA.^35–37 A low cost FPGA-based LIA has also been developed which operates at a low demodulation frequency,³⁸ and FPGA-based LIAs have been compared with analog devices in terms of signal accuracy.³⁹ However, we believe that this article is the first to characterize a high frequency, open source LIA. The open source code may lead to a range of future uses in research, education, and industry.

The FPGA system design and implementation was performed using software provided by the manufacturer of the FPGA, Xilinx. A simplified version of the design circuitry block diagram can be seen in Fig. 1. Signals received by the ADCs are passed to the processing blocks where they are multiplied by the reference signal [which is generated internally by direct digital synthesis (DDS)] and filtered using a single pole infinite impulse response (IIR) filter. The resulting output is written to the SBC’s random access memory (RAM) via the FPGA’s memory interface block. This data is then written to a ramdisk file also contained within the STEMlab’s RAM, alleviating high read/write workloads which were observed to cause critical failures of the SD card. The data are also passed to the on-board digital-to-analog converters (DACs) along with the reference signal that is used to modulate the desired signal. This reference can be extracted via the DAC output for external use.

Data retrieval from the STEMlab to a host computer can be achieved via the DACs that are provided with SubMiniature version A (SMA) connections for output to an oscilloscope. These DACs have 14-bit resolution combined with 125 MS/s data rate. Non-offset, digital amplification of up to 2000 times the raw output is available. However, noise introduced by the DACs makes the output undesirable in cases where small changes in signal intensity are to be detected. Alternatively, data may be transferred to a host personal computer (PC) via file transfer from the STEMlab’s RAM. This produces low noise data but can only be performed on the entirety of the LIA’s allocated storage space of approximately 65 megabytes (MB). While this process may last for tens of seconds, all data (X, Y, R, and ϕ) for both output channels are received simultaneously. Further limitations include the inability to operate using an external lock-in reference, cross talk that can occur between the two input channels and no facility for subtraction of channels (e.g., A-B). Due to the programmable nature of the STEMlab, end users are able to implement their own data transfer methods, which may be shown to alleviate some or all of these limitations.

While the FPGA is responsible for signal processing and data transfer, parameter setting takes place on the STEMlab’s Linux SBC. This device is packaged along with the FPGA on the STEMlab board, allowing the user to operate the Red Pitaya LIA (RePLIA) or any other custom FPGA application entirely using the STEMlab itself. Parameter setting and system control are performed using C and Python codes written specifically for use with the LIA. These codes may be accessed via secure shell (SSH) or a terminal emulator but, in practice, are accessed via a Java-based graphical user interface (GUI) on a client computer that allows the user to largely ignore the STEMlab’s Linux element. This open-source GUI allows for the setting of all available RePLIA parameters.

Data were extracted from both LIAs via Ethernet connection. In the case of the RePLIA aboard the STEMlab, this avoided noise from its DACs which were found to increase noise by up to three orders of magnitude.

Noise for both LIAs during operation was measured at various demodulation frequencies with no input signal present and with a constant amplitude signal produced with an Agilent N5172B EXG vector signal generator. Similarly, noise was measured while varying the time constant of the LIAs with the demodulation frequency fixed at the value determined to be the least noisy by the previous method. As with the input noise, these data are presented after a fast Fourier transform (FFT).

Passbands for each LIA at various demodulation frequencies were obtained by applying a constant amplitude signal at the specified demodulation frequency. This signal was then combined with a sweep between the minimum and maximum frequencies passing through the demodulation frequency, with a sweep time of 10 s.

The HF2LI provides a built in input noise measurement protocol. The experimental conditions detailed in the HF2LI user notes were replicated,³⁰ and the input noise was measured. Noise was collected while the inputs were terminated for periods of 1, 10, and 100 s. This noise was then subjected to a FFT, and the noise level was assessed and compared with the manufacturer’s stated input noise level of 5 nV/√Hz at 1 MHz demodulation for the output frequencies greater than 10 kHz.⁴⁰ 

Optimal operational parameters were deduced by examining the output of the RePLIA at varying demodulation frequencies and time constants. The optima chosen were those which resulted in the lowest output noise level. This behavior was examined both with an applied signal and with the terminated inputs. The RePLIA maintains capability over a wide range of demodulation frequencies (10 kHz–50 MHz), which were also characterized, but figures are quoted with respect to optimal parameters unless otherwise stated.

Figure 2 shows input noise spectral density for both LIAs at 1 s, 10 s, and 100 s collection periods. Increasing collection time t was expected to produce a $t$ decrease in noise. Both LIAs remained within close agreement of this prediction after a 100 s collection time [Fig. 2(c)]. Noise levels were obtained by taking an average of base-lined data from each LIA at the relevant collection time. In Fig. 2(a), the data for 1 s of collection time has been zero padded, by adding 4 s worth of zeros, to reduce the width of the frequency bins. These averages produce figures of 89, 21, and 6 nV for the RePLIA for the collection times of 1, 10, and 100 s, respectively, corresponding to the sensitivities of 89, 66, and $60nV/Hz$⁠. When the RePLIA was operated using the conditions stipulated for measurement of the HF2LI input noise, the noise levels are 131, 133, and $130nV/Hz$⁠. This shows that the optimal operating parameters for the HF2LI differ from those appropriate to the RePLIA. It should be noted that the manufacturer specified sampling rate for the HF2LI limits the span of the FFT output to 120 Hz. Frequencies beyond this limit can be found in the HF2LI’s user manual in section 8.4 on page 665.³⁰ A wider output frequency plot for the RePLIA can be found in  Appendixes A and  B (Fig. 13).

The noise spectrum for the HF2LI [Fig. 2(b)] shows greater noise below 80 Hz and lower noise at higher output frequencies. By contrast, the RePLIA shows a higher level of noise that is largely steady up to 120 Hz [Fig. 2(a)] output frequency.

Figure 3 shows FFTs of the RePLIA output collected for 100 s at a range of demodulation frequencies, with time constants optimized for the relevant demodulation period (see  Appendixes A and  B). There is a marked difference in noise at demodulation frequencies below 100 kHz, although above this threshold the noise is roughly constant.

Output from the RePLIA digital-to-analog converters (DACs) was also produced (see  Appendixes A and  B), showing a constant noise level at frequencies below 100 kHz. Although this noise level is several orders of magnitude greater than that incurred in data extracted via the Ethernet connection, this may be an acceptable trade-off in certain cases. This consistency suggests that noise inherent to the DACs is the limiting factor when obtaining data using this method, although this noise can be reduced as described in Ref. 28. Signal-to-noise as measured at the DACs increases with an increase in the DAC multipliers, plateauing toward saturation of the RePLIA’s outputs (see Fig. 7 in  Appendixes A and  B).

Figures 4(a) and 4(b) show the shape of LIA passbands when modulating at varying frequencies with time constants optimized for each frequency. The HF2LI demonstrates a narrower passband with less transmission at unwanted frequencies. These passbands are shown to be approximately Lorentzian in line shape with a full-width half-maxima of 2.6 kHz for demodulation frequencies above 100 kHz (see  Appendixes A and  B), and they begin to reduce in intensity above 30 MHz demodulation with the HF2LI, whereas the output is consistent up to 50 MHz demodulation with the RePLIA. Figure 5(c) shows the normalized output at megahertz demodulation frequencies for both LIAs. The half power point is indicated (⁠$Vmax2$⁠, where V_max is the peak voltage output), which for the RePLIA is encountered at a demodulation frequency of around 60 MHz, which is close to half of the device’s 125 MHz sample rate, as can be expected from the Nyquist sampling theorem.⁴¹ 

Linearity of the output relative to the input is demonstrated in Fig. 5. Input voltages were varied, and the resultant DAC output voltage were measured for both the ±1 V and ±20 V input ranges. Linearity is observed over ±700 mV and ±1100 mV, respectively. Outside these regions, the STEMlab’s input, having only 14 bits, introduces significant nonlinearities, as does the improper impedance matching of the RePLIA’s inputs.

The RePLIA performs lock-in amplification at frequencies up to 50 MHz, with an input noise level of 90 nV/√Hz. The respective figures from the Zurich Instruments HF2LI (50 MHz demodulation with 5 nV/√Hz input noise) show that the FPGA LIA detailed in this article is an open source alternative.

We thank Ben Breeze and Matt Dale for assistance and advice. This research was funded by Bruker Biospin and the Engineering and Physical Sciences Research Council (EPSRC) via Grant No. EP/L015315/1, and G. W. Morley was supported by the Royal Society.

The RePLIA was operated in a dual channel input mode with the output producing amplitude data. These data were collected at a rate of 20 ksamples/s. It is important to note that in setting a sample rate, the actual rate per sample will be $1$/$8$ of that set, as the set rate includes one sample per output channel per time increment (2 input channels comprising R, X, Y, and ϕ for each input channel). This sample rate is dependent on both the system being measured and the hardware over which data are transmitted but can be set by the user to any rate within the sample rate range of the STEMlab, although this sample rate may ultimately affect the accuracy of resultant signals. When obtaining data via the DAC outputs, collection has been performed by a Pico Technology Picoscope 4424 digital oscilloscope. The Picoscope and DAC outputs were also used when determining the time constants for the RePLIA. Data extracted via the RePLIA’s Ethernet port were converted to millivolt values by dividing the actual numerical value by 2.1 × 10⁶, a conversion factor that was determined by comparing the Ethernet values with the corresponding values produced at the DACs with no DAC multiplication applied.

The Zurich Instruments HF2LI was operated according to the instructions laid out in section 3.5 of the HF2 User Manual,³⁰ using the parameters in Table I.

The time constants detailed in Table II were used for measurements made with the RePLIA. For frequencies in between those listed, the time constant corresponding to the lower frequency was used. Minimum time constants τ_min have been determined by τ_min = 10/f_mod, where f_mod is the demodulation frequency. This ensures that for a given time constant, 10 modulation periods or more elapse during the time constant. The actual time constants used were chosen based on the line shape of passbands as seen in Fig. 5(a) in the main text. Time constants were made as large as possible without distortion of the Lorentzian line shape of these passbands.

Figure 6(a) shows an FFT of the terminated input data at 10 kHz. These data were extracted from the digital-to-analog converters (DACs), with the noise level indicating that the DACs themselves are the most significant source of noise. Contrasting this with Fig. 3, where we see that without DAC noise, the varying demodulation frequency causes a distinct change to noise levels. Figure 7(b) demonstrates an increase in the output signal to noise ratio with increasing demodulation frequency.

Figure 7(a) shows the effect on an FFT while varying the DAC amplification multiplier, with the extremes in this range shown in Fig. 7(b). There is no significant difference in noise level between these extremes. Although Fig. 7(c) shows that an increase in the DAC multiplier does improve the signal-to-noise ratio, care should be taken not to saturate the STEMlab’s 1 V maximum output.

Figure 8 demonstrates the effect of the time constant on the shape of the passband for a given demodulation frequency, with 500 kHz used as an example. Excessively long time constants produce a narrower passband at the expense of line shape; fringes appear at output frequencies close to but greater than the demodulation frequency, leading to the distortion of output signals. Shorter time constants produce a more consistent line shape at the cost of passband linewidth. Further to this, extremely short time constants (below those detailed in Table II) are unable to detect changes on time scales appropriate to the demodulation frequency. In terms of software, the time constant can be set to any value above 9 × 10⁻⁶ s. However, appropriate setting of the time constant is necessary to ensure the correct representation of output signals, and an understanding of the physical nature of systems being measured is also necessary for accurate results.

Figure 9 shows FFTs of low demodulation frequency data at varying collection times. Certain frequency elements are evident throughout, which are not evident at higher demodulation frequencies. These components are visible in data extracted both via the DACs and via the STEMlab’s Ethernet port.

Figure 10 shows the effect of time constant on noise. Although noise decreases with longer time constants, signal distortions as seen in Fig. 8 limit the choice of time constant used.

Figure 11 shows the measured 10 MHz passband of both the RePLIA and HF2LI along with a Lorentzian fit of the data, demonstrating a rough conformation with such a line shape. These data give a full-width half-maximum of 2.6 kHz for the RePLIA and 2 kHz for the HF2LI. Figures 8 and 9 both contain artifacts arising from the single order filter. Increasing the order of the filter may reduce the prominence of these features, although experiments with the HF2LI suggest that such benefits may be marginal.

Higher noise at lower frequencies, as seen in Fig. 3, is consistent with flicker noise of the input stage, as demonstrated in Fig. 12, in that it is of the form of 1/f.

Largely, the RePLIA is limited by the factors introduced by the STEMlab’s hardware and software. The maximum sample rate of the demodulated signal corresponds to the output sample rate of the STEMlab (125 MS/s) when using the DAC outputs. However, this sampling rate is limited instead by the network connection when extracting data via the Ethernet adapter.

Mathematical operations such as A_out = A_in − B_in have not been implemented at the current time, although this is entirely plausible by adding such functionality within the FPGA code.

Power consumption for the RePLIA is 4 W when idle and <6 W during lock-in operation.

Cross talk between input channels results in a signal 0.3% of the input signal amplitude reflected in the secondary input. The output voltage range is limited by the board to ±1 V.

Figure 13 represents the same data as Fig. 2 in the main text, but as plain FFTs of noise data as opposed to noise spectral density.

The RePLIA has been used for magnetometry using an ensemble of nitrogen vacancy centers in diamond. We intend to apply this technique to magnetocardiography, where it would be preferable to use approximately 200 sensors, requiring 100 dual channel lock-in amplifiers.⁴²