This paper describes a novel miniature microcontroller based curve tracing circuit, which was designed to monitor the environmental effects on Silicon Carbide Junction Field Effect Transistor (SiC JFET) device performance, while exposed to the low earth orbit environment onboard the International Space Station (ISS) as a resident experiment on the 7th Materials on the International Space Station Experiment (MISSE7). Specifically, the microcontroller circuit was designed to operate autonomously and was flown on the external structure of the ISS for over a year. This curve tracing circuit is capable of measuring current vs. voltage (I-V) characteristics of transistors and diodes. The circuit is current limited for low current devices and is specifically designed to test high temperature, high drain-to-source resistance SiC JFETs. The results of each I-V data set are transmitted serially to an external telemetered communication interface. This paper discusses the circuit architecture, its design, and presents example results.

The International Space Station (ISS) is currently being used for in-situ testing of materials and devices in the low earth orbit (LEO) environment.1 As a test facility, the ISS has many challenging environments effects such as thermal profiles, atomic oxygen presence, vacuum, and radiation. Developers of materials and devices have found great value in evaluating performance in-situ using the ISS operating environment. The current vs. voltage (I-V) curve tracing circuit in this paper was designed to support an endurance test experiment of Silicon Carbide Junction Field Effect Transistors (SiC JFETs) in the ISS environment. The experiment consisted of two SiC JFETs as the devices under test (DUTs); one in experimental high temperature packaging2 and one in a commercial room temperature package. The measurements performed are drain-to-source current (IDS) vs. drain-to-source voltage (V DS) curves at various gate-to-source voltages (V GS).

The test platform onboard the ISS is a Materials on the International Space Station Experiment (MISSE) Passive Experiment Container (PEC). This suitcase like container is shown in Figure 1. Figure 1(a) shows the MISSE7 PEC mounted on an Express Logistics Carrier (ELC) on the ISS. Figure 1(b) shows the many types of experiments mounted on the PEC with the SiC JFET experiment outlined. The experiment was contained in a 2 mm thick aluminum box that provides some radiation shielding and exposed the electronics to a predicted yearly total ionizing dose of approximately 170 rad Si.3 The MISSE7 experiment set provided +5 Volts Direct Current (VDC) power and a serial communications interface for telemetry data. The MISSE7 PEC also has heaters onboard to maintain the temperature of the electronics to a range of −40 °C to +50 °C for survivability.

FIG. 1.

(a) MISSE7 PEC mounted the ELC. The experiment is shown outlined in (b).

FIG. 1.

(a) MISSE7 PEC mounted the ELC. The experiment is shown outlined in (b).

Close modal

The SiC JFETs were developed at the NASA Glenn Research Center and are capable of surviving harsh environments with a temperature range of −125 °C to +600 °C. The transistors are small signal JFETs used within instrumentation circuits such as amplifiers and digital logic gates.4 These transistors have been demonstrated operating for extended periods of time (>10 000 h) at 500 °C and in digital logic integrated circuits (ICs) operating for over 3000 h at 500 °C.5 The SiC JFETs under test have a large drain to source channel resistance greater than 10 KΩ when fully on. These JFETs also need a V GS of −10 V or greater to fully turn off the transistors, and must maintain a zero to negative gate bias so as not to damage the pn junction of the JFET gate. In addition, V DS needs to be near +15 V to reach the saturated drain-to-source current (IDSS). As only a +5 VDC power supply was provided to experimenters, ±15 V supplies needed to be designed and incorporated into the experiment circuit to generate the needed V GS and V DS voltages.

The physical layout for the MISSE7 experiment set allotted a footprint area of approximately 10 cm × 20 cm for the SiC JFET experiment. The experiment circuit board also supported electronics for two additional experiments: the atomic oxygen fluence monitor and a gas sensor. Although these experiments will not be discussed in this paper, they added to the size constraints of the overall design. Since two transistors were under test, it was decided to construct two independent test circuits to include the ±15 V supplies for each test circuit. This allowed redundant JFET testing, since both circuits have similar JFETs with different packaging. In the event of a single circuit failure, some data would be recovered from the redundant circuit.

The physical size constraints of the experiment necessitated a new circuit design for transistor curve tracing, which miniaturizes the curve tracing function. This paper will present a novel miniature standalone transistor curve trace circuit that operates from a single DC voltage source and includes all needed support circuitry. The circuit uses selected integrated circuits with a successful ISS flight history and utilizes a novel load configuration to account for the shortcomings of these components. Designed to use minimal physical space and mass, it is ideal for a space flight test. The circuit enabled the first space flight test of high temperature SiC JFETs while successfully operating on board the International Space Station from November 2009 to May 2011.

A curve tracing circuit exercises an electronic device through its operational region. This is done by placing a variable electrical load either in series or parallel with the DUT. By varying the electrical load, the DUT is swept through varying operating regions. The variable load can consist of a bank of resistors, an active power source or a transistor as shown in Figure 2. Resistor banks being the simplest form of implementation are passive loads that provide fixed data points of operation, as shown in Figure 2(a). Unfortunately, these circuits increase footprint with the number of desired data points. As well as increased size, these circuits are also not flexible due to the resistors being fixed values. Active power sources or sinks such as the voltage controlled current source shown in Figure 2(b) are flexible, but use additional power, take up space, and can potentially damage the DUT. The third option, the MOSFET, is an ideal choice as a passive load that acts as a variable resistor with system capability limiting resolution in modulating the DUTs gate voltage shown in Figure 2(c).

FIG. 2.

Variable load options for performing a curve trace on the DUT. (a) shows a resistor bank, where a resistor can be switched in for each point in the curve. (b) shows a voltage controlled current source, where the number of points on the curve is determined by the resolution of the source and controller voltage. (c) shows a MOSFET acting as voltage controlled variable resistor, where the number of points on the curve is determined by the resolution of the controller voltage.

FIG. 2.

Variable load options for performing a curve trace on the DUT. (a) shows a resistor bank, where a resistor can be switched in for each point in the curve. (b) shows a voltage controlled current source, where the number of points on the curve is determined by the resolution of the source and controller voltage. (c) shows a MOSFET acting as voltage controlled variable resistor, where the number of points on the curve is determined by the resolution of the controller voltage.

Close modal

I-V curve tracing circuits for in-situ device characterization are not new, a number of solar cell I-V curve tracing circuits have been demonstrated on flight platforms. Solar cell I-V curve tracing circuits are needed to characterize device performance degradation in the space environment, and have been demonstrated on MISSE5, which represents the state-of-the-art in space photovoltaic cell curve tracing measurements.6 MISSE5 used a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) as the load with solar cells as the DUT. In addition to the choice of operating electronic load for the curve trace circuit, the DUT itself may also add complexity to the curve trace circuit. For instance, the nature of two-port solar cells differs from transistors in that they are two port devices as opposed to three port and require the generated power to be dissipated, which is not required for transistors. The third port of the transistor complicates the design by adding another port of the DUT to control. Transistor I-V curve tracing circuits have been demonstrated in the laboratory, but these circuits are large because they often depend on external laboratory power supplies and signal generators.7,8

A number of constraints were taken into consideration during the circuit design. The radiation environment dictated most choices in the design. Component selection was the primary method of mitigating radiation effects on the circuit coupled with some simple design rules. The authors had success with an extended flight of solar cell I-V circuitry on MISSE5 and these same circuit components were chosen for the design of this experiment. The central components of this design were the Silicon Laboratories C8051F121 microcontroller and the LT1013/1014 operational amplifiers. The microcontroller has onboard digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) with multiplexers to provide numerous inputs.9 The LT1013 op amp is a precision amplifier based on bipolar technology10 that was shown to perform well as a component of the forward technology solar cell experiment instrumentation circuitry during extended, an extended flight on the ISS.11,12

Together with the chosen components, two design rules were employed in the op amp measurement circuitry. These rules were used to limit errors that might be introduced from increasing bias currents due to radiation damage, one of the major concerns for bipolar linear circuits in a low dose radiation environment.13 The rules were as follows.

  1. Minimize resistance values in the op amp gain circuits.

  2. Balance Thevenin resistances as looking out of any op amp input.

Rule 1 will minimize voltage offsets generated by increased bias currents flowing through gain resistors. For instance, if a 1 kΩ resistor is used in place a 10 kΩ resistor, then for the same current flowing through those resistors, 1/10th the offset voltage will be generated with the smaller resistor compared to the larger. Rule 2 will minimize input offset voltage errors due to increased bias currents. If the resistances are balanced at the inputs, then for any increase in bias current at the inputs, the offset voltages will shift by equal amounts, assuming the bias current increases equally for both inputs.

The selection of the LT1013/1014 op amp did provide one drawback in that its output voltage swing is not rail to rail (+supply to −supply) but instead as the data sheet lists can be as low as ±12.5 V when used with ±15 V supplies. This becomes an issue when looking at the various circuit topologies that may be constructed using a JFET as the DUT and a MOSFET as the load (Figure 3). Various curve tracing topologies are illustrated: (a), (b), and (c) are series and (d) is a shunt. Figure 3 shows three basic types of circuit topologies: (a) and (b) show a series load sitting above the DUT and (c) shows a series load sitting under the DUT. Each of these series circuits ((a), (b), and (c)) requires one of the gate voltages, either the Load in (a) and (b) or the DUT in (c) to be driven to the +V supply rail: to fully turn on the load in (a), to fully turn off the load in (b), and to fully turn on the DUT in (c). With the limited output swing of the LT1013/1014, either the DUT will not be tested over the full V DS range of the positive supply rail or the DUT will not be tested over the full range of V GS. While rail-to-rail operational amplifiers are available that can overcome this output voltage swing limit, an alternative topology will also work. This is shown in (d) of Figure 3. In this configuration, the load is in parallel with the DUT and acts as a shunt. The load MOSFET controls the voltage across the DUT by acting as a voltage controlled resistor. One drawback of this configuration is when the load is fully turned on, its resistance is in the mΩs, which can lead to excessive current. This in turn leads to the need of a current limiting resistor. The current limiting resistor will also limit the maximum V DS, but with small IDSS transistors such as the SiC JFETs, the maximum V DS is closer to the supply rail compared to any of the series configurations. The maximum span of V DS needs to be balanced with acceptable supply current.

FIG. 3.

Various curve tracing topologies. (a), (b), and (c) are series and (d) is a shunt.

FIG. 3.

Various curve tracing topologies. (a), (b), and (c) are series and (d) is a shunt.

Close modal

A simplified schematic diagram showing the curve tracing circuit from a systems view is shown in Figure 4. Microcontroller power is provided by a 3.3 V low drop out linear regulator. The microcontroller has two onboard 12-bit DACs and two onboard ADCs, a 12-bit and 8-bit, respectively. Additionally, each ADC has a built in multiplexer, allowing each ADC to make measurements at 8 input pins. The microcontroller contains an internal voltage reference of 2.4 V for its analog components, which defines the full-scale measurement voltage. The 8-bit ADC uses the +3.3 V supply voltage of the microcontroller as its reference, allowing a larger measurement range but less resolution. These references give 586 μV resolution step for the 12-bit components and 12.9 mV resolution step for the 8-bit ADC. The 12-bit ADC also has a built in temperature sensor attached to its multiplexer, so the board temperature can be sampled at the time of a curve.

FIG. 4.

Diagram of circuit to perform curve tracing of SiC JFET as the DUT.

FIG. 4.

Diagram of circuit to perform curve tracing of SiC JFET as the DUT.

Close modal

The circuit operates by sweeping two control voltages in the circuit. The first is the gate voltage of the DUT (V Gate) or SiC JFET and is controlled by the digital-to-analog converter zero (DAC0) through amplifier (A5). The second is the drain voltage of the DUT (V Drain) and is controlled by varying the NMOSFET load (Q1s) channel resistance. So, V Drain is controlled by the voltage at the gate of the Q1 from DAC1 through amplifier (A1).

The circuit is capable of making four voltage measurements with the respective ADC.

  1. DUT drain voltage (V Drain in Figure 4), 12-bit ADC.

  2. DUT source voltage (V source in Figure 4), 12-bit ADC.

  3. DUT gate voltage (V Gate in Figure 4), 8-bit ADC.

  4. The circuit supply voltage (V supply in Figure 4), 8-bit ADC.

Each of the measured voltages is amplified as shown in Figure 4. The amplifiers provide a corresponding gain, a high impedance load to the circuit being measured, and a low impedance driver into the ADC.

The sweep of V Gate is controlled by DAC0 through amplifier A5. A5 is an inverting amplifier to provide the negative gate voltage needed to turn off the DUT. The DACs onboard the microcontroller have a maximum output value of +2.4 V (limited by the onboard voltage reference). This necessitates the need for an amplifier to multiply the DAC0 output voltage by a factor of −6 times to generate a close to full-scale negative voltage at the gate of the DUT (−15 VDC) to fully turn off the DUT.

A software control loop is implemented to guarantee V Gate is set correctly. Using closed loop software control of V Gate, the controller is able to monitor the voltage at the gate and log the actual value. This is in contrast to open loop control where the microcontroller would write a value to the DAC from a look-up table and have no feedback from the current voltage reading at the gate. Monitoring V Gate during closed-loop control allows logging and telemetering of V Gate and can be used to show the circuit is operating correctly.

The software feedback loop algorithm used to set the control voltages is shown in the flow chart of Figure 5. The algorithm consists of a binary search within the DAC output range. The search is implemented by stepping through each of the 12 bits of the DACs range, starting by writing the most significant bit of the DAC (or half the full scale). Once the DAC value is written, the controlled value (V Drain, V Gate) is then sampled by the ADC 100 times and averaged to yield current value. If current value is greater than the requested value, nothing is done, but when the current value is less than the requested value, the value of the current DAC bit is added to a temporary variable, “Temp” in the flowchart. All successive DAC bits, as they are stepped through are added to this temporary variable, producing the final DAC value. After the final, or 12th iteration of this loop, the current value written to the DAC leaves the controlled value within one least significant bit (LSB) of the requested value.

FIG. 5.

Flow Chart of closed loop control of commanded circuit variables.

FIG. 5.

Flow Chart of closed loop control of commanded circuit variables.

Close modal

A V Drain sweep is performed similar to that of the V Gate, but is controlled by current steering through Q1. As the gate voltage of Q1 is changed, the channel resistance of Q1 (RDS,Q1) changes, thus the current flowing through Q1 is varied. This current flowing through Q1 generates the drain voltage (V Drain) by varying the resistance divider between RCurrentLimit and the parallel combination of RDS,DUT (the resistance of the DUT from drain to source) and RDS,Q1 according to the Eq. (1),

V DRAIN = V SUPPLY × R DS , DUT R DS , Q 1 R DS , DUT R DS , Q 1 + R CurrentLimit .
(1)

This equation is non-linear and RDS,DUT is dependent on the voltage between its gate to source (V GS) and temperature, which can fluctuate over 50 °C. RSense is omitted from Eq. (1) because it is much smaller than RDS,DUT, 10 Ω compared to over 10 kΩ, the voltage across RSense is also omitted for that reason. The complexity of these relationships makes necessary the need for closed loop control of V Drain, also using the algorithm described in Figure 5. V Drain is sampled, while DAC1 writes to the gate of Q1 through amplifier A1. Also to note, since the temperature of the environment was only controlled to a survival range, no attempt was made to compensate for temperature drift, instead the temperature was sampled at the time of the curve and recorded as part of the curve data set.

The drain to source current flowing the DUT (IDS) is derived from the sense resistor (RSense) and the source voltage (V Source) using Ohms law,

I DS = V Source Rsense .
(2)

A schematic for the complete curve tracing circuit is shown in Figures 6 and 7. Figure 6 demonstrates the corresponding power circuit containing the +5 VDC to +15 VDC boost converter and +15 VDC to −15 VDC voltage inverter, and Figure 7 shows the curve tracing load and measurement circuits. The boost converter needed to generate +15 VDC is made up of IC U2 and the surrounding parts in the left side of Figure 6: Q2A/Q2B, Q3, L1, D1, R5, R11, R16, R12, and R7. The +15 VDC supply is connected to the positive supplies for operational amplifiers U3A and U3B. The +15 VDC to −15 VDC voltage inversion circuit is shown in the right half of Figure 6, made up of Q4A, Q4B, Q5, Q2B, C10, C11, D3, D4, D5, D6, and the surrounding resistors. The circuit is a common charge transfer voltage inversion circuit, charging C10 to the +15 VDC supply rail through the diode D5. Then, connecting the positive lead of C10 to ground, generating −15 VDC on the negative lead of C10, which shows up on the negative lead of C11 by the current flowing through D6. The negative voltage across C11 provides the −15 VDC rail to the operational amplifiers U3A and U3B. The voltage inverting circuit is driven by two non-overlapping clocking signals provided by programmable counter arrays within the microcontroller, named VInv_CLK and not_Vinv_CLK, controlling the direction of current through Q4B and D5, then Q4A and D6. Zener diodes D3 and D4 provide voltage transient protection to the microcontroller outputs.

FIG. 6.

Schematic of Curve tracing circuit +5 VDC to +15 VDC boost converter and +15VDC to −15VDC voltage inverter.

FIG. 6.

Schematic of Curve tracing circuit +5 VDC to +15 VDC boost converter and +15VDC to −15VDC voltage inverter.

Close modal
FIG. 7.

Schematic of curve tracing circuit.

FIG. 7.

Schematic of curve tracing circuit.

Close modal

Because this curve tracing circuit is duplicated twice on the printed circuit board, the option to shut down this circuit is provided by the microcontroller JFET_EN signal to minimize power consumption. JFET_EN is connected to the enable pin of U2, disabling the +15 VDC and the gate of MOSFET Q1B, disabling the voltage inverter.

Figure 7 shows the curve tracing load and measurement circuit schematic. Op amp U3A and its associated resistor network amplifies the DAC0 signal with a gain factor of −6 times to drive the DUT gate. U3B samples the gate voltage and attenuates the DUT gate voltage by a factor of −6 times (or provides a gain of −1/6 times) to provide the JFET_gate signal to the 8-bit ADC. U3A and U3B provide the loop to control the DUT gate voltage. One of the features of the DUT gate circuitry is the path to ground R18 and R23. During power down, each of the DUT terminals should have a path to ground, allowing any charge buildup to have a discharge path so the DUT will not be damaged if unbiased. U3A and U3B are the only op amps powered by the ±15 VDC supplies, all others use +5 VDC. U1A samples the +15 VDC supply, attenuates by a factor of 1/6 times, and provides that voltage (V Supply) to the 8-bit ADC. U1B samples the DUT drain voltage, attenuates it by a factor of 1/6 times, and provides V Drain to the 12-bit ADC. U1C samples the DUT source voltage generated by the DUT drain current (IDS) flowing through a 10 Ω RSense and provides a gain of 69 times. This voltage labeled V Source in the schematic is sampled by the 12-bit ADC and is used to derive IDS. The final op amp U1D provides a gain of 1.5 times to the DAC1 output to drive the gate of the current shunt NMOSFET Q1.

Figure 8 shows an example curve trace of the room temperature packaged SiC JFET by the miniature circuit in comparison with the laboratory source measurement units, both taken at room temperature. In red are curve traces taken by laboratory source measurement units prior to integration into the flight circuit board. The blue traces show the curves taken by the miniaturized flight curve trace circuit during preflight tests. These curves are from the room temperature packaged SiC JFET shown in Figure 9. Included in the curve data set are the gate voltages shown in the legend of Figure 8 and the circuit board temperature with other housekeeping data. There is a disagreement between the miniature curve tracer and the commercial units of approximately 2% for the max IDS or V GS = 0 curve. All resistors used in the design have a one percent tolerance which will introduce some error into the measurements. This discrepancy may also be attributed to the added resistance from the conductive epoxy used to connect the transistor leads to the circuit board traces and the epoxy used to fasten the transistor package to the circuit board and encase the transistor leads.

FIG. 8.

Plot of the miniature curve trace circuit outputs (blue) and laboratory source measurement units performing curve traces (red) on the same room temperature packaged SiC JFET transistor. Drain-to-source current (IDS) vs. drain to source voltage (V DS) at varying gate to source voltages (V GS).

FIG. 8.

Plot of the miniature curve trace circuit outputs (blue) and laboratory source measurement units performing curve traces (red) on the same room temperature packaged SiC JFET transistor. Drain-to-source current (IDS) vs. drain to source voltage (V DS) at varying gate to source voltages (V GS).

Close modal
FIG. 9.

Photograph of flight circuit board incorporating two JFET transistor curve tracing circuits. The microcontroller is mounted on the bottom of the printed circuit board and is not shown in the photograph.

FIG. 9.

Photograph of flight circuit board incorporating two JFET transistor curve tracing circuits. The microcontroller is mounted on the bottom of the printed circuit board and is not shown in the photograph.

Close modal

No performance degradation of the JFETS was seen during the flight test.14 Experiment data were sampled hourly when power was applied and transmitted over a serial link to the MISSE7 Communications Interface Board, which handled all telemetry operations. The circuit successfully operated on orbit from November 2009 until its return to earth in May 2011. While the circuit operated successfully, one issue was identified during the flight period. The circuit’s −15 VDC supply would not operate fully at lower temperatures (temperatures below 16 °C). There was a correlation in the maximum V GS output voltage and temperature, where the maximum voltage would fall with temperature. This was due to the bipolar junction transistors used in the voltage inversion circuit, where the current gain decreases with temperature. This was verified post flight and on the flight back up hardware. The correction to this problem is to decrease the biasing resistors, so more current will flow. While this error did not allow the circuit to perform all the gate voltage sweeps, the circuit always allowed the sweep at ∼VGS = 0.

A photograph of the flight circuit board is shown in Figure 9. The flight circuit board contains two complete curve tracing circuits, one to support the high temperature packaged JFET and the other the room temperature packaged JFET, both controlled by a single microcontroller. The circuit board is much larger due to the support of two additional experiments not discussed. Each curve tracing circuit requires less than 32.3 cm2 board area, allowing for multiple independent circuits to be used on a single small printed circuit board. This small footprint enables in-situ testing of devices in a variety of environments.

A novel miniature microcontroller based curve tracing circuit was designed to enable a flight test of SiC JEFT transistors. The circuit was successfully flown and operated on the exterior of the International Space Station for over a year, periodically characterizing silicon carbide JFETs. There was an issue with the negative voltage supply circuitry that affected circuit performance in temperatures below 16 °C. The cause of this issue was identified as low bias current in the negative supply circuit and it is noteworthy to highlight that this neither damages the circuit nor the devices under test. The described circuit uses minimal space and mass and it is ideal for recurring space flight experiments. Even though this circuit was designed for characterizing JFETs, the circuit topology is applicable for MOSFETs, diodes, and Bipolar Junction Transistors (BJTs) with minor modifications.

This work was funded by the NASA Aeronautics Research Mission Directorate in the Fundamental Aeronautics Program under the Subsonic Fixed Wing Distributed Engine Control Project. The authors would like to thank Philip Neudeck of the NASA Glenn Research Center who provided the SiC JFETs, Liang-Yu Chen of the Ohio Aerospace Institute who packaged the SiC JFETs, and George Baaklini of the NASA Glenn Research Center for advice and support. The authors are also grateful to Phillip Jenkins of the Naval Research Laboratory for providing the opportunity to fly this circuit on MISSE7, as well as the telemetry data, and his review of this work.

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