Synaptic behavior simulation in transistors based on MoS2 has been reported. MoS2 was utilized as the active layer to prepare ambipolar thin-film transistors. The excitatory postsynaptic current phenomenon was simulated, observing a gradual voltage decay following the removal of applied pulses, ultimately resulting in a response current slightly higher than the initial current. Subsequently, ±5 V voltages were separately applied for ten consecutive pulse voltage tests, revealing short-term potentiation and short-term depression behaviors. After 92 consecutive positive pulses, the device current transitioned from an initial value of 0.14 to 28.3 mA. Similarly, following 88 consecutive negative pulses, the device current changed, indicating long-term potentiation and long-term depression behaviors. We also employed a pair of continuous triangular wave pulses to evaluate paired-pulse facilitation behavior, observing that the response current of the second stimulus pulse was ∼1.2× greater than that of the first stimulus pulse. The advantages and prospects of using MoS2 as a material for thin-film transistors were thoroughly displayed.

Neuron simulation, as a forefront research area in artificial intelligence and neuromorphic computing, aims to emulate and replicate the functionalities and behaviors of biological neurons.1–3 Many novel devices are being used as artificial synapses, such as resistive memories/memristors4–7 and transistors,8–10 to achieve multiple states in this field.11 Organic thin-film transistors have garnered extensive attention and research as a new class of electronic devices. In recent years, two-dimensional materials like graphene12,13 and transition metal dichalcogenides,14,15 have become research hotspots due to their atomic thickness16 and excellent electrical and optical properties,17–19 which offer potential for further miniaturization.20–22 Considering the advantages of two-dimensional materials, this work employs MoS2 with a larger bandgap (1.6–1.8 eV) to fabricate ambipolar MoS2 synaptic transistors.23 

Zhang et al. reported a heterojunction structure composed of MoS2/WSe2, comparing the vertical and horizontal contacts of MoS2/WSe2. Experimental data confirmed that the heterojunction under vertical contact exhibited a larger bandgap than that under horizontal contact, suggesting that vertical contact is more conducive to carrier transport.24 Zhang et al. also reported a TMDs heterojunction structure based on MoTe2/MoS2, which was applied to photoelectric detection.25 Interestingly, although MoS2 is a natural n-type semiconductor, Wang et al. achieved the fabrication of self-biased MoS2 ambipolar transistors through the presence of an electric double layer in an ionic liquid. The device exhibited a symmetric distribution of n-type and p-type characteristics on the transfer characteristics curve, with both positive and negative field-effect mobility being ideal.26 This device demonstrated electrical characteristics similar to the MoS2 thin-film transistors designed in this work.

Zhu and colleagues prepared a laterally coupled IZO-based synaptic transistor network on a nanogranular P-doped SiO2 electrolyte film. They observed a strong lateral electrostatic coupling effect resulting from proton migration in the P-doped SiO2 electrolyte film. Successful simulations of paired-pulse facilitation (PPF), dynamic filtering functions, and spatiotemporal signal processing were achieved. The oxide-based synaptic network proposed here holds significant importance for synaptic electronics and the construction of neuromorphic systems.27 

Go et al. demonstrated a crucial computing component—a resistive switching synaptic junction (RIMS) utilizing a novel thin film deposited metal electrode-based uniform partial-state transition facilitated framework. This synaptic junction is constructed using compact thin-film deposition techniques. Specifically, a deposited-only nanopillar-type device based on Ge2Sb2Te5 was developed to achieve rapid operation, intermediate bias range, multiple states, and various synaptic functions. The test results of the RIMS synapse demonstrate fast PPF/paired-pulse depression (PPD). The RIMS synapse also exhibits multiple states and rapid long-term potentiation/long-term depression (LTP/LTD). Additionally, the RIMS synapse shows fast spike-timing-dependent plasticity (STDP). The underlying cause of the increase in conductance states facilitated by uniform partial-state transition is elucidated through electro-thermal simulations. Given the scalability and stackability of these two-terminal resistive switching devices, our results could pave the way for high-density integration of artificial synapses with small features.28 

Loke and colleagues demonstrated the ability to control the thermal diffusion properties of thermal-guiding (TG) structures by simulating them using finite-element methods. They utilized nanoscale graphene-on-silica (GOS) stacked materials that can be integrated into CMOS, showcasing the control over thermal diffusion properties of TG structures. Additionally, they described other interesting aspects of the dependence of thermal-diffusion properties on the delay of excitation timings through an application to neuromorphic computing. The main components of neuromorphic circuits are devices capable of controlling the strength of connections in response to varying input signals, mimicking the functions of biological synapses.29 

Currently, there have been significant advancements in the research of MoS2 organic thin-film transistors for neuron simulation. Previous studies have shown that MoS2 thin-film transistors can mimic the excitatory and inhibitory signal conduction processes of biological neurons, enabling neuromorphic synapse functionality. Kim et al. fabricated bias-modulated synaptic transistors based on ultra-thin MoS2. By applying positive and negative pulses, the device could respectively simulate the excitatory and inhibitory behaviors of natural synapses.30 The baseline and percentage change of postsynaptic currents (PSCs) could be adjusted through a back-gate bias, allowing for the reconfiguration of weight distribution in machine learning. The opposite trends observed in PSC changes between single-pulse and multi-pulse tests were highly useful for simulating the recovery characteristics of natural synapses. Kim prepared a germanium gated MoS2 optoelectronic transistor,31 which could detect light from the visible to infrared regions using a band-bending modulation-based detection mechanism. Additionally, the Ge-gated MoS2 optoelectronic transistor was proposed as a multi-level visual synaptic device, operating within different current ranges under dark, visible, and infrared light conditions.

Despite achieving some promising results in the research of MoS2 thin-film transistors for neuron simulation, there are still many challenges. Issues related to the stability of transistor performance and precise control of plasticity require further in-depth research. However, these challenges also provide valuable opportunities for future studies, driving the development of the neuron simulation field. Therefore, this work aims to offer a MoS2 organic thin-film transistors in neuron simulation and provide prospects for their future applications in neuromorphic synapses and neuromorphic computing.

MoS2 is a layered transition metal dichalcogenide. It exhibits weak van der Waals coupling between layers. As the number of layers decreases, MoS2 transitions from an indirect bandgap to a direct bandgap, with the bandgap increasing from 1.2 to 1.8 eV. MoS2 nanosheets possess excellent photoelectric stability, a large specific surface area, and unique physical, chemical, and electronic properties. MoS2 stands as one of the most promising materials for energy conversion and storage.32 Based on the excellent above characteristics of molybdenum disulfide, we choose it as active layer material. The MoS2 suspension (1 mg/ml, obtained by lithium intercalation) was purchased from XF Nano Co., LTD. (Nanjing, China). Polyvinylpyrrolidone (PVP) powder is sourced from Sigma-Aldrich (Shanghai, China). Dilute the MoS2 solution to 0.5 mg/ml and mix with PVP in a 1:1 ratio. In this work, polymethyl methacrylate (PMMA) organic material is mainly used to make insulating layer. Take an appropriate amount of PMMA and put it into a beaker, then add acetone solution to prepare a solution with a concentration of 20 mg/ml. Place the beaker on a Magnetic stirrer and stir for 12 h to fully dissolve the solution. In this study, MoS2 material with extremely thin thickness and high mobility was used as the active layer of thin-film transistors. Add an appropriate amount of MoS2 solvent into the beaker, and then add an appropriate amount of PVP polymer to obtain the mixed solution. The device microstructure was observed with a scanning electron microscope (SEM, Crossbeam 350, ZEISS, Deutschland). Atomic force microscopy (AFM) was used to observe the surface topography of the device (Innova SPM, Bruker, Shanghai, China). The ultraviolet spectrum (UV–Vis) of MoS2 was measured by an ultraviolet–visible spectrophotometer (TU-1901, Puxi, Beijing, China).

In this study, the spin-coating method was employed to deposit the insulating layer of PMMA and the active layer of MoS2-PVP mixed solution separately onto the ITO substrate. We primarily utilized the evaporation method to deposit aluminum electrodes onto the MoS2 thin film. The electrodes were designed in a fork-like shape, and the width-to-length ratio of the source-drain electrodes was set at 480/1. The mask was positioned and fixed above the active layer on the ITO conductive glass, and the ITO glass with the mask was then secured onto the substrate holder within the deposition chamber. The aluminum wire was placed on the evaporation boat. The vacuum chamber was then sealed and evacuated to a pressure of 2 × 10−3 Pa. The aluminum wire was heated to initiate the evaporation process. During the evaporation, the deposition rate was controlled to start with a slow speed and gradually increase afterward. Once the film deposition was complete, the deposition boat was allowed to cool down to room temperature. The vacuum chamber was then vented to atmospheric pressure, and the ITO conductive glass coated with the evaporated aluminum electrodes was retrieved.

The preparation process is shown in Fig. 1(a). Most of the transistor devices are constructed in a bottom-gate configuration. This is because it is easy to deposit organic semiconductor materials on the insulating layer, and methods related to heat treatment can be safely used to prepare the insulating layer without causing any damage to the organic semiconductor layer. On the other hand, if the lower organic semiconductor layer is contaminated during the deposition of the metal gate, the performance of the top-gate structure transistor would be significantly degraded. Therefore, we chose the bottom-gate/top structure to fabricate the devices, and the device structure is illustrated in Fig. 1(b). The surface roughness of the device was observed using an AFM to be ∼2.2 µm [Fig. 1(c)]. The relatively flat and uniform film provides suitable conditions for charge transfer and contact between the material and the electrodes. Figure 1(d) displays the cross-sectional SEM image of the Al/MoS2-PVP/PMMA/ITO device. The SEM image reveals a four-layer structure, with the active layer thickness measuring 160 nm and the insulating layer thickness measuring 120 nm. Figure 1(e) shows the ultraviolet-visible absorption spectrum of MoS2, and the wavelength corresponding to the bandgap width is 656 nm. By using the equation Eg = hc/λ, the bandgap width of MoS2 is calculated to be 1.87 eV.

FIG. 1.

(a) Preparation process of the Al/MoS2-PVP/PMMA/ITO device. (b) Schematic diagram of the device structure. (c) AFM image of the MoS2-PVP active layer. (d) SEM characterization image of the device. (e) Ultraviolet absorption spectrum of MoS2.

FIG. 1.

(a) Preparation process of the Al/MoS2-PVP/PMMA/ITO device. (b) Schematic diagram of the device structure. (c) AFM image of the MoS2-PVP active layer. (d) SEM characterization image of the device. (e) Ultraviolet absorption spectrum of MoS2.

Close modal

The Keithley 4200 is used as a testing platform to measure the performance of the transistor. The platform includes a semiconductor parameter analyzer, connecting cables, and probes. During the testing process, the probes are respectively connected to the gate, drain, and source of the transistor, with the source being grounded.

Figure 2(a) shows the transfer characteristics curve of MoS2 thin-film transistor at drain voltage (VDS) of 2 V. This curve shows that the organic transistor is an ambipolar device with both n-type and p-type characteristics. The threshold voltage for the n-type region is 8.9 V with a subthreshold swing of 6.75 mV/dec, while for the p-type region, the threshold voltage is 1.18 V with a subthreshold swing of 6.14 mV/dec. The carrier mobility for the n-type region is 11.38 cm2/V s, and for the p-type region, it is 12.51 cm2/V s. For thin-film transistors, the threshold voltage and subthreshold swing are important parameters. It can be observed that the fabricated transistor has a relatively small threshold voltage, indicating that the transistor can start conducting at lower voltages. This enables the transistor to be driven and controlled at lower voltages, reducing power consumption and energy consumption. Additionally, a smaller threshold voltage can provide higher amplification gain. In amplification circuits, the small-signal gain of a transistor is related to its threshold voltage. A smaller threshold voltage means the transistor can more easily achieve amplification, providing higher gain. A smaller subthreshold swing also means that the transistor consumes less energy in the subthreshold region. This is crucial for low-power applications such as mobile devices, sensor networks, and energy-efficient circuits. A smaller subthreshold swing can reduce static and dynamic power consumption, improving overall energy efficiency. It can also enhance the transistor’s resistance to noise, increasing the circuit's reliability and stability.

FIG. 2.

(a) Transfer characteristics curve of MoS2 thin-film transistor (VDS = 2 V). (b) Transfer characteristics curves of MoS2 thin-film transistor at VDS = 10, 5, and 2 V. (c) Output characteristics of the p-type region of MoS2 thin-film transistor. (d) Output characteristics of the n-type region of MoS2 thin-film transistor.

FIG. 2.

(a) Transfer characteristics curve of MoS2 thin-film transistor (VDS = 2 V). (b) Transfer characteristics curves of MoS2 thin-film transistor at VDS = 10, 5, and 2 V. (c) Output characteristics of the p-type region of MoS2 thin-film transistor. (d) Output characteristics of the n-type region of MoS2 thin-film transistor.

Close modal

For p-type transistors, the channel is formed by holes, and an increase in gate voltage will create a reverse electric field between the channel and the gate. This reverse electric field suppresses the movement of holes, leading to a decrease in output current. The substrate in p-type transistors is made of an n-type semiconductor material, and in p-type transistors, the substrate plays a crucial role. With an increase in gate voltage, the charge and potential distribution in the substrate change, affecting the movement of holes in the channel, resulting in a decrease in output current. In the transfer characteristics curve of the n-type transistor, the current increases with an increase in gate voltage. The channel of the n-type transistor is formed by electrons, and an increase in gate voltage generates a forward electric field between the channel and the gate. This forward electric field enhances the movement of electrons, leading to an increase in output current. N-type transistors typically have higher electron mobility than p-type transistors. A higher electron mobility means that electrons can move more easily in the channel when an electric field is applied. With an increase in gate voltage, the electric field intensifies, enhancing electron flow and increasing output current. Moreover, n-type transistors have a p-type substrate, and the substrate’s properties play an important role in the behavior of the transistor. As the gate voltage increases, the charge and potential distribution in the substrate are affected, allowing better control of electron flow in the channel, resulting in an increase in output current. Additionally, from the graph, we can observe that when the gate voltage is very large, the transfer characteristics curve of the transistor tends to level off. This is because when the gate voltage is sufficiently large, the transistor can enter the saturation region. In the saturation region, the output current of the transistor reaches its maximum limit, and further increasing the gate voltage will not significantly increase the output current. With an increase in gate voltage, the electric field between the gate and the channel gradually saturates. In the electric field saturation state, the speed of electron or hole movement no longer increases linearly with the electric field. This slows down the increase in output current, resulting in the leveling off the transfer characteristics curve. From Fig. 2(a), we can also observe that in transistors, when the same absolute value of gate voltage is applied, the drain current under negative gate voltage is typically greater than that under positive gate voltage. This is because a negative gate voltage causes a Fermi level adjustment between the gate and the substrate, resulting in more electrons crossing the gate-substrate interface and increasing the drain current.33 Moreover, under negative gate voltage, the Fermi level adjustment may increase the energy of thermally emitted electrons, allowing them to overcome the barrier and leading to an increase in drain current.33 

Figure 2(b) shows the transfer characteristics curves of the MoS2 thin-film transistor at VDS of 10, 5, and 2 V, respectively. From these curves, it can be observed that as the drain-source voltage increases, the drain current decreases for the p-type transistor and increases for the n-type transistor. For the p-type transistor, as the drain voltage increases, the drain current decreases. This is because a transistor is a device that controls the drain-source current by manipulating the gate voltage. In the p-type transistor, when the gate voltage is relatively low, the gate-drain junction is reverse-biased, leading to the existence of a drain current. However, as the drain voltage increases, the reverse bias of the gate-drain junction strengthens. This widens the depletion region of the gate-drain junction, limiting the flow of drain current. Therefore, an increase in drain voltage leads to a decrease in drain current. On the other hand, in the n-type transistor, when the gate voltage is relatively low, the gate-drain junction is forward-biased, resulting in the presence of a drain current. As the drain voltage increases, the drain current also increases. This is because, with an increase in drain voltage, the forward bias of the gate-drain junction intensifies. This widens the channel region of the gate-drain junction, allowing more charge carriers to flow from the drain to the source. From the graph, it is evident that the smaller the drain-source voltage, the higher the on/off ratio of the thin-film transistor. When the drain-source voltage is small, the channel is subjected to a lower electric field, resulting in a smaller drain current in the on-state. Conversely, in the off-state, the drain current is very close to zero. This leads to an increased on/off ratio since the off-state current is close to zero while the on-state current is relatively large. When the drain-source voltage is small, the conduction state of the organic thin-film transistor occurs under a lower electric field. Due to the lower carrier mobility of organic materials, the lower electric field results in a smaller carrier drift velocity.

Figure 2(c) represents the output characteristics of the p-type region of the MoS2 thin-film transistor. From the graph, it can be observed that when the VDS is relatively small, the p-type transistor operates in the non-saturation region. In the non-saturation region, the drain current is mainly influenced by two factors: hole concentration and electric field strength. A smaller VDS results in a lower electric field strength, which allows holes to move with less restriction, leading to a smaller drain current. As VDS increases, the p-type transistor may enter the saturation region. In the saturation region, the drain current remains relatively constant. This is because when VDS becomes sufficiently large, the electric field strength in the drain-source junction reaches saturation, limiting the migration speed of electrons and holes. As a result, the increase in VDS has a minor impact on the drain current in the saturation region.

Figure 2(d) shows the output characteristics of the n-type region of the MoS2 thin-film transistor. In an n-type transistor, an increase in the gate voltage (VGS) generates a positive electric field. This positive electric field attracts more free electrons into the channel region. As the gate voltage increases, the positive electric field becomes stronger, providing a greater driving force for electron movement in the channel, leading to an increase in current. Therefore, with the increase in gate voltage, the current in the n-type transistor also increases. This is because the increase in gate voltage alters the transistor’s potential distribution, promoting electron motion in the channel.

The thickness of the insulating layer is a design parameter for the transistor, which determines the electrical performance and characteristics of the device. A larger insulating layer thickness can provide better isolation, reducing leakage current and interconnect capacitance in the transistor. However, a larger insulating layer thickness may also lead to increased crosstalk and response time. From Fig. 3(a), it can be observed that the maximum value of Ig is around 5 × 10−8 A, indicating that the PMMA insulating layer exhibits strong barrier properties, and the insulating layer thickness is moderately suitable.

FIG. 3.

The Al/MoS2-PVP/PMMA/ITO thin-film transistor (a) IgVg characteristics; (b) retention characteristics; (c) capacitance characteristics; (d) conductance characteristics.

FIG. 3.

The Al/MoS2-PVP/PMMA/ITO thin-film transistor (a) IgVg characteristics; (b) retention characteristics; (c) capacitance characteristics; (d) conductance characteristics.

Close modal

The hold characteristics of a transistor refer to the variation in drain current when the gate voltage is held constant while the transistor is in the ON state. The hold characteristics provide important information about the stability and storage properties of the transistor. As shown in Fig. 3(b), the designed transistor in this study achieves a large ON/OFF current ratio of 1.96 × 105, and the OFF state can be stably maintained within 36000 s, indicating good storage properties and stability. The ON/OFF current ratio of a transistor represents the current or conductance ratio between the ON and OFF states of the transistor. The magnitude of the ON/OFF current ratio provides information about the switching speed and energy efficiency of the transistor. A larger ON/OFF current ratio means that the transistor can switch quickly from the OFF state to the ON state or vice versa. Fast switching speed is crucial for high-frequency applications and rapid switching in digital circuits. Moreover, a smaller ON/OFF current ratio may result in increased noise and distortion during the switching process, affecting the quality and accuracy of the signals.

Figure 3(c) demonstrates that in the CV curve at a frequency of 106 Hz, the depletion region sharply decreases from the accumulation region to the inversion region. This indicates that the interface between MoS2/PVP and the PMMA layer on the ITO surface has a low concentration of traps and mobile ions, which accelerates the charging phenomenon. Devices fabricated with other organic semiconductor materials (such as pentacene) cannot achieve such sharp depletion curves in CV.34,35 This difference may arise from the fast movement of holes or electrons in MoS2.

Figure 3(d) shows the conductivity characteristics of the MoS2 transistor, and the presence of a peak is caused by the saturation of drain current. The transistor may experience current saturation during operation. In this case, when the transistor is in saturation, further increasing the input voltage or the amplitude of the input signal will not result in a significant increase in the output current. Therefore, in the conductivity plot, when the transistor approaches or reaches saturation, the conductivity reaches a peak and remains relatively constant thereafter, forming a peak. In the saturation region of the transistor, when VDS increases, the conductivity often increases as well. This is because a larger VDS leads to an enhancement of the drain-source electric field, which in turn increases the drain current. As the drain current’s contribution to the conductivity increases, the conductivity also increases.

The biological synapse is a crucial site for transmitting information from presynaptic to postsynaptic neurons. Under external stimulation, an action potential of a neuron can be transmitted to the next neuron through the synapse, EPSC changes in synaptic weights. In this study, the presynaptic neuron corresponds to the drain electrode in the Al/MoS2-PVP/PMMA/ITO transistor, while the postsynaptic neuron corresponds to the source electrode. To simulate the EPSC phenomenon, a single pulse voltage was applied to the device at the source and drain electrodes. We tried applying various voltages (e.g., 2, 3, 4, 5 V) to observe the response of the device. We found that the current response was most pronounced when applying a voltage of 5 V with a pulse width of 200 ms. The experimental results are shown in Fig. 4(b). The pulse arrives at 40 ms, and the device’s response current increases upon pulse arrival and gradually decays after the pulse is removed, with the final response current slightly larger than the initial current. Throughout the process, the increase in response current indicates the generation of EPSC. When testing the STP characteristics, it is necessary to use a lower voltage to control the behavior of the device. We tried voltages of 0.5, 1, 1.5, 2, 2.5, and 3 V. It was observed that significant characteristics could be observed when the voltage was increased to 3 V. Figure 4(c) illustrates a series of 10 consecutive tests were conducted using pulse voltage (amplitude = 3 V, pulse width = 5 ms).

FIG. 4.

The synaptic behaviors based on the Al/MoS2-PVP/PMMA/ITO device. (a) Illustration of a biological synapse. (b) Simulation of EPSC phenomenon. (c) STP plasticity in 10 continuously positive pulses (Amplitude = 3 V, width = 5 ms). (d) LTP plasticity after 92 consecutive positive pulses (Amplitude = 3 V, Width = 5 ms). (e) STD plasticity in 10 continuously negative pulses (Amplitude = −3 V, Width = 5 ms). (f) LTD plasticity after 88 consecutive negative pulses (Amplitude = −3 V, Width = 5 ms). (g) Current response after continuous stimulation with two triangular wave pulses: PPF simulation. (h) PPF index as a function of time interval (Δt). (i) STDP in Hebbian learning rules.

FIG. 4.

The synaptic behaviors based on the Al/MoS2-PVP/PMMA/ITO device. (a) Illustration of a biological synapse. (b) Simulation of EPSC phenomenon. (c) STP plasticity in 10 continuously positive pulses (Amplitude = 3 V, width = 5 ms). (d) LTP plasticity after 92 consecutive positive pulses (Amplitude = 3 V, Width = 5 ms). (e) STD plasticity in 10 continuously negative pulses (Amplitude = −3 V, Width = 5 ms). (f) LTD plasticity after 88 consecutive negative pulses (Amplitude = −3 V, Width = 5 ms). (g) Current response after continuous stimulation with two triangular wave pulses: PPF simulation. (h) PPF index as a function of time interval (Δt). (i) STDP in Hebbian learning rules.

Close modal

Evidently, the resulting device’s output current underwent a gradual augmentation, signifying a transient boost in plasticity akin to the concept of short-term memory in human cognitive function. In such cases, the brain promptly reacts to momentary stimuli but does not retain enduring recollections. Notably, the device displayed varying performance characteristics when subjected to distinct stimulation intensities of short and protracted pulse voltages. After the application of 10 voltage pulses, the device’s failure to manifest an ON state was conspicuous, indicating that the emulated human brain failed to achieve long-term memory formation within that span. A repetition of the pulse voltage stimulation regimen ensued. It was only after a sequence of 92 consecutive stimulation pulses that the device underwent activation. Consequently, its initial current value of 0.14 mA underwent a remarkable surge to 28.3 mA [as observed in Fig. 4(d)]. This pivotal shift can be interpreted as the brain’s transition from a transient memory state to a more enduring one.

The progressive escalation in the number of input pulse voltages directly correlates with the escalating trend in the output current, concurrently resulting in the establishment of a functional conductive pathway. We assert influence over the conductive channel’s formation by manipulating the number of applied pulse voltages. Similarly, under negative voltage, the device also transitions from short-term memory (STM) to long-term memory (LTM), as shown in Figs. 4(e) and 4(f). The device exhibits a small range of current variation in response to a few pulse stimulations, consistent with STP behavior. However, with an increase in the number of pulses, the current undergoes a sharp increase, indicative of LTP behavior.

Additionally, in the experiment, a pair of continuous triangular wave pulses were applied to the device’s two ends, and the current values corresponding to each stimulation were recorded to simulate the PPF function of the biological synapse. As shown in Fig. 4(g), both pulse amplitudes of the two stimulations were 3 V, and the pulse width was 20 ms. The response current corresponding to each stimulation is shown as the blue line in the figure. It can be observed that the response current of the second stimulation pulse is greater than that of the first stimulation pulse, with the current value enhanced by ∼1.2×, indicating a significant enhancement effect. To investigate the relationship between this current enhancement and the time interval between the two pulses, as shown in Fig. 4(h), five groups of current responses with intervals ranging from 10 to 50 ms were tested, and the paired-pulse facilitation index was used to evaluate the strength of current enhancement. The calculation method is as follows:
PPFINDEX=(I2I1)/I1×100%.
(1)
According to Eq. (1), the intensities of the five sets of current enhancement are obtained, and then a nonlinear fitting of the discrete test data is performed. The fitted function is as follows:36 
PPF=C1exp(Δt/τ1)+A1.
(2)

The fitting results are shown as curves in the figure, and the test data are well distributed around the curves, where τ1 = 13.4 ms is the attenuation term of PPF. From the graph, it can be observed that as the time interval increases, the facilitation index decreases rapidly. Therefore, the device can effectively simulate the PPF function of biological synapses.

The successful simulation of PPF behavior indicates that our device possesses excellent short-term synaptic plasticity, characterized by significant plastic changes occurring within short time intervals, with an exponential decrease as the interval time increases. For biological synapses, spiking-timing-dependent plasticity (STDP) is a crucial mechanism for memory and learning, making it particularly important to simulate STDP behavior in our synaptic device. In STDP, the synaptic strength between two neurons can adaptively adjust based on the timing difference (Δt) between pre- and postsynaptic spikes. The weight calculation of the synaptic connections follows formula (3):
Δw=G2G1G1×100%,
(3)
where G2 and G1 represent the conductance values of the second pulse and first pulse, respectively. However, unlike PPF/PPD, we define the cases of Δt > 0 and Δt < 0 when the presynaptic pulse arrives before and after the postsynaptic pulse, respectively. This leads to synaptic facilitation or depression. For Δt > 0, the device's conductance state increases, but as Δt increases, Δw decreases, resulting in an exponential curve. When Δt < 0, the conductance state decreases, indicating that the synapse is in a depressed state [Fig. 4(i)]. In STDP research, LTP is typically modeled as a single exponential function, while LTD is often modeled as a double exponential function.37 This modeling choice is based on experimental observations of biological synaptic plasticity phenomena. LTP refers to the gradual increase in synaptic transmission efficiency when a synapse receives a series of repeated stimuli. In mathematical modeling, this efficiency increase can often be well described by a single exponential function. On the other hand, LTD involves a gradual decrease in synaptic transmission efficiency after receiving a different specific pattern of stimuli. This complex behavior is closer to being described by a double exponential function, as it involves more complex time dependence and the interaction of multiple biological processes.37 So, the STDP experimental data is fitted using an exponential function:
STDPPotention=C2expΔtτ2+A2,
(4)
STDPDepression=C3exptτ3+C4exptτ4+A3.
(5)
C2, C3, and C4 are scaling factors, and τ is the characteristic time constant of STDP. When Δt > 0, C2 = 1.25, τ2 = 12.75 ms. Similarly, when Δt < 0, C3 = −2.46, τ3 = −4.41 ms, and C4 = −2.46, τ4 = −5.39 ms. The results demonstrate that by adjusting the Δt and order between pulses, our device successfully emulates the STDP characteristics observed in biological synapses.

Spike voltage-dependent plasticity (SVDP) is a form of synaptic plasticity where changes in synaptic strength are influenced by the voltage of the postsynaptic neuron in response to a spike.38 In SVDP, the timing of presynaptic spikes and the voltage level of postsynaptic spikes play a crucial role in adjusting synaptic weights. SVDP reflects how the state of the postsynaptic neuron influences changes in synaptic efficacy. This plasticity is believed to contribute to fine-tuning neural circuits and encoding information in neural networks. To validate the SVDP behavior, we also investigated the variation of device conductivity under different pulse intensities, as shown in Figs. 5(a)5(e). We used 10 consecutive pulses of the same width, only changing the intensity of the pulses. The results indicate that after applying negative voltage pulses, the device conductivity decreases. Lower voltage pulses only slightly alter the low-conductance state, while higher voltages have a more significant impact on the conductivity state [Fig. 5(f)].

FIG. 5.

Ten consecutive pulses with positive voltage: (a) amplitude of 3 V; (b) amplitude of 5 V; (c) amplitude of 8 V; (d) amplitude of 9 V; (e) amplitude of 10 V; (f) current responses at five different voltage intensities.

FIG. 5.

Ten consecutive pulses with positive voltage: (a) amplitude of 3 V; (b) amplitude of 5 V; (c) amplitude of 8 V; (d) amplitude of 9 V; (e) amplitude of 10 V; (f) current responses at five different voltage intensities.

Close modal
The importance of calculating power consumption in the design and application of electronic devices cannot be overstated, as it directly impacts the device's performance, efficiency, stability, and reliability. By calculating power consumption, design optimization can be achieved to enhance device performance and efficiency, therefore, based on Eq. (6):
W=I×V×t.
(6)

The power consumption of the fabricated Al/MoS2-PVP/PMMA/ITO device is 0.03 J.

Following the discussion above, we further compared the basic electrical properties of transistors prepared using other materials, and the results are summarized in Table I. Due to the various factors influencing the performance of transistors, simultaneously optimizing all performance parameters to the highest level is challenging. Through comparisons, it can be observed that thin-film transistors prepared with rGO embedded with Au NPs, InGaSnO, polymer blend of pentafluorophenyl methacrylate and branched polyethyleneimine, and CuI active layer materials are unipolar, while the MoS2 in our work exhibits a distinct n-type and p-type bipolar behavior. Compared with rGO embedded with Au NPs, our MoS2 transistor has a larger on/off ratio and a smaller threshold voltage, but a lower carrier mobility. Compared with polymer blend of pentafluorophenyl methacrylate and branched polyethyleneimine, our MoS2 transistor has a smaller threshold voltage and a larger carrier mobility. Compared with CuI, our MoS2 transistor has a higher carrier mobility and a smaller threshold voltage.

TABLE I.

Different active layer transistor characteristics comparison.

Active layer materialTransistor typeSwitching ratioThreshold voltage (V)Charge carrier mobility (cm2/V·s)Reference
MoS2 n/p 1.96 × 105 8.9/1.18 11.38/12.51 This work 
InGaSnO >1 × 109 0.47 116.5 39  
rGO embedded with Au NPs <1 5.74 22.887 34  
Polymer blend of pentafluorophenyl methacrylate and branched polyethyleneimine 107 13 ± 2 7.5 40  
CuI 2.7 × 102 0.18 41  
Active layer materialTransistor typeSwitching ratioThreshold voltage (V)Charge carrier mobility (cm2/V·s)Reference
MoS2 n/p 1.96 × 105 8.9/1.18 11.38/12.51 This work 
InGaSnO >1 × 109 0.47 116.5 39  
rGO embedded with Au NPs <1 5.74 22.887 34  
Polymer blend of pentafluorophenyl methacrylate and branched polyethyleneimine 107 13 ± 2 7.5 40  
CuI 2.7 × 102 0.18 41  

From the comparisons, it can be understood that achieving the highest level for all parameters during the transistor fabrication process is difficult. The MoS2 transistors we prepared have relatively stable performance across various parameter indices, ensuring that MoS2 does not exhibit significant defects in subsequent use. The favorable characteristics of MoS2 transistors are attributed to the lattice structure formed by molybdenum ions and sulfur ions in MoS2, enabling electrons to move with higher mobility within this lattice structure, resulting in a higher carrier mobility. MoS2 is composed of multiple layers of two-dimensional crystals stacked together, and the weak van der Waals forces between the layers allow relatively easy sliding of one layer over another. This interlayer coupling characteristic enables MoS2 to maintain relative stability when forming stacked structures. The primary reasons for the excellent properties of MoS2 transistors lie in their ionic structure, electronic structure, and interlayer coupling characteristics. These features establish MoS2 as a crucial material for researching and developing new electronic devices.

In summary, the simulation of synaptic behavior in MoS2-based transistors has been reported. This transistor exhibited outstanding ambipolar characteristics and stability. Additionally, we simulated fundamental functions of biological synapses. The EPSC phenomenon was simulated, demonstrating a gradual decay in current following the removal of applied pulses, ultimately resulting in a response current slightly exceeding the initial level. Subsequently, ±5 V voltages were separately applied for 10 consecutive pulse voltage tests, revealing short-term potentiation and depression behaviors. After 92 consecutive positive pulses, the device current transitioned from an initial value of 0.14 mA to a remarkable 28.3 mA. Similarly, following 88 consecutive negative pulses, the device current underwent significant changes, indicating long-term potentiation and depression behaviors. In addition, the behavior of PPF and SVDP is simulated. Our study demonstrated that the transistor based on MoS2 possessed exceptional electrical properties and showcased potential in simulating biological synaptic functions. This research holds promise for future applications of two-dimensional materials in neural morphology computing.

Funding was received from Natural Science Foundation of Heilongjiang Province, China (Grant No. LH2023F045).

The authors have no conflicts to disclose.

Yufei Wang: Conceptualization (equal); Formal analysis (equal); Resources (equal). Qi Yuan: Investigation (equal); Methodology (equal); Resources (equal); Supervision (equal); Writing – original draft (equal). Xinru Meng: Resources (equal); Validation (equal); Visualization (equal). Yanmei Sun: Data curation (lead); Investigation (lead); Supervision (lead); Writing – review & editing (equal).

The data that support the findings of this study are available from the corresponding author upon reasonable request.

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