It is known that Belousov-Zhabotinsky (BZ) reaction can be applied to chemical computation, e.g., image processing, computational geometry, logical computation, and so on. In the field of logical computation, some basic logic gates and basic combinational logic circuits, such as adder, counter, memory cell, have already been implemented in simulations or in chemical experiments. In this paper, we focus on another important combinational logic circuit, binary decoder. Integrating AND gate and NOT gate, we first design and implement a one-bit binary decoder through numerical simulation. Then we show that one-bit decoder can be extended to design two-bit, three-bit, or even higher bit binary decoders by a cascade method. The simulation results demonstrate the effectiveness of these devices. The chemical realization of decoders can guide the construction of more sophisticated functions based on BZ reaction; meanwhile, the cascade method can facilitate the design of other combinational logic circuits.

Belousov-Zhabotinsky (BZ) reaction is an important chemical oscillating reaction discovered by Boris Belousov and further developed by Zhabotinsky.1 It has been proposed that some types of photosensitive BZ reactions can be applied to chemical computation. Unlike computation in electronic computers, chemical computation relies on geometrically-constrained excitable chemical medium, and uses the change of concentrations of the BZ reagents to transmit information and realize computation.2,3

The first successful application of chemical computation was image processing in 1989,4 since then, many different prototypes have been designed and tested on a variety of tasks, including optimal path search in a labyrinth,5–7 image processing,8 robot navigation,9 direction detection,10 computational geometry,11 arithmetic and logical computations,12,13 and so on. In the applications, the chemical implementations of logic circuits have attracted the attention of many researchers in the past 20 years. These logical devices are based on the space-time interaction of travelling excitation waves. By a clever geometrical arrangement of the channels for the excitation wave propagation, researchers have constructed several logical devices, such as Boolean logic gates,14–17 adders,18–20 counters,21 memory cells.15 Many of them have already been realized in experiments.

In this paper, we perform the entire simulations towards the realization of a combinational logic circuit, multi-bit binary decoder, which converts binary information from n input lines to a maximum of 2n unique output lines. Binary decoder is widely used in digital electronics. It is necessary in applications such as data multiplexing, 7 segment display, as well as memory address decoding.22 

In this paper, one-bit binary decoder is designed and implemented with some existing chemical signal processor components first. Considering the components have already been verified in experiments, this device is highly compatible for experimental implementation. The structures of multi-bit binary decoders become complex, as the numbers of bits increase. We adopt a cascade method when designing multi-bit decoders. This method links n-bit decoder (n ⩾ 2) with (n − 1)-bit decoder. We can construct n-bit decoder based on (n − 1)-bit decoder. Each n-bit decoder includes a (n − 1)-bit decoder, which leads to a simpler structure. The simulation results demonstrate that our designs achieve the decoding functions.

The rest of the paper is organized as follows. Two-variable Rovinsky-Zhabotinsky (RZ) model of BZ reaction is introduced in Sec. II. Section III outlines some basic chemical signal processors and a logic gate combination. The gate is employed to construct binary decoders. Section IV shows the structures and simulation results of binary decoders. The paper is concluded in Sec. V.

In this paper, we employ the RZ model of the BZ reaction to calculate the propagation of the pulses.20,21,23,24 The RZ model can be derived from the well-known Field-Koros-Noyes (FKN) reaction mechanism.1 The model has two variables, x and z, corresponding to dimensionless concentrations of activator HBrO2 and of catalyst

${\rm Fe(phen)}_3^{3+}$
Fe ( phen )33+⁠. In the active regions, which contain the catalyst, the time evolution of the concentrations of x and z is described by Eqs. (1):
\begin{equation}\frac{{\partial x}}{{\partial \tau }} = \frac{1}{\varepsilon }\left[ {x(1 - x) - \bigg(2q\alpha \frac{z}{{1 - z}} + \beta \bigg)\frac{{x - \mu }}{{x + \mu }}} \right] + {\nabla ^2}x,\end{equation}
xτ=1ɛx(1x)2qαz1z+βxμx+μ+2x,
(1a)
\begin{eqnarray}\frac{{\partial z}}{{\partial \tau }} = x - \alpha \frac{z}{{1 - z}}.\end{eqnarray}
zτ=xαz1z.
(1b)

In the passive regions, where catalyst is absent, the concentrations of x and z evolve according to Eqs. (2):

\begin{equation}\frac{{\partial x}}{{\partial \tau }} = - \frac{1}{\varepsilon }\left[ {{x^2} + \beta \frac{{x - \mu }}{{x + \mu }}} \right] + {\nabla ^2}x,\end{equation}
xτ=1ɛx2+βxμx+μ+2x,
(2a)
\begin{eqnarray}z = 0.\end{eqnarray}
z=0.
(2b)

In numerical calculations, Eqs. (1) and (2) are solved numerically using Euler method with a five-node Laplace operator for the diffusion term. The time step Δτ is 0.0001, and the distance between each grid point Δρ is 0.3301.20 The other parameters are the same values as considered in Refs. 20 and 21, and 23: ε = 0.1176, q = 0.5, α = 0.068, β = 0.0034, and μ = 0.00051. For these values of parameters, the stationary concentrations of x and z in the active regions (stationary solution of Eqs. (1)) are: x = 7.27 × 10−4, z = 1.06 × 10−2; and the stationary concentrations in the passive regions (stationary solution of Eqs. (2)) are: x = 5.12 × 10−4, z = 0.

We initiate the pulses in the active regions by increasing the value of x to 0.1 at the end of signal channels, and then the excitation waves will propagate inside the channels. Based on the geometrical configuration of the channels, many kinds of computational devices can be implemented by the model. In simulation results, the black color shows the distribution of the active regions, and the white parts are passive. A high concentration of activator x is marked as a gray wave in the active regions.

A T-shaped coincidence detector is shown in Fig. 1. The device has two parts: a horizontal bar above as the signal channel, and a T-shaped structure below to detect coincidence.21 The distance between the above bar and the horizontal bar on the T (detector bar) is very important. If two pulses propagate simultaneously from two sides of the above bar, they will meet in the middle and annihilate. With proper distance between the two bars, a pulse appears in the detector bar, and an output pulse is sent through the vertical part of the T. However, when a single pulse propagates inside the bar, it dies at the other end and does not excite the detector bar. The coincidence detector can detect the meeting areas of the pulses. This device will be employed to construct logic gates and binary decoders in this paper, as shown in Secs. III C and IV.

FIG. 1.

A classical T-shaped coincidence detector.21 Grid size is 100 × 90, the channels are 20 grid points wide and the gap is 10 grid points wide.

FIG. 1.

A classical T-shaped coincidence detector.21 Grid size is 100 × 90, the channels are 20 grid points wide and the gap is 10 grid points wide.

Close modal

Penetration means a pulse propagating in the active region can penetrate into a passive part and disappears after some distance.3 The pulse can excite the active region behind the passive stripe, if the stripe is narrow enough.23 The pulse propagates more quickly in active region than passive region, so penetration can be used for pulse delay. As shown in Fig. 2, under the simulation condition, it leads to 13-grid point delay for a penetration unit with a 20-grid point wide channel and an 8-grid point wide passive stripe. This property will be applied to implement three-bit binary decoder in Sec. IV D.

FIG. 2.

Pulse delay by penetration unit. Grid size is 120 × 80, the channels are 20 grid points wide and the gap is 8 grid points wide. (a) Pulses propagation before penetration. (b) Pulses propagation after penetration.

FIG. 2.

Pulse delay by penetration unit. Grid size is 120 × 80, the channels are 20 grid points wide and the gap is 8 grid points wide. (a) Pulses propagation before penetration. (b) Pulses propagation after penetration.

Close modal

In this section, we design a new device that achieves the functions of AND, OR, and NOT logic gates simultaneously. This device will be simplified to a one-bit binary decoder, as shown in Sec. IV B. Figure 3 illustrates the structure, which is formed by a rectangular ring channel with two inputs A and B, and three outputs, A OR B, A AND B, NOT B, respectively, from top to bottom. In this figure and those following, Boolean 1 and 0 are represented by the presence and absence of the excitation pulse, respectively, for information coding.

FIG. 3.

Structure of AND, OR, and NOT gate combination. Grid size is 130 × 170, the channels are 20 grid points wide.

FIG. 3.

Structure of AND, OR, and NOT gate combination. Grid size is 130 × 170, the channels are 20 grid points wide.

Close modal

Three fundamental logical functions of the device are described below:

  1. OR gate: The output channel of OR gate is connected to the ring channel directly. The output is 0 only if no pulse appears at A or B; otherwise, an output pulse is sent through the channel, which gives 1 as the output.

  2. AND gate: The output channel of AND gate is in the middle of the ring and connected to a coincidence detector. With the presence of two input pulses, the detector becomes excited and the output is 1; in other cases, the detector is not excited and the output is 0.

  3. NOT gate: In this case, input A is used as auxiliary 1 input. The output channel is at the bottom and also connected to a coincidence detector. With the absence of pulse at B, the pulse from A propagates through the channel, forks and the two pulses collide at b, then a new pulse is generated, and the output is 1. However, if there is a pulse at B, the two pulses meet at a, as a result, the output is 0.

Note that the pulses from input A/B propagate into B/A, which has no influence on the outputs. Hence, we do not add chemical diodes25–27 in front of the inputs for simplicity. Simulation results of this device can be found in the supplementary material.28 Table I lists all the possible inputs and the corresponding outputs. It is found that the device realizes AND, OR, and NOT logic operations simultaneously.

Table I.

Functionality of AND, OR, and NOT gate combination.

ABA OR BA AND BNOT B
ABA OR BA AND BNOT B

We discuss the design and realization of decoders in this section. To simplify the design and implementation, it is desirable for the structures to satisfy a number of criteria:

  1. Making the structures as small as possible.

  2. The width of the channel is set to 20 grid points.

  3. Using penetration for pulse delay; the width of the gap is set to 8 grid points.

  4. The width of both active regions and passive regions is set to multiples of 10 grid points except penetration. Hence, the distance between two parallel channels is at least 10 gird points, and the distance between the channels and the borders is at least 10 grid points too.

  5. The length of the detector bar in T-shaped coincidence detector is set to 40 gird points. Hence, if two parallel channels are connected to coincidence detectors, the distance between them is at least 30 grid points (see Fig. 4).

FIG. 4.

Two parallel channels connected to coincidence detectors. The unit is 10 grid points wide and high.

FIG. 4.

Two parallel channels connected to coincidence detectors. The unit is 10 grid points wide and high.

Close modal

A one-bit binary decoder (1 to 2 decoder) has one input A and two outputs Y1 and Y0. When A = 1, the outputs (Y1 and Y0) are 1, 0; When A = 0, the outputs are 0, 1. To perform this function in BZ medium, an auxiliary 1 input is needed, which is input E (Enable) in the truth table (see Table II).

Table II.

Truth table of one-bit binary decoder.

EAY1Y0
EAY1Y0

The Boolean relationships between the inputs and outputs are given by Eq. (3). We build the one-bit binary decoder simply by removing OR gate from AND, OR, and NOT gate combination, which is implemented in Sec. III C,

\begin{eqnarray}\rm {Y_0} &=& \rm {NOT\ A} = \rm {\tilde{A}},\nonumber \\[-6pt]\\[-6pt]\rm {Y_1} &=& \rm {A\ AND\ E} = \rm {A} \cdot \rm {E}.\nonumber\end{eqnarray}
Y0= NOT A=Ã,Y1=A AND E=A·E.
(3)

Figure 5 illustrates the structure of one-bit binary decoder, where, A and E (auxiliary 1 input) are input channels, Y1 and Y0 are output channels. The structure is optimized by using the geometrical constraints (see more detail in the supplementary material28). For the one-bit binary decoder, we only need to consider two cases of the inputs:

  1. A = 0 (E = 1): With the absence of input A, pulse from E propagates through the channel and forks, two pulses collide and annihilate, then a new pulse is generated and sent through output Y0, so the outputs (Y1 and Y0) are 0, 1.

  2. A = 1 (E = 1): Pulses from A and E propagate through the channel, collide, and annihilate, generating and sending a new pulse through output Y1, so the outputs are 1, 0.

FIG. 5.

The structure of one-bit binary decoder. Grid size is 130 × 160. Each unit is 10 grid points wide and high.

FIG. 5.

The structure of one-bit binary decoder. Grid size is 130 × 160. Each unit is 10 grid points wide and high.

Close modal

Images extracted from time-series simulations are shown in Fig. 6 (cf. Videos 1 and 2).

FIG. 6.

Pathway of pulse propagation in the one-bit binary decoder when inputs (E and A) are (a) 1, 0. (b) 1, 1 (enhanced online). [URL: http://dx.doi.org/10.1063/1.4794995.1] [URL: http://dx.doi.org/10.1063/1.4794995.2]

FIG. 6.

Pathway of pulse propagation in the one-bit binary decoder when inputs (E and A) are (a) 1, 0. (b) 1, 1 (enhanced online). [URL: http://dx.doi.org/10.1063/1.4794995.1] [URL: http://dx.doi.org/10.1063/1.4794995.2]

Close modal

A two-bit binary decoder (2–4 decoder) has two inputs B and A, and four outputs Y11, Y10, Y01, and Y00. The truth table with an auxiliary 1 input E is shown in Table III.

Table III.

Truth table of two-bit binary decoder.

EBAY11Y10Y01Y00
EBAY11Y10Y01Y00

From the truth table, we obtain

\begin{eqnarray}\rm {{{Y_{00}} = \tilde{A} \cdot \tilde{B}}},&\quad \rm {{{Y_{01}} = A \cdot E \cdot \tilde{B}}},\nonumber \\[-6pt]\\[-6pt]\rm {{{Y_{10}} = \tilde{A} \cdot B}},&\quad \rm {{{Y_{11}} = A \cdot E \cdot B}}.\nonumber\end{eqnarray}
Y00=÷B̃,Y01=A·E·B̃,Y10=÷B,Y11=A·E·B.
(4)

The two-bit binary decoder has three inputs. For output Y11, only when all three inputs are present, the result is 1. It is difficult and complicated to construct the device directly according to Table III and Eq. (4). We adopt a cascade method to solve this problem.

Substituting Eq. (3) into Eq. (4), we have

\begin{eqnarray}\rm {{{Y_{00}} = {Y_0} \cdot \tilde{B}}},&\quad \rm {{{Y_{01}} = {Y_1} \cdot \tilde{B}}},\nonumber \\[-6pt]\\[-6pt]\rm {{{Y_{10}} = {Y_0} \cdot B}},& \quad \rm {{{Y_{11}} = {Y_1} \cdot B}}.\nonumber\end{eqnarray}
Y00=Y0·B̃,Y01=Y1·B̃,Y10=Y0·B,Y11=Y1·B.
(5)

Equation (5) links the two-bit decoder with the one-bit decoder. We construct the two-bit decoder based on the one-bit decoder. The two-bit decoder is divided into two parts as shown in Fig. 7: a one-bit decoder with lower bit input A and auxiliary 1 input E as inputs, a rectangular ring channel with the outputs of the one-bit decoder Y1, Y0 and higher bit input B as inputs. Since Y1 and Y0 are not 1 simultaneously, the rectangular ring has at most two 1 inputs, which makes the design simpler.

FIG. 7.

Schematic diagram of two-bit binary decoder.

FIG. 7.

Schematic diagram of two-bit binary decoder.

Close modal

The structure of two-bit binary decoder is shown in Fig. 8, in which, the length of the output channels of the one-bit decoder is adjusted to keep the pulses in pace. The geometrical constraints are employed to make the structure smaller. The supplementary material28 shows how to calculate the size of the structure.

FIG. 8.

The structure of two-bit binary decoder. Grid size is 260 × 270. Each unit is 10 grid points wide and high.

FIG. 8.

The structure of two-bit binary decoder. Grid size is 260 × 270. Each unit is 10 grid points wide and high.

Close modal

The higher bit input (input B) channel of the two-bit decoder can be put on the top or at the bottom of the rectangular ring. Since the output channel Y1 is over the output channel Y0 in the one-bit decoder, with the absence of higher bit input B, the output channel Y00 is over the output channel Y01 in the two-bit decoder. We set the input channel B to the top of the ring, so that the output channels are arranged in numerical order (Y00, Y01, Y10, and Y11 from top to bottom). Otherwise, the output order should be Y10, Y11, Y00, Y01, if the input channel B is at the bottom.

Figure 9 (cf. Videos 3 and 4) shows the simulation results of the two-bit binary decoder with input (E, B and A) 110, and 111. In Fig. 9(a) (cf. Video 3), Pulses propagate from input E and B, but not from input A. In one-bit decoder, Y0 has an output pulse. The pulses from B and Y0 collide and generate a new pulse in output channel Y10, suggesting the output (Y11, Y10, Y01, and Y00) is 0100. In Fig. 9(b) (cf. Video 4), With E, B, A all having pulses, the pulses is sent through Y1 and Y11 in one-bit and two-bit decoders, respectively, so the output is 1000. Other simulation results can be found in the supplementary material.28 

FIG. 9.

Pathway of pulse propagation in the two-bit binary decoder when inputs (E, B, and A) are (a) 1, 1, 0. (b) 1, 1, 1 (enhanced online). [URL: http://dx.doi.org/10.1063/1.4794995.3] [URL: http://dx.doi.org/10.1063/1.4794995.4]

FIG. 9.

Pathway of pulse propagation in the two-bit binary decoder when inputs (E, B, and A) are (a) 1, 1, 0. (b) 1, 1, 1 (enhanced online). [URL: http://dx.doi.org/10.1063/1.4794995.3] [URL: http://dx.doi.org/10.1063/1.4794995.4]

Close modal

Three-bit binary decoder (3–8 decoder) has three inputs C, B, and A, an auxiliary 1 input E, and eight outputs Y111, Y110, Y101, Y100, Y011, Y010, Y001, and Y000. Table IV lists all possible inputs and the corresponding outputs. Similarly, Eq. (6) describes the relationship between the outputs of the two-bit decoder and the three-bit decoder:

\begin{eqnarray}\rm {{Y_{000}} = {Y_{00}} \cdot \tilde{C}},&\quad \rm {{Y_{001}} = {Y_{01}} \cdot \tilde{C}},\nonumber \\\rm {{Y_{010}} = {Y_{10}} \cdot \tilde{C}},&\quad \rm {{Y_{011}} = {Y_{11}} \cdot \tilde{C}},\nonumber \\[-8pt]\\[-12pt]\rm {{Y_{100}} = {Y_{00}} \cdot C},&\quad \rm {{Y_{101}} = {Y_{01}} \cdot C},\nonumber\\\rm {{Y_{110}} = {Y_{10}} \cdot C},&\quad \rm {{Y_{111}} = {Y_{11}} \cdot C}.\nonumber\end{eqnarray}
Y000=Y00·C̃,Y001=Y01·C̃,Y010=Y10·C̃,Y011=Y11·C̃,Y100=Y00·C,Y101=Y01·C,Y110=Y10·C,Y111=Y11·C.
(6)
Table IV.

Truth table of three-bit binary decoder.

ECBAY111Y110Y101Y100Y011Y010Y001Y000
ECBAY111Y110Y101Y100Y011Y010Y001Y000

We build a three-bit binary decoder by the similar method. As shown in Fig. 10, the three-bit decoder consists of a two-bit decoder and a rectangular ring channel. In this structure, penetration units are used for pulse delay. In order to arrange the output channels in numerical order, the highest bit input (input C) channel is set to the bottom of the rectangular ring. We optimize the structure by the geometrical constraints described in Sec. IV A.

FIG. 10.

The structure of three-bit binary decoder. Grid size is 440 × 560.

FIG. 10.

The structure of three-bit binary decoder. Grid size is 440 × 560.

Close modal

Figure 11 (cf. Video 5) shows the simulation result with input (E, C, B, and A) 1111. With the presence of all inputs, the pulses is sent through Y1, Y11, and Y111 in one-bit, two-bit, and three-bit decoders, as a result, the final output (Y111, Y110, Y101, Y100, Y011, Y010, Y001, and Y000) is 10 000 000. Other simulation results can be found in the supplementary material.28 Using the same basic structure and principle, higher bit decoders can be implemented easily.

FIG. 11.

Pathway of pulse propagation in the three-bit binary decoder when inputs (E, C, B, and A) are 1, 1, 1, 1 (enhanced online). [URL: http://dx.doi.org/10.1063/1.4794995.5]

FIG. 11.

Pathway of pulse propagation in the three-bit binary decoder when inputs (E, C, B, and A) are 1, 1, 1, 1 (enhanced online). [URL: http://dx.doi.org/10.1063/1.4794995.5]

Close modal

In this paper, we have discussed how to build binary decoders based on BZ reaction platform. The one-bit binary decoder is constructed by integrating AND gate and NOT gate, in which, a T-shaped coincidence detector is involved. The two-bit binary decoder includes a one-bit decoder and a rectangular ring channel. This device uses the outputs of the one-bit decoder as the inputs of the rectangular ring, and achieves the function of 2-to-4 decoding. Similarly, the three-bit binary decoder is designed based on the two-bit decoder. With the same cascade method, higher bit binary decoders can be constructed.

The binary decoders are implemented in numerical simulations using only T-shaped structures for coincidence detection, penetration units for time delay, and straight channels for pulse propagation. Since these existing components have already been verified in experiments, we believe that our decoders work well in BZ medium. Note that we should control the input pulses carefully in chemical experiments, thus, the pulses will meet in the right areas, and corresponding decoding information will be outputted.

As a basic combinational logic circuit, binary decoder is widely used in the field of digital electronics. The chemical realization of binary decoders expands the functions of chemical computation, facilitating the constructions of chemical computer and other intelligent systems.

We are grateful to the National Natural Science Foundation of China (NSFC) (Grant Nos. 61273341, 61105107, and 91023045), the National High Technology Research and Development Program (“863” Program) of China (Grant No. 2013AA041102), the Research Fund for the Doctoral Program of Higher Education of China (Grant No. 20110031110032), and the Fundamental Research Funds for the Central Universities (Grant No. 65012081).

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Supplementary Material