Scaling effects on the microstructure and thermomechanical response of through silicon vias (TSVs)

With the continuous miniaturization of transistors in microelectronics, three-dimensional heterogeneous integration has attracted tremendous attention due to its potential to achieve a high-performance 3D computations system and extend the benefits of Moore's law without scaling the transistors in the font-end-of-line (FEOL).¹ Through silicon via (TSV) is a crucial component for 3D integration as it enables the high-density interconnection and high bandwidth communication between vertically 3D stacked dies. TSV with a diameter of >5 μm has been widely studied in advanced semiconductor technologies such as silicon interposers and high bandwidth memory,² which has become an essential part of high-performance computing units for artificial intelligence, supercomputers, and graphic cards.³ To meet the future needs of memory transistor scaling while also enabling backside power delivery networks (BSPDN), the TSV size and pitch must be further scaled to the submicrometer range with targets of ultrahigh interconnect density of >10⁶/mm² (i.e., ∼1 TSV/μm).⁴ 

A TSV is essentially a metal wire embedded vertically inside the silicon substrate. The typical structure of TSV is composed of a central metal interconnect surrounded by thin films such as the dielectric insulator, the diffusion barrier, and the adhesion liner. Copper, widely used as a metal conductor for via-middle and via-last TSV processes, has a coefficient of thermal expansion (CTE) 6× as large as silicon. As a TSV is thermally loaded during either fabrication or operation, CTE mismatch can lead to significant mechanical strain and stress within both the Cu and surrounding Si, which can degrade both reliability and performance. TSV-induced thermal stress, for example, is known to induce interfacial delamination,⁵ Cu pumping,⁶ and undesired carrier mobility change in Si due to its piezoelectric properties.⁷ Therefore, understanding the thermomechanical response of TSV is of great importance in the design and development of advanced 3D-integrated circuits.

While the thermomechanical response of micro-TSV has been extensively studied, knowledge gaps remain as the structures scale toward 1 μm and smaller. It remains unclear, for example, whether scaling TSVs will alter the degree to which plasticity impacts mechanical response upon thermal processing. For larger TSVs (>5 μm diameter), wafer warpage,^6,8–11 Cu pumping,^12–14 device performance,^7,15–17 and thermal stress^18–26 have each been studied as a function of TSV diameter. Based on these prior studies, larger Cu TSVs (>5 μm diameter) and the surrounding silicon are known to each respond in a nearly elastic manner after being annealed at high temperatures. For example, Beyne²⁷ and Wolf et al.⁶ studied the evolution of TSV wafer warpage during high-temperature thermal annealing and subsequent thermal cycling and found a nearly elastic response in both Cu and Si. Similarly, temperature sensitive examinations of carrier mobility within metal–oxide–semiconductor field-effect transistors (MOSFET) near Cu TSVs exhibited a linear response implying an elastic response of Si near the TSV.^7,15 Microbeam x-ray diffraction, meanwhile, has observed local plastic deformations near the Cu-surface even as the buried-Cu and surrounding Si remain elastic.²⁸ Plasticity has also been observed in Cu films subject to comparable thermal annealing while similarly sized TSVs analyzed concurrently exhibited an elastic response.¹¹ Taken together, it must, therefore, be concluded that the morphology and size together dictate the thermomechanical response of TSVs, thus warranting an examination as these structures continue in their miniaturization.

This examination is further motivated when considering the known size dependence of mechanical properties in metals at even the micrometer scale. Uchic et al.,²⁹ for example, measured the yield strength of micro-sized single crystals. They reported that at the micrometer scale, the extrinsic length scale, namely, the diameter of the micro-cylinder, impacts the mechanical strength. The yield strength of the single crystal was found to increase dramatically as the specimen size shrinks. Subsequent studies have supported this conclusion and extended it to various crystal materials, including copper.³⁰ Apart from the extrinsic length scale, the intrinsic length (i.e., the grain size) also contributes to the mechanical strength of polycrystals. The classical Hall–Petch theory predicts that mechanical strength increases with the decrease in the grain size.³¹ Recently, it has been demonstrated that as the sample size approaches the microscale, the increased surface-to-volume ratio plays an important role, leading to a deviation from the Hall–Petch theory.³² Furthermore, an inverse Hall–Petch has also been proposed for grains with a size of several tens of nanometers.³³ 

These extrinsic and intrinsic length scales are each at play for micrometer-scale TSVs. Electroplated Cu exhibits grain sizes that are typically submicrometer in size. With thermal annealing, Cu-grains are known to grow to sizes exceeding a micrometer that act to relieve strain via “pump out.”²⁸ Thus, micrometer-scaled TSVs have diameters comparable to the grains themselves. It is, therefore, possible that grain growth—and, hence, the mechanical response known to be affected by grain size—could change with TSV scaling.

An investigation incorporating stress measurement and size-dependent material microstructure characterization is, therefore, needed to assess how dimensional scaling impacts the thermomechanical response of micro-TSVs. In response, we systematically quantify stress changes within the Si surrounding TSVs as their diameters shrink from 5 to 1 μm while maintaining a 5:1 aspect ratio using Raman spectroscopic stress imaging. An analytical model is proposed and utilized to explain the experimentally measured stress that considers local Cu shrinkage and global wafer bowing, which indicates that the TSVs respond predominately in an elastic manner. The persistence in the elastic response is considered in light of diameter-dependent changes in the grain size that are quantified with electron backscatter diffraction.

TSV arrays having diameters ranging from 1 to 5 μm and an aspect ratio of ∼5:1 were fabricated on 1 × 1 cm² die taken from a 525 μm thick Si-wafer. The array pitch was fixed at 10 μm to allow comparison between the different via diameters. The pitch between TSVs can also be a significant design factor, which will be addressed in our future work. These sizes resulted in die nearly covered by arrays that provided approximately ∼1 × 10⁶ TSVs per die for characterization. As shown schematically in Fig. 1(a), the process flow for array fabrication begins by first forming the blind vias with Deep Reactive Ion Etching (DRIE) Bosch etching of the silicon. The etch was followed by a series of thin-film depositions including in order 60 nm SiO₂ insulator, 25 nm Ti barrier, and 300 nm Cu seed layer. The thickness of the Cu seed layer is measured on the top surface of TSV sample and indicates the upper bound of seed layer thickness. Void free metal filling was then achieved with bottom-up Cu electroplating. Chemical mechanical polishing (CMP) was performed after electroplating to expose the TSV vias by removing the overplated copper and using the SiO₂ layer as an etch stop. Finally, TSVs were thermally annealed in a forming gas-purged furnace at 400 °C for 1 h after the CMP TSV via revealing process. The detailed process and optimization of TSV fabrication can be found in our previous work.³⁴ 

TSV-array is inspected with cross-sectional imaging using scanning electron microscopy (SEM) and focused ion beam (FIB). Briefly, arrays are first cross-sectioned with ion milling, creating a through cut with a width of several hundreds of micrometers and a rough cross section. These cross-sectioned samples are then transferred to an SEM/FIB system, where smooth TSV cross sections are created with further polishing. EBSD (electron backscatter diffraction) was then performed on a subset of TSVs to characterize the grain size and orientation of the copper microstructure before and after annealing.³⁴ The 52° tilted FIB image in Fig. 1(b) shows the high-quality, void-free filling, of different-sized electroplated Cu TSVs. Figure 1(c) shows the corresponding top-view optical images of arrays with variable diameter after the excess Cu-layer was removed by CMP. The diameters of TSVs were measured with top-view SEM imaging and rounded to the nearest micrometer when mentioned below. Together, these micrographs indicate the fabrication of relatively uniform, void free, arrays of diameters ranging from 1 to 5 μm.

Stress was quantified within the Si surrounding the TSV using Raman spectroscopy in a backscattered arrangement. Both linescan and image-based measurements were performed by rastering the laser over the sample with a piezo-stage and acquiring a spectrum every 200 or 250 nm, respectively. This was realized using a WiTec alpha300R spectral imaging system employing a 532 nm laser focused to a diffraction limited spot size onto the top Si surface of the TSV-array with a 100×/0.9 objective at a laser flux of <10 mW/μm². Separate power dependent studies ensured minimal heating of the Si at this flux. Raman scattered light was directed to a 600 mm focal-length Czerny-Turner type spectrometer equipped with an 1800l/mm grating, resulting in a spectral precision in the determination of the Si phonon energy of Δω ∼ 0.05 cm⁻¹.

With this precision and the known calibration response of the Si Raman signal to biaxial stress (D = −3.6 cm⁻¹/GPa),³⁵ stress differences of as little as 14 MPa were resolvable. Absolute stress measurements require the knowledge of the stress free, or reference, energy $( ω o∼520.4 c m − 1)$ of the Si Raman peak. Day to day variations in the spectrometer calibration and laser wavelength can cause the reference energy of the Si signal to fluctuate by far more than the system precision Δω unless in some way corrected. For this reason, a bare (001) Si surface analogous to that used in TSV-array fabrication was examined before each Raman measurement to directly specify the stress-free reference. Practically, two-hundred spectra were collected from the bare Si over a line spanning 20 μm. The average Raman peak position over these 200-spectra was then taken as ω_o. The biaxial stress (σ) was then calculated when measuring the TSV-array via the standard relation linking the measured peak position (ω) to this reference position via $σ=( ω − ω o)/D$⁠. The daily measurement of the reference position enables absolute measurements having an uncertainty that is comparable to the precision in the system of 14 MPa. The precision of stress measurement is further improved with repeated measurements and increased collection time of the Raman signal.

Thermal annealing is an important process in TSV fabrication as it stabilizes the microstructure of Cu³⁶ and reduces the Cu pumping of via-middle TSV in the back-end-of-line (BEOL) process.⁶ However, thermal annealing can also generate considerable residual stress due to the CTE mismatch between the differing materials making up the TSV. Before annealing, electrodeposited Cu is in a fine-grained and low-stress state.³⁷ With annealing, Cu changes in its microstructure and volume. This alters not on the stress with the Cu portion of the TSV but also the surrounding Si as well.

For example, upon the initial application of the thermal load, the large CTE mismatch between the Cu and Si generates considerable thermal stress inside the TSV. As time advances, plastic deformation and recrystallization²⁷ of Cu gradually release the thermal stress, bringing the whole structure to a stress-free state at a temperature typically between 115 and 400 °C.^{7,10,15,17,38} This high-temperature stress relief is accomplished primarily through “pumping” of the metal that results in permanent Cu protrusion above the Si surface that occurs in tandem with significant grain growth.^9,13 Cooling from this low-stress state induces stress into the structure once again owing to the CTE mismatch. The Cu core shrinks toward the center of the TSV pulling against Si resulting in a notable residual stress in the entire TSV structure (i.e., Cu, barrier layer, dielectric, and Si). The magnitude of stresses within the materials will be dictated by not only the process but so too the diameter of the TSV and the microstructure of the Cu.

To examine the TSV's effect on the surrounding Si, stress was quantified along the centerline connecting two adjacent TSVs, as is shown by the schematics of Fig. 2. The resulting stress profiles for differing TSV diameters are also provided in Fig. 2, where the raw data of every spectrum are accompanied by a moving average over 9 separate spectral acquisitions. As expected, owing to the larger CTE of Cu relative to Si, the stress is found to be compressive within the semiconductor near the Cu core. This is consistent with previous studies.²² Despite being qualitatively similar, TSV diameter does impact the stress profile. Significant differences in the magnitude and trend of the stress within the Si are observed as the TSV diameters scale from 4 to 1 μm in diameter.

Owing to the constant 10 μm pitch (P) between vias, smaller TSVs show less mechanical crosstalk and, as a consequence, lower average stress. The smallest 1 μm diameter TSVs, for example, exhibit a stress profile that transitions from compression closest to the metallic core to one of slight tension before dissipating to a nominally stress-free state 2 μm from the edge of a via [see Fig. 2(a)]. This leaves roughly 6 μm of Si that is stress free. Larger diameter TSVs do not, however, have a sufficient span of silicon for this relaxation to take place as can be seen in Figs. 2(b) and 2(c) for the 2 and 4 μm arrays. Stress does not fully relax between these larger vias due to the crosstalk culminating in a larger average stress even at the midpoint between individual vias.

Using this midpoint stress between vias as a proxy for stress effects in the Si, the magnitude of equivalent stress at the center of gaps between was quantified for different TSV diameters. The distance between the center of the gap to the nearest TSV center is consistently 5 μm for all TSV arrays, ensuring a fair comparison between different TSV sizes. As shown in Fig. 3, a line scan is performed on the centerline of the gap between TSVs, and the average residual stress value at the gap center is calculated. For each data point in Fig. 3, the stress value is comprised of an average among 10 separate gaps between TSVs for a given diameter, where each gap was itself measured with five individual line-scans. Stress increases until reaching a maximum at a diameter of ∼4.5 μm before decreasing. The non-monotonic dependence of stress on the TSV size can be explained by considering the combined effects of global bending and local shrinkage of Cu TSVs, which are discussed in detail with the elastic model proposed in the next session.

A linear elastic analytical model is proposed to understand the mechanism behind the mechanical behavior of TSV-induced thermal stress. The model is developed based on the superposition principle. The stress field of the TSV-array is decomposed into two parts, namely, the global stress induced by the sample warpage and the local stress distribution caused by the shrinkage of Cu cores in TSVs. Both the stresses induced by global bending and local shrinkage are assumed to be biaxial stresses, allowing the addition of the two stress components. To simplify the model, the nanoscale dielectric (SiO₂) and barrier (Ti) layers are neglected leaving only Cu and Si. The microstructure and stress state of Cu seed layer can be different from the electroplated copper.³⁹ Such an impact was not considered due to the reduced seed layer thickness within the TSV structure. The mechanical properties of these materials are taken from the literature,¹⁰ as listed in Table I.

The Raman stress image along with the stress distribution connecting TSV centers is compared with the analytical model in Fig. 4, where a notable consistency is found between theory and experiment. The stress contours in Figs. 4(a) and 4(b)—along with the linescan of Fig. 4(c)—each indicate a concentration of compressive stress near the Cu core that rapidly transitions to tension upon moving from the TSV core. The similarity between experiment and theory extends to all examined diameters as seen in Fig. 4(d). Importantly, the measured non-monotonic average stress at the centerline between two adjacent TSVs having a maximum at a diameter near 4.5 μm is predicted by the elastic analytical treatment considering only local stress induced by Cu shrinkage and global bending.

Beyond indicating that the mechanical behavior is largely elastic for the examined diameter range, correlation between experiment and theory provides a perspective to understand the TSV-induced evolution of stress. With the increase of TSV diameter, for example, the volumetric ratio of Cu increases. Its effect becomes, therefore, more pronounced. On one hand, more copper enhances the impact of Cu shrinkage and, thus, the compressive stress in the silicon. On the other hand, a greater amount of copper provides more force to bend the wafer that induces tension in the silicon. These countervailing effects vary with diameter at differing rates. Bending dominating at smaller diameters that then gives way to shrinkage. The trade-off in the dominance of these effects leads to the non-monotonic trend.

We speculate that the elastic response persisting at smaller diameters is a consequence of strengthening in the Cu that occurs with a decrease in grain size caused by the geometric constraint of the TSV diameter itself. This statement is arrived at by considering diameter-dependent changes in the microstructure observed in EBSD in conjunction with known grain size dependence of yield strength in Cu.³⁰ As shown in Fig. 5, the TSV diameter impacts the Cu grain size. Larger diameters lead to larger grains. The average grain size roughly scales to the radius of the TSV after annealing [see Fig. 5(c)]. These differences in the grain size have consequences for the mechanical response. Additionally, the EBSD images show the uniform microstructure of copper inside the TSV, illustrating a good consistency between the copper seed layer and the electroplated copper.

Smaller grain size limits the generation of dislocations and strengthens Cu.³² Moreover, smaller grain sizes inherently increase the concentration of grain boundaries, which limit the motion of dislocations.³⁷ A reduced number of dislocation and a slowing of their motion lead to enhanced strength. In combining these two effects: it can be inferred that the yield strength of Cu will increase as the TSV diameter is scaled down. Given the nearly elastic thermomechanical response previously reported for thermally annealed TSVs with diameters >5 μm^7,27,38 with the grain size boost in strength at even smaller diameters, the observation of an elastic response here is consistent with expectation after the TSV annealing process.

The effects of scaling on the thermomechanical response of Cu TSVs with a diameter spanning from 1 to 5 μm are investigated with Raman stress measurement and EBSD grain characterization before and after thermal annealing. The measured stress increases with diameter up to a maximum near 4.5 μm before decreasing. The non-monotonic trend is explained using an analytical model that includes the competition between global bending and local CTE mismatch including purely elastic effects, which correlates well with measured stress. The grain size of Cu is also dictated by the TSV scaling having an average size that roughly corresponds to via radius. This geometric dependence on the grain size increases the yield strength of the Cu and, thus, will likely extend elastic effects to some degree with continued scaling of this technology integral for advanced system architectures.

This work was supported by the Semiconductor Research Corporation (SRC) as a part of the Global Research Collaboration (GRC) in the Center for Heterogeneous Integration Research on Packaging (CHIRP). The fabrication and EBSD characterizations are also supported by Dr. Tiwei Wei's start-up funds from Purdue University. We thank our SRC liaisons, Yu-Tao Yang from MediaTek, and Se-Ho You from Samsung for their feedback and input.

The authors have no conflicts to disclose.

Shuhang Lyu: Conceptualization (equal); Data curation (equal); Formal analysis (equal); Investigation (equal); Methodology (equal); Visualization (equal); Writing – original draft (equal). Thomas Beechem: Conceptualization (equal); Funding acquisition (equal); Methodology (equal); Project administration (equal); Resources (equal); Supervision (equal); Writing – review & editing (equal). Tiwei Wei: Conceptualization (equal); Formal analysis (equal); Funding acquisition (equal); Investigation (equal); Project administration (equal); Resources (equal); Supervision (equal); Writing – review & editing (equal).

The data that support the findings of this study are available from the corresponding author upon reasonable request.