Conventional computing architectures are not suited to meet the unique workload requirements of artificial intelligence and deep learning, which has sparked a growing interest in memory-centric computing. One primary challenge in this field is sneak path current in memory devices, which degrades data storage and reliability. Another critical issue is ensuring device performance stability over time and under varying environmental conditions. To overcome these challenges, in this work, we introduce a Dion–Jacobson perovskite-based self-rectifying memory cell that not only reduces the sneak path current but also demonstrates remarkable stability in electrical parameters. The fabricated device maintains consistent performance, including rectification ratio (∼103), on/off ratio (∼103), and set voltage (∼0.52 V), for over 200+ days within a temperature range of 25–70 °C and relative humidity conditions up to 70%RH. Importantly, our work represents an innovative step forward in the observation of self-rectification and stable performance in perovskite-based devices, showing the way for their widespread application in memory-centric computing architectures. Furthermore, to understand the electrical behavior across its different states, i.e., high resistance state and low resistance state, electrochemical impedance spectroscopy is performed, which gives insight into the individual contribution of resistance, capacitance, and inductance.
I. INTRODUCTION
Recent trends in the field of computation have ushered in a significant paradigm shift, moving away from conventional computing approaches and increasingly embracing memory-centric computing. This profound transformation is being primarily driven by the ever-expanding demands of artificial intelligence (AI) and deep learning applications.1–3 In the world of traditional computing, a notable limitation arises when dealing with AI and deep learning workload, namely, the substantial volume of data that needs to be transferred between separate memory modules and processing units. This frequent back-and-forth data movement introduces significant latencies and energy consumption, hindering the overall efficiency of these computations.4 To address this challenge, a transformative approach is emerging, wherein the focus shifts toward memory-centric computing.5,6 These innovative memory solutions aim to satisfy consumer demands for memory products that offer greater capacities and improved performances, while also alleviating the data transfer bottlenecks seen in traditional computing architectures. To tackle this inefficiency, memristive devices have garnered significant attention in the realm of data storage and processing, as well as bio-inspired computing.7 The appeal of the memristor lies in their dynamic behaviors, which closely resemble the synaptic and neuronal functions found in biological systems.8 Memristive devices typically feature a straightforward sandwich structure, making them ideal for constructing crossbar arrays and facilitating large-scale integration. Although memristive devices have significant potential for data storage, there are a few critical challenges such as sneak path current and device stability in the development of memristor-based crossbar arrays. Sneak currents can substantially compromise the performance of both memristor and neural networks because they lead to unwanted crosstalk and data corruption.9,10 To address this issue, a common solution involves the integration of transistors alongside resistors in a series configuration, often referred to as 1T1R (one transistor–one memristor).11,12 This configuration effectively diminishes the sneak current problem, ensuring that data can be read and written accurately. Nevertheless, while the 1T1R configuration resolves the sneak current issue, it introduces a new layer of complexity to the crossbar array's architecture. The integration of an additional access device in each cross-point not only increases the physical complexity but also adds to the computational overhead and power consumption, which is contrary to the objective of achieving memory-centric computing simplicity and efficiency. As a result, there is a growing and compelling demand within the field for memristive devices to develop new device structures that possess self-rectifying characteristics, such as self-rectifying memory cells (SRMCs).13,14 SRMCs incorporate asymmetry and nonlinearity into their current–voltage characteristics to decrease the sneak path currents, making them highly desirable for high-density memory applications in memory-centric computing without the need for additional access devices.15–18 Moreover, perovskite-based devices are frequently characterized by their inherent instability, which poses significant challenges for practical applications. Therefore, in this study, a novel Dion–Jacobson (DJ) perovskite with quasi-2D layered structure and the 3-(aminomethyl)piperidinium (3AMP)-based spacer cation has been used that exhibits remarkable stability for over 200+ days. The electrical parameters of the memristor, such as the on/off ratio, rectification ratio, and set voltage, remain consistent under external environmental conditions, including temperatures up to 70 °C and relative humidity up to 70%RH. This enhanced stability significantly contributes to the robustness and reliability of the device, making it a promising candidate for data storage and artificial brain-like neuromorphic computing applications.
The memristor device undergoes a transition from the high resistance state (HRS) to low resistance state (LRS), when a suitable set voltage or threshold voltage is applied. Between the HRS and LRS, the memristor exhibits diverse electrical properties, including resistive, capacitive, and inductive behaviors to varying degrees. Typically, the HRS demonstrates resistive and capacitive characteristics, while the LRS at low frequency may exhibit inductive features.19 Understanding these properties is crucial for characterizing memristive devices effectively. Electrochemical impedance spectroscopy (EIS) is a powerful technique capable of measuring all three key properties of a memristor (resistive, capacitive, and inductive) using an equivalent circuit model. By analyzing the impedance response of the device, EIS provides detailed insight into the individual contributions of resistance, capacitance, and inductance, enabling a comprehensive understanding of the memristor's electrical behavior across its different states.20,21 In the process of EIS measurement, time-dependent voltage signal represented by V = Vdc + Vac sin (2πft) was applied, where Vdc was varied for different states of memristor, i.e., HRS and LRS, and Vac, which is commonly known as perturbation voltage. The corresponding complex impedance Z = Z′ + iZ′′ is measured as a function of frequency and presented through the Nyquist plot.
Furthermore, the neuromorphic characterization of a memristor device has potential to replicate cognitive tasks, which holds paramount importance in the realm of artificial intelligence.22 In order to replicate cognitive tasks, a particular focus is on the correlation of memristor characteristics with the alpha, gamma, and delta phases of the brain, which have not been extensively explored in prior research. By harnessing the properties of memristor to replicate the alpha, beta, and gamma phases of brain activity, one can unlock new capabilities in artificial intelligence with greater efficiency, adaptation, and proficiency in complex cognitive functions. Furthermore, neuromorphic characterizations like spike time dependent plasticity (STDP), spike duration dependent plasticity (SDDP), and spike-number-dependent plasticity (SNDP) were performed to demonstrate that the device can function effectively as a synaptic element. These characterizations provide crucial evidence supporting the potential of memristor-based systems to emulate biological synapses, thereby enhancing their applicability in neuromorphic computing and artificial neural networks.
II. RESULTS AND DISCUSSION
A. Current–voltage characterization
In this study, two device configurations were proposed through modifications in interface engineering using low-dimensional perovskite as an active layer. The structural and morphological properties of the low-dimensional perovskite active layer are characterized by x-ray diffraction (XRD) and scanning electron microscopy (SEM), which follows the previous literature23 (Fig. S1 in the supplementary material). The first memristor device configuration is ITO/PEDOT:PSS/active layer/Ag and the second is ITO/PEDOT:PSS/active layer/PMMA/Ag [Fig. 1(a)]. The complete fabrication process is discussed in the Experimental Details section. The current–voltage (I–V) study of the first device reveals a set voltage of around ∼0.9 V and, low on/off ratio as shown in Fig 1(b). Current–voltage (I–V) characteristics were recorded in the DC sweeping mode (0 V → 1 → 0 → −1 → 0 V), with an external bias applied to the Ag top electrode (TE) and ITO bottom electrode (BE) grounded. In device structure ITO/PEDOT:PSS/active layer/PMMA/Ag, the top contact interface was modified by applying a poly(methyl methacrylate) (PMMA) coating on the active layer to restrict the direct diffusion of Ag ions and protect the device against humidity, enhancing its environmental stability and operational life span.24 The I–V curve of ITO/PEDOT:PSS/active layer/PMMA/Ag device displayed in Fig. 1(b) is highly nonlinear and asymmetric, resembling the features typically associated with self-rectifying memory cell (SRMC). In a SRMC, this asymmetry leads to rectification behavior, where current flows more readily in one direction than in the reverse direction.25 This property is highly desirable for large-scale crossbar array applications, which can be crucial for building memory cells and crossbar application.
Schematic of the device configuration, along with the statistical data and mechanism analysis of the current–voltage (I–V) characteristics. (a) Device architecture of ITO/PEDOT:PSS/active layer/PMMA/Ag, (b) current–voltage (I–V) characteristics, (c) 1000 cycle-to-cycle variations of current–voltage (I–V) characteristics, and (d) and (e) cumulative probability of HRS, LRS, and rectification ratio, (f) resistive switching behavior in specific voltage regions, (g) conduction under a positive voltage bias, (h) conduction under a negative voltage bias, (i) schematic representation of the band alignment, illustrating the HOMO (Highest Occupied Molecular Orbital) and LUMO (Lowest Unoccupied Molecular Orbital) levels of the device's constituent layers26 (drawing is not to scale).
Schematic of the device configuration, along with the statistical data and mechanism analysis of the current–voltage (I–V) characteristics. (a) Device architecture of ITO/PEDOT:PSS/active layer/PMMA/Ag, (b) current–voltage (I–V) characteristics, (c) 1000 cycle-to-cycle variations of current–voltage (I–V) characteristics, and (d) and (e) cumulative probability of HRS, LRS, and rectification ratio, (f) resistive switching behavior in specific voltage regions, (g) conduction under a positive voltage bias, (h) conduction under a negative voltage bias, (i) schematic representation of the band alignment, illustrating the HOMO (Highest Occupied Molecular Orbital) and LUMO (Lowest Unoccupied Molecular Orbital) levels of the device's constituent layers26 (drawing is not to scale).
In order to ensure the reproducibility of the device, the current–voltage (I–V) characteristics were measured for up to 1000 scan cycles [Fig. 1(c)] and then cumulative probability is plotted to visualize the changes in electrical parameters like HRS, LRS, on/off ratio, and rectification ratio in Figs. 1(d) and 1(e), with respect to number of cycle. The set voltage of the device is found to be ∼0.52 V, the on/off ratio is 103, and the rectification ratio is 103 with very low variation in all electrical parameters. The power consumption of the device is ∼235 nW, the comparison table is provided to ensure that this device is a strong candidate for both data storage and neuromorphic applications (Table S1 in the supplementary material). These characteristics highlight the device's potential for low-power, high-performance memory applications and its suitability for use in advanced computational systems that mimic neural processes. To understand the conduction mechanism of resistive switching, the I–V characteristics are analyzed by replotting in various voltage regions as shown in Fig. 1(f). The I–V characteristics are fitted into distinct regions to identify the various conduction mechanisms, such as Schottky emission, Poole–Frenkel (PF) emission, and trap-assisted tunneling (TAT). For Schottky emission, the relationship is described by ln I vs V1/2, in contrast, for PF conduction, the current–voltage characteristics are expressed as ln(I/V) vs V1/2, while for TAT, the relationship is represented by ln(I/V) vs 1/V. It is evident from the figure that the plots of ln(I) vs V1/2 and ln(I/V) vs V1/2 can be accurately fitted with straight lines only within the voltage ranges of 0.04–0.37 and 0.55–1 V, respectively, while the reverse bias (−1 to 0 V) is dominated by PF emission and the Schottky emission mechanism (Fig. S2 in the supplementary material). The schematic representation of the ion movement in both forward and reverse directions is shown in Figs. 1(g) and 1(h). In both forward and reverse bias conditions, tunneling and PF emission are the primary mechanisms observed. This behavior is due to the film's polycrystalline nature, as observed from XRD results in Fig. S1 in the supplementary material. The presence of grain boundaries within the material creates trapping sites for charge carriers. These traps significantly influence the observed tunneling and PF emission effects, resulting in the dominant mechanisms observed in the measurements.
In order to understand the mechanism for the rectification, band arrangement is investigated as shown in Fig. 1(i). In the layered structure of the device comprising of ITO/PEDOT:PSS/active layer/PMMA/Ag, the alignment of the lowest unoccupied molecular orbital (LUMO) levels across the various materials plays an important role in influencing the transport of charge carriers. Notably, the LUMO levels exhibit a systematic stepwise increment from the ITO interface to the PMMA layer. This gradient in energy levels facilitates an efficient charge injection pathway under forward bias by sequentially reducing the energy barriers for charge carrier's migration toward the Ag electrode. This configuration under forward bias supports the flow of charge carriers toward the Ag electrode, significantly increasing the conductance. In contrast, under reverse bias, the LUMO level of PMMA acts as a robust barrier, severely restricting the backflow of charge carriers from Ag to the other layers. This notable inequality in barrier heights between the forward and reverse biases gives rise to a pronounced rectifying behavior.15 This energy barrier asymmetry highlights the critical influence of molecular orbital alignment on electrical performance and charge flow efficiency within layered memristive devices.
B. Electrochemical impedance characterization
In order to investigate the impedance of memristor in the HRS, the device was subjected to zero bias, the values of bias were chosen to remain below switching voltage (VDC < VSET). To ensure the device under test remained in the HRS, prolonged measurements were minimized wherever possible and lower perturbation voltage was applied. This precaution was taken because longer and higher perturbation voltage measurement durations may increase the risk of forming a conductive filament between the electrodes during EIS measurement, potentially altering the device's resistance state.
In both device configurations (ITO/PEDOT:PSS/active layer/Ag and ITO/PEDOT:PSS/active layer/PMMA/Ag), there was a noticeable decrease in the widths of the Nyquist plots moving from the HRS to the LRS [Figs. 2(a)–2(d)]. According to the literature, this reduction in resistance typically corresponds to a switching mechanism involving the entire matrix layer.27–29 The capacitance values obtained through equivalent circuit analysis remained nearly unchanged across both configurations while only the parallel resistance increased (Fig. S3, Table S2 in the supplementary material). This increase can be attributed to the introduction of PMMA, which has increased the charge transfer resistance at the top contact interface. The resulting increase in parallel resistance contributes to the lower value of current and gives a higher on/off ratio. Transitioning from the HRS to the LRS, both devices exhibited inductive behavior at low frequency, consistent with previous studies.30,31 Our analysis of this inductive behavior suggests that in the LRS of the device, when the direction of the electric perturbation changes, the ions do not instantly change their position due to inertia acting on them within the matrix of the active layer. This phenomenon gives rise to the inductive response observed in DJ perovskite-based devices.
Imaginary vs real components of the impedance (Nyquist plots) spectroscopy measured in the frequency range 1 Hz–1 MHz for HRS and LRS states. (a) and (b) Nyquist plot for device configuration of ITO/active layer/Ag, in the HRS (no bias) and LRS (applied bias of 0.9 V) state, respectively, (c) and (d) Nyquist plot for device configuration, ITO/PEDOT:PSS/active layer/PMMA/Ag in HRS and LRS (applied bias of 0.7 V) state, respectively. The values of LRS voltages have been selected on the basis of set voltage values of the respective device.
Imaginary vs real components of the impedance (Nyquist plots) spectroscopy measured in the frequency range 1 Hz–1 MHz for HRS and LRS states. (a) and (b) Nyquist plot for device configuration of ITO/active layer/Ag, in the HRS (no bias) and LRS (applied bias of 0.9 V) state, respectively, (c) and (d) Nyquist plot for device configuration, ITO/PEDOT:PSS/active layer/PMMA/Ag in HRS and LRS (applied bias of 0.7 V) state, respectively. The values of LRS voltages have been selected on the basis of set voltage values of the respective device.
C. Stability performance analysis
Perovskite is known for its instability with respect to varying humidity, temperature, and over extended periods of time. However, it is crucial to develop memristor devices that can maintain performance and stability under extreme environmental conditions.32,33 In this work, 3AMP-based low-dimensional DJ perovskite has been used to fabricate a device capable of sustaining its performance, and the results are shown in Figs. 3(a)–3(i). I–V measurements with respect to humidity levels ranging from 40% to 80%RH are shown in Fig. 3(a). These results show consistent performance, with uniform values for the set voltage, rectification ratio, on/off ratio, state up to 70%RH [Fig. 3(a)]. The degradation device observed at 80% RH can be attributed to moisture-induced ionic migration within the perovskite layer, leading to structural degradation and alteration of electronic properties. To evaluate temperature-related stability, experiments were conducted involving I–V measurements while subjecting the device to temperatures ranging from 25 to 80 °C, as illustrated in Fig. 3(b). Results revealed a nearly consistent performance of electrical parameters such as set voltage, on/off ratio, rectification ratio, up to 70 °C, affirming the device's robust stability in response to temperature fluctuations. However, above 70 °C, the device fails to maintain these characteristics due to thermal degradation of the active layer and interfacial materials. The elevated temperatures can cause increased ionic mobility and diffusion, disrupting the uniformity of the conductive filaments and leading to a breakdown in the device's switching mechanism. Consequently, this thermal stress results in a significant decline in the on/off ratio and rectification ratio, indicating a loss of the memristor behaviour. Furthermore, to assess device's reproducibility and long-term stability, I–V characterizations were conducted for 200 days. The results revealed negligible variations in the rectification ratio, set voltage, and on/off ratio, throughout the observation period, firmly establishing the device's exceptional stability over time [Fig. 3(c)]. Additionally, to validate the consistency of device performance, 100 cycle-to-cycle variations were examined for two distinct devices on the 200th day, confirming device's stability over time (Fig. S4 in the supplementary material). The device exhibited standard stable performance in both HRS and LRS, with a retention time for ∼76 000 s (∼21 h) and endurance of 103 cycles at standard conditions. Under standard conditions, the device exhibited stable performance in both HRS and LRS, with a retention time of 22 000 s and endurance of 103 cycles [Figs. 3(d) and 3(g)]. Conversely, under extreme environmental conditions of 70% RH [Figs. 3(e) and 3(h)] and 70 °C [Figs. 3(f) and 3(i)], the device exhibited a retention time of up to 103 s and endurance of 102 cycles. These results confirm that the device exhibits stable performance across diverse environmental conditions.
Stability performance of the ITO/PEDOT:PSS/active layer/PMMA/Ag device under external factors such as temperature, humidity, and prolonged durations extending to 200 days. (a) Comparison of I–V characteristics for different humidity conditions (%RH), (b) comparison of I–V characteristics for different temperature conditions, (c) comparison of I–V characteristics at different days, Retention. (d)–(f) Variations in HRS and LRS states in standard and extreme humidity and temperature conditions, Endurance. (g)–(i) Variations in HRS and LRS states in standard and extreme humidity and temperature conditions.
Stability performance of the ITO/PEDOT:PSS/active layer/PMMA/Ag device under external factors such as temperature, humidity, and prolonged durations extending to 200 days. (a) Comparison of I–V characteristics for different humidity conditions (%RH), (b) comparison of I–V characteristics for different temperature conditions, (c) comparison of I–V characteristics at different days, Retention. (d)–(f) Variations in HRS and LRS states in standard and extreme humidity and temperature conditions, Endurance. (g)–(i) Variations in HRS and LRS states in standard and extreme humidity and temperature conditions.
Memory serves as a fundamental element in the learning and decision-making processes within biological organisms. Unlike modern semiconductor memory devices, human memory is inherently temporary.34 Notably, it is important to replicate short-term memory (STM) to long-term memory (LTM). The process of converting from STM to LTM in neuromorphic systems can potentially be controlled by modulating the width of electrical pulses applied to memristor devices [Fig. S5(a) in the supplementary material].35,36
In the realm of synaptic simulation, memristor can adjust their resistance states in response to the duration and intensity of the electrical stimuli they receive, analogous to how biological synapses strengthen or weaken. Increasing the pulse width can be analogous to prolonged synaptic activity in biological neurons, which is crucial for long-term potentiation (LTP), a mechanism believed to motivate the formation of long-term memories.37,38 This approach, where wider pulses induce a more pronounced resistive change in the memristor, mimics the natural synaptic reinforcement seen during repetitive neuronal firing, thereby enhancing the durability and strength of the synaptic connections in artificial neural network (ANN). In the context of memory devices, as shown in Figs. S5(a) and S5(b) in the supplementary material, transitioning from a lower pulse width (10 ms) to a higher pulse width (100 ms) highlights the differentiation between STM and LTM. When a lower pulse width (10 ms) is applied, the device exhibits a more significant drop in current, indicating a transient change that is characteristic of STM, where information is temporarily stored and quickly forgotten. Conversely, a higher pulse width (100 ms) results in a less significant drop in current, signifying a more stable and lasting alteration in the device state, demonstrative of LTM, where information is retained for extended time. This transition from STM to LTM underscores the ability to regulate the memory retention of the device by controlling the pulse width, thus enabling the emulation of dynamic human memory processes in neuromorphic computing applications. Spike time-dependent plasticity (STDP) based on the Hebbian learning rule was investigated to demonstrate the potential of these devices for neuromorphic applications. STDP is an advanced learning method where synaptic changes depend on the timing of neuron pulses.39–43 These learning rules depend on the difference between the spikes occurring at the pre- and post-synaptic neurons, (Δt = tpre − tpos). When Δt > 0, it leads to LTP, while Δt < 0 leads to LTD.41,42 The STDP pattern (asymmetric Hebbian and asymmetric anti-Hebbian) is recorded for low dimensional DJ perovskite as shown in Figs. 4(a) and 4(b) using a pair of pulses (+0.55 V, 90 ms and −0.3 V, 90 ms) as pre- and post-synaptic spike, respectively. The experimental data were fitted using the function, , where A1, A2, and W0 represent constant terms. Biological synaptic transmission typically operates at speeds around 0.1–50 ms, reflecting the rapid transmission of signals across synapses in the nervous system. In this study, low dimensional DJ-based memristor devices exhibit a comparable communication time of approximately 31 ms, highlighting their potential for neuromorphic computing applications.
Synaptic characterization of the ITO/PEDOT:PSS/active layer/PMMA/Ag device. Spike time dependent plasticity (STDP) (a) and (b) asymmetric Hebbian and asymmetric anti-Hebbian, (c) spike-number-dependent plasticity (SNDP), (d) spike duration dependent plasticity (SDDP), (e) schematic representation of the three-layer neural network for pattern recognition, (f) pattern recognition accuracy of the ideal synaptic device (98%) and memristor device (89%) after ten epochs.
Synaptic characterization of the ITO/PEDOT:PSS/active layer/PMMA/Ag device. Spike time dependent plasticity (STDP) (a) and (b) asymmetric Hebbian and asymmetric anti-Hebbian, (c) spike-number-dependent plasticity (SNDP), (d) spike duration dependent plasticity (SDDP), (e) schematic representation of the three-layer neural network for pattern recognition, (f) pattern recognition accuracy of the ideal synaptic device (98%) and memristor device (89%) after ten epochs.
Synaptic current with the number of spikes is indicative of the memristor's neuromorphic properties, mimicking the way biological synapses strengthen with repeated stimulation. This behavior is crucial for neuromorphic computing applications, where devices are designed to emulate the adaptive and learning functions of neural networks. As shown in Fig. 4(c), as the number of spikes increases, the postsynaptic current also increases, indicating the adaptive learning of the device, which is generally known as spike-number-dependent plasticity (SNDP). This makes it a promising candidate for future artificial neural network implementations.44 As the pulse width increases, the current increases as shown in Fig. 4(d), which is known as spike duration dependent plasticity (SDDP). Additionally, spike-number-dependent plasticity was investigated by varying the pulse width. As shown in Fig. S5(c) in the supplementary material, increasing the pulse width from 0.5 to 100 ms results in a corresponding increase in current. This suggests that the formation of conductive filaments becomes stronger with wider pulses, indicating enhanced synaptic plasticity and more robust neuromorphic behavior of the device.43
Furthermore, in order to increase the effectiveness of device as an artificial synapse, a three-layer neural network multilayer perceptron simulation was carried out. As shown in Fig. 4(e), an input layer with 784 neurons, one hidden layer with 128 neurons, and an output layer with 1 neuron make up this three-layer neural network. Here, the input layer provides a data set of handwritten MNIST images with size of 28 × 28 pixels, ranging from 0 to 9.43 The hidden layer makes use of a simplified input feature based on the synaptic weight matrix. A total of 10 000 MNIST test set images and 50 000 MNIST training data set images were used for testing and training throughout each epoch. In this artificial neural network (ANN) model-based analysis, we used potentiation and depression data to simulate image recognition [Fig. S5(d) in the supplementary material]. For efficient ANN simulations, a neuromorphic device should exhibit high linearity and symmetry in potentiation and depression to ensure accurate weight updates, along with consistent performance. The hyper-parameters utilized during this analysis included the activation function (ReLU) and the optimizer (Adam). These choices were made to enhance the model's performance and accuracy in recognizing images by effectively managing the learning process and ensuring optimal parameter updates. The device demonstrated an impressive recognition accuracy of ∼95% after ten epochs of training [Fig. 4(f)]. This indicates the device is a highly promising candidate for artificial synapses, exhibiting impressive potential in neuromorphic computing applications. Synaptic current with the number of spikes is indicative of the memristor's neuromorphic properties, mimicking the way biological synapses strengthen with repeated stimulation. This behavior is crucial for neuromorphic computing applications, where devices are designed to emulate the adaptive and learning functions of neural networks.
In the complex dynamics of the human brain, neural oscillations play a fundamental role in coordinating various cognitive functions. Among these oscillatory patterns, delta (δ), alpha (α), and gamma (γ) indicates different frequency bands associated with different states of consciousness and cognitive processing.45–47 Delta waves with frequencies below 4 Hz are predominant during meditation and deep sleep. Alpha oscillations, occurring at frequencies between 8 and 13 Hz, are prominent during states of relaxation and mental activity, but also play a role in inhibiting irrelevant or distracting sensory inputs to enhance focus. Conversely, gamma oscillations, typically ranging from 25 to 100 Hz, are implicated in higher cognitive functions such as memory formation, attention, and sensory perception.48,49 Remarkably, recent advancements in neuro-engineering have enabled the replication of these neural oscillations in artificial neural networks, mirroring the brain's ability to generate and modulate oscillatory patterns for various cognitive tasks and states of consciousness.
This replication holds promise for the development of innovative technologies, such as brain–computer interfaces and neuromorphic computing systems, aimed at enhancing human–machine interactions and advancing artificial intelligence. Our work successfully emulated the complex dynamics of delta, alpha, and gamma rhythms in our devices, marking a pivotal milestone in artificial intelligence development. Our work examined the behavior of device at different frequency modes, particularly focusing on gamma, alpha, and delta modes [schematic shown in Fig. 5(a)]. The oscillatory patterns we applied are in the form of pulses, similar to activation potentials in the brain. Each pulse is applied with a constant amplitude across three different frequencies. Specifically, we applied 10 pulses at each frequency, systematically recording the current response at the peak value, which occurs at 1 V for each pulse. Our experimental observations, as shown in Fig. 5(b), reveals a noteworthy phenomenon in the gamma mode, characterized by higher frequencies, in which strong filament formation is formed and because of that higher current is observed compared to delta and alpha modes of frequencies, which is similar to a biological brain in which robust and strongly interconnected neural network is observed in the gamma mode (Fig. S6 in the supplementary material). This observation underscores the resemblance between device dynamics and the functional architecture of neural networks in the brain. Such insights help the development of advanced neuromorphic technologies with enhanced computational capabilities.
Spike Rate Dependent Plasticity (SRDP) represents the relationship between synaptic weight changes with varying spike rates. (a) Schematic representation of the oscillatory pattern in the human brain, (b) spike rate dependent plasticity (SRDP) for different phases of the brain, i.e., delta phase (meditation state), alpha phase (relaxation state), and gamma phase (critical thinking state).
Spike Rate Dependent Plasticity (SRDP) represents the relationship between synaptic weight changes with varying spike rates. (a) Schematic representation of the oscillatory pattern in the human brain, (b) spike rate dependent plasticity (SRDP) for different phases of the brain, i.e., delta phase (meditation state), alpha phase (relaxation state), and gamma phase (critical thinking state).
III. CONCLUSIONS
In conclusion, this study demonstrates the successful development of a self-rectifying memory cell using low-dimensional Dion–Jacobson perovskite-based memristor incorporating a 3AMP spacer cation. Our investigation aimed to evaluate the long-term stability of these devices by monitoring key parameters, including the on/off ratio, set voltage, and rectification ratio, over a period of 200 days. To assess the stability of the device under varying temperature and humidity conditions, with humidity ranging from 40% to 80%RH and temperatures ranging from 25 to 80 °C, comprehensive assessments were conducted to evaluate device performance under real-world operating scenarios. Furthermore, our device also demonstrates neuromorphic characteristics such as transition from short-term memory to long-term memory, spike-timing-dependent plasticity (STDP), image recognition, and replication of the three phases of brain activity.
IV. EXPERIMENTAL DETAILS
A. Materials
Methyl ammonium iodide (>99.5%), lead iodide (>99.5%) 3-(aminomethyl)piperidine, poly(methyl methacrylate),N,N-dimethylformamide, ITO-coated glass substrate, and dimethyl sulfoxide were purchased from Sigma-Aldrich and used as received.
B. Structure and solvent preparation
The memristor devices with a planar structure ITO/active layer/PMMA/Ag were fabricated for data storage and synaptic learning applications [Fig. 1(a)]. Solvents for low-dimensional perovskite were prepared using a molar ratio of MAI, PbI2, and 3AMP in the ratio of 2:3:2 in DMF and DMSO. This precursor solution was heated and stirred on a hot plate at 75 °C for 2 h until the solution completely dissolved. The ITO-coated glass substrates were cleaned through standard procedure using acetone and IPA followed by ultra-sonication in DI water for 20 min. Thereafter, substrates were subjected to ozonization for 15 min. PEDOT:PSS was spin coated at 3000 rpm for 60 s followed by annealing for 30 min at 90 °C. The DJ hybrid perovskite thin film was prepared by spin-coating at 3500 rpm for 60 s followed by annealing at 40 min at 80 °C. Furthermore, PMMA was spin coated at 3000 rpm for 30 s. Finally, Ag top electrode was deposited by screen printing method with a diameter of ≈1 mm.
C. Characterizations of thin film and devices
Laboratory of Advance Synthesis and Characterization (LASC) probe station and a source measurement unit (Keithley 2604B) were used to measure the I–V characteristics of fabricated memristor devices. A positive bias is applied at the top of the electrode (Ag), while the BE (ITO) was grounded during the measurements of all devices. All the electrical characterizations were done under the ambient environment conditions. SEM was conducted to investigate the morphology of the thin film by ZEISS Ultra 55. For investigation the structure of the perovskite film, XRD was done by Rigaku Miniflex 600C.
SUPPLEMENTARY MATERIAL
See the supplementary material consists of x-ray diffraction and field emission scanning electron images, Equivalent circuit diagram for impedance analysis with parametric tables, stability data for 200 days for different devices, and schematic of filament formation for the delta phase, alpha phase, and gamma phase of the brain.
ACKNOWLEDGMENTS
A.S. and M.K. gratefully acknowledge the fabrication support from Science and Engineering Research Board (SERB) core Research Grant No. CRG/2020/000869. A.S. would also like to gratefully acknowledge GUJCOST (Grant No. GUJCOST/STI/2021-22/3873) from the Government of Gujarat, India, to support electrical characterizations.
AUTHOR DECLARATIONS
Conflict of Interest
The authors have no conflicts to disclose.
Author Contributions
Manish Khemnani: Writing – original draft (equal). Muskan Jain: Formal analysis (equal). Denish Hirpara: Formal analysis (equal). Manoj Kumar: Writing – review & editing (equal). Brijesh Tripathi: Supervision (equal); Writing – original draft (equal). Ankur Solanki: Funding acquisition (lead); Supervision (equal); Validation (equal).
DATA AVAILABILITY
The data that support the findings of this study are available within the article and its supplementary material.