Metal free all oxide SnO_x/HfO_x bilayer transristor synapse for neuromorphic computing

Modern computing systems, grounded in the von Neumann architecture proposed in 1945, primarily utilize conventional CMOS transistors. While this architecture has been foundational for computing, it presents several challenges, particularly in processing unstructured big data efficiently. Bottleneck of von Neumann architecture arises due to the sequential data transfer between the CPU and memory, causing a data transfer rate limitation.¹ Recent development of generative artificial intelligence (Gen-AI), deep learning, Internet of Things (IoT), demands that data processing in these fields should consume low energy, operate at high speeds, and achieve increased performance computing.² Scientists and researchers developed neuromorphic architecture inspired by the working principle of the human brain, which contains billions of neurons, has a large memory capacity, and processes vast amounts of information with high speeds and low energy consumption (∼20 W).³ This type of architecture consists of artificial neural network (ANN)-based memristors or artificial synapses that can emulate biological synapses. Neuromorphic computing is thus considered a suitable solution to overcome the von Neumann bottleneck. It can solve complex tasks such as speech recognition, language translation, face detection, and health monitoring.^4–7 

Making artificial synapses using conventional CMOS transistors that can mimic the behavior of the brain is a challenging task. Going through the hypothetical concept of memristor, as a fourth fundamental element, proposed by Leon Chua in 1971,⁸ the researchers in the HP laboratory physically realized two-terminal memristor devices based on TiO_x in 2008.⁹ It is a two-terminal passive electronic device that retains a memory of the amount of charge that has previously flowed through it, allowing it to store and process information. The structure of a memristor typically consists of two metal electrodes separated by a thin insulating layer, often made of a high bandgap semiconductor or metal oxide. At the beginning of the twenty first century, memristor drew huge attention toward its numerous applications such as artificial synapses,¹⁰ analysis of big data,¹¹ non-volatile memories,¹² neuromorphic computing,¹³ signal processing,¹⁴ photonic computing,¹⁵ analog/digital circuits,¹⁶ flexible electronic devices,¹⁷ biological applications,¹⁸ etc.

It is observed that artificial synapses based on memristors are successfully used to mimic the biological synaptic functions of the human brain.¹⁹ The materials used for synaptic devices must exhibit several key characteristics to function effectively in neuromorphic systems. First, they should possess high non-volatility, which means that they can retain memory states even after power is off, similar to biological synapses that maintain long-term potentiation or depression.²⁰ The materials also exhibit tunable analog responses to external stimuli, such as voltage or current, critical for synaptic plasticity—the ability to strengthen or weaken connections based on activity. Furthermore, fast switching times are essential to mimic the rapid signaling served in biological synapses.²¹ For synaptic devices to operate efficiently, they also need to demonstrate low power consumption, ensuring that energy usage does not become a bottleneck in large-scale networks. Overall, the materials should be compatible with scalable manufacturing techniques, ensuring that synaptic devices can be produced cost-effectively for large scale use in neuromorphic computing systems.²² 

There are many efforts for fast switching with energy efficient binary oxide-based memristors made to mimic the biological synapses.^23–25 Ismail et al. presented a Pt/TiN/SnO_x/Pt memory device as a potential breakthrough in neuromorphic computing.²⁶ Pyo et al. analyzed the threshold switching and bipolar resistive switching behaviors, along with the non-volatile memory properties, of an Ag/SnO_x/TiN memory device.²⁷ Wang et al. proposed a sandwiched structure of HfO_x/AlO_y showing analog switching performance.²⁸ Jiang et al. demonstrated a novel HfO_x-based multilayer structure to improve the linearity and showing the potential for applying these devices in synaptic mimicry and neuromorphic computing.²⁹ In our previous work, we showed how memristor synapses can be used not only for neuromorphic computing but also as nociceptors.³⁰ 

Development of flexible and transparent synaptic memristors is key to advancing next-generation electronics, particularly in fields, such as wearable technology, neuromorphic computing, and smart materials. Lu et al. explored a low power memristor on van der Waals SnS [tin(II) sulfide] whose power consumption is as low as ∼100 fJ per switch.³¹ Tang et al. demonstrated a halide-based flexible threshold switching memristor neuron that exhibit an ultrahigh switching speed of less than 35 ns.³² Memristors based on flexible substrates have been widely investigated over the last few years with various materials such as organic polymers, inorganic semiconductors,³³ amorphous silicon, two-dimensional (2D) materials,³⁴ metal oxides,²⁴ graphene,³⁵ and perovskites³⁶ as the switching layer. A literature study shows that the bi-layer binary oxide-based memristors are more effective in switching performance than monolayer oxide memristors.³⁷ Stacking of different oxide layers to engineer the structure, such as HfO_x/HfO₂,³⁸ Al₂O₃/TiO₂,³⁹ HfO_x/TiO₂, and Al₂O₃/Nb₂O₅,⁴⁰ etc., have been explored by different researchers to improve the switching characteristics of memristors.

SnO_x and HfO_x bi-layer metal oxide structure is a promising structure for the development of synaptic devices. This material combination is chosen for its potential to harness the complementary properties of both oxides. Tin oxide (SnO_x) is well known for its high conductivity and tunable resistive switching behavior, making it suitable for the rapid and reversible changes required in synaptic plasticity.⁴¹ On the other hand, hafnium oxide (HfO_x) is a high-k dielectric material with excellent non-volatile memory characteristics and stability, which is crucial for ensuring long-term retention of synaptic states.⁴² The bilayer configuration of SnO_x and HfO_x offers a synergistic effect.^43,44 This combination allows for development of synaptic devices that exhibit the required non-volatility, tunability, and fast switching, addressing the core challenges in neuromorphic computing.⁴³ Moreover, both materials are compatible with conventional semiconductor fabrication techniques, making them scalable for large-scale integration in neuromorphic systems.⁴⁵ Although some efforts were made to improve the switching performance in bilayer oxide-based memristor synapses but multilevel characteristics with high endurance in SnO_x/HfO_x memristors are awaited.

In this work, we report the development and characterization of all oxide-based transristor (transparent memristor) devices fabricated by RF sputtering. The transristor devices consist of a bilayer of SnO_x/HfO_x thin films with different thicknesses sandwiched between ITO electrodes. The memristive and synaptic properties of the device are also investigated.

Thin films (SnO_x and HfO_x) deposited on indium tin oxide (ITO) coated polyethylene naphthalate (PEN) substrate by RF magnetron sputtering. All depositions are carried out at room temperature. The ITO coated PEN substrate is first ultrasonically cleaned in acetone, followed by 2-propanal and de-ionized water. A thin layer of HfO_x is deposited on a 50 nm ITO/PEN substrate by RF sputtering, followed by a comparatively thick SnO_x thin film on it. A 180 nm thick ITO round shape with a diameter of 100 μm is deposited on SnO_x as a top electrode through a metal shadow mask to fabricate ITO/SnO_x/HfO_x/ITO/PEN memristive metal-insulator-metal (MIM) device. The same procedure is followed to prepare different samples by varying the thickness of SnO_x and HfO_x. The final transristor devices consist of a vertical thin film stack of ITO (180 nm)/SnO_x (y nm)/HfO_x (z nm)/ITO (50 nm)/PEN, where y and z, respectively, denote the thickness of SnO_x (10, 20, or 35 nm) and HfO_x (6, 10, or 15 nm). Fabricated devices are named as ISHI10/6, ISHI20/6, ISHI35/6, ISHI35/10, and ISHI35/15. First, we have optimized the thickness of SnO_x and the HfO_x. The numbers in the names ISHIy/z represent the thickness of the reactive sputtered SnO_x and HfO_x in nm.

The electrical I–V characteristics are measured at room temperature using an Agilent B1500A semiconductor parameter analyzer and B1530A wave-form generator/fast measurement. For all measurements, voltage bias (positive and negative) is applied to the ITO top electrode, while the bottom electrode (BE) is grounded. The optical transmittance of the transristor is examined by using a UV–vis spectrometer (Hitachi U-3010). The composition of the switching regions is investigated using x-ray photoelectron spectroscopy (XPS) (ULVAC-PHI PHI 5000 Versaprobe II). The sputtering during XPS were performed in a 180° hemispherical analyzer equipped with 128 channel detector using 5 kV Ar ion gun in a base pressure of 2 × 10⁻⁷ Pa.

We schematically depicted the biological synapse and the similarity between a biological synapse and an artificial one, constructed from an all oxide transparent memristor (or transristor) on a flexible platform, utilizing the SnO_x/HfO_x bilayer structure in Fig. 1. The communication between the two synapses and their ionic movements is also represented.

XPS analysis is performed to verify the presence of oxygen vacancies in the SnO_x- and HfO_x-based transristor device, as shown in Fig. 2. The measurement is performed at different depths of the optimized device. In the memristor devices, the oxygen vacancies, which is responsible for the synaptic properties, are calculated by analyzing O1 s spectra.^46–48 The oxygen vacancies lying on the surface and at the interfaces of the two films play an important role in the current conduction property. The O1 s spectra obtained from the XPS are simulated using the Gaussian function and deconvoluted. The spectra, as shown in Figs. 2(a)–2(c), give two peaks—one for O_I (lattice oxygen) centered at a lower binding energy of 530.3–530.4 eV and a second for O_II (oxygen vacancies) with the higher binding energy of 531.1–531.4 eV. The slight variation in the binding energy values is due to the change in the film depth. The ratio of O_II/O_total is calculated to find out the concentration of oxygen vacancies in the thin film.⁴⁹ O_total is given by the sum of peak areas of O_I and O_II. The calculated O_II/O_total ratio at the interface of ITO/SnO_x, SnO_x/HfO_x, and HfO_x/ITO is around 0.291, 0.292, and 0.297, respectively. Figure 2(d) shows the trends of the O_II/O_total ratio corresponding to the etching time of 3 s, 11 s, 17 s, 23 s, 29 s, and 35 s. It is observed from the trend that oxygen vacancy concentration is higher at the interfaces of ITO/SnO_x, SnO_x/HfO_x, and HfO_x/ITO as compared to adjacent SnO_x and HfO_x layers. Also, it is inferred that oxygen vacancy concentration in HfO_x is higher than that in the SnO_x layer.

Figure 3(a) shows the TEM measurements carried out to analyze the microstructure of SnO_x and HfO_x layers. TEM allows for the observation of nanoscale features, such as the formation and evolution of conductive filaments, which are often responsible for the memristor's switching behavior. Energy-dispersive x-ray spectroscopy (EDX) mapping, as shown in Figs. 3(b)–3(e), is used for analyzing the elemental composition of each layer within the cross-sectional TEM image of the optimized memristor. The analysis highlights the elemental distribution of key materials—oxygen (O), indium (In), hafnium (Hf), and tin (Sn)—throughout the device. It confirms that the fabrication process has successfully produced the intended material composition and structure. This result corroborates with the XPS analysis.

A corresponding physical model for the optimized device is also presented to show the gradual switching mechanism in the device. The physical and chemical properties of any oxide materials depend on the presence of oxygen vacancies.^50,51 These vacancies induce resistive switching phenomena by the formation of conductive filament (CF) when an electric potential is applied at TE.^26,47,52 It is well established that the filamentary switching is dominant on the device where forming is essential.^53,54 The CF is responsible for the change in resistance in the material. The movement of oxygen vacancies depends on the applied voltage and the device's material properties. When a voltage is applied in a certain direction, it causes oxygen vacancy movement that creates a conductive path, leading to a decrease in resistance (LTP). A voltage of opposite polarity causes the conductive path to break or weaken, increasing the resistance (LTD). Tracking is observed in the change of conductance using I–V curves or time-dependent measurements during pulsed stimulation (e.g., voltage pulses) to evaluate how the resistance changes in response to LTP or LTD-inducing stimuli.

Figure 3(f) shows the pristine state of the device where no bias is given. Initially, in this state, more oxygen vacancies are found in the HfO_x layer than in the SnO_x layer as confirmed by XPS analysis. Also, at the same time, the concentration of oxygen vacancies in the interfaces of SnO_x/HfO_x and HfO_x/ITO is higher than that in the HfO_x layer. Now, on the application of the positive bias to TE [Fig. 3(g)], oxygen vacancies, which are randomly distributed in the SnO_x and HfO_x layers, form a CF between the TE and BE. It results in switching the device from the initial state to LRS (on state) with oxygen vacancies in the interfaces of ITO/SnO_x and SnO_x/HfO_x moving toward the HfO_x/ITO interface. During negative bias at the TE, oxygen ions are re-ionized to oxygen atoms and fill the vacancies to rupture the filament, and the device switches off, i.e., returns to a high resistance state [Fig. 3(h)]. The oxygen atom signifies the neutral oxygen present within the oxide layers. It is inferred from the mechanism that the bilayer device SnO_x/HfO_x has the ability to show gradual switching modulation and can be used in artificial synapses.

The current–voltage (I–V) characteristics (semi-log scale) of the devices having different SnO_x and HfO_x thicknesses are shown in Figs. 4(a)–4(e). The voltage sweeps and compliance current (CC) are optimized for the best switching performance. All the transristors, i.e., ISHI10/6, ISHI20/6, ISHI35/6, ISHI35/15, and ISHI35/10 reveal the bipolar resistive switching (BRS) characteristics. During the set process, the device switched from a high resistance state (HRS) to a low resistance state (LRS) due to the formation of conductive filament (CF) using oxygen vacancies (V_o), while the reset process from LRS to HRS on the rupture of CF by recombining V_o with the oxygen ions that migrate from the oxygen reservoir to the interface of ITO/SnO_x. It has been observed from the characteristics that as the thickness of SnO_x is increased from 10 to 35 nm, both set/reset voltages are trying to attain a minimum value. For ISHI10/6 [Fig. 4(a)] and ISHI20/6 [Fig. 4(b)] devices, a significant current fluctuation is observed during the reset state. This might be due to the generation of new oxygen vacancies in the gap region of SnO_x/HfO_x at that moment.⁵⁵ 

Furthermore, at a SnO_x thickness of 35 nm, a gradual increase and decrease of current occurs during both set and reset states, which is the prerequisite for a good memristive synaptic device,⁵⁶ as it allows for precise control over the resistive state, making it suitable for applications in neuromorphic computing. Such gradual transitions are critical for ensuring proper synaptic functions, such as potentiation and depression, which enable the device to mimic biological learning and memory processes. In this case, the most significant noticeable change in the device ISHI35/6 [Fig. 4(c)] is the lower CC required for the SET process. As the thickness of SnO_x increases from 10 to 35 nm, the required CC to obtain good switching properties is decreased to 100, indicating a reduction in power consumption. This reduction in CC can be interpreted by the fact that as the dielectric oxide thickness increases, there is an increase in resistance in the switching layer as less number of oxygen vacancies are found in the conductive filament.⁵⁷ 

After optimizing the SnO_x thickness at 35 nm, we vary the HfO_x thickness for 15 and 10 nm, and the characteristics of ISHI35/15 [Fig. 4(d)] and ISHI35/10 [Fig. 4(e)] are observed. A fluctuation in the current during set and reset states is found in ISHI35/15, while an abrupt set occurs in ISHI35/10. The different set/reset voltages obtained and the CC of the devices are summarized in Table I, and Fig. 4(f) shows the trends of set and reset voltages of the different devices. The forming potential for the three devices, ISHI35/6, ISHI35/10, and ISHI35/15, are shown in Fig. S1 in the supplementary material. We conclude that the diverse electrical characteristics obtained in the different devices are based not only on the difference of oxygen vacancies in the oxide layer but also on the asymmetry in the tunnel current density originating from the different barrier heights of SnO_x and HfO_x. Among them, ISHI35/6 shows better bipolar switching properties than the others.

The endurance of our fabricated devices ISHI10/6, ISHI20/6, and ISHI35/6 is investigated by giving a bipolar voltage sweep at 0.1 V readout voltage as shown in Figs. 5(a)–5(c). The devices having CC less than 1 mA are measured for endurance characteristics. From Figs. 5(a) and 5(b), it is seen that for the devices ISHI10/6 and ISHI20/6, degradation between LRS and HRS occurs after 110 cycles and 160 cycles, respectively. The two devices show the resistance decrease at HRS after each cycle of the writing and erasing process, so they do not retain their stability. The degradation might be due to the formation of additional oxygen vacancies when the device undergoes RESET states.⁵⁸ The endurance characteristics of the device ISHI35/6, as shown in Fig. 5(c), remain stable and have a comparable ratio without any recognizable degradation between LRS and HRS during set/reset operation over 10⁴ cycles. The data retention capability of ISHI35/6 lasts for 10⁴ s, as shown in Fig. 5(d). So, it is concluded that the device ISHI35/6 is highly stable and optimized. Fig. S2 in the supplementary material shows the I–V and endurance characteristics of a monolayer HfO_x and Fig. S3 in the supplementary material shows the I–V characteristics of the transristor with thickness of 40 nm SnO_x/6 nm HfO_x.

The multi-level resistive switching characteristics of the device are mainly investigated to realize their data storage capability and for implementation in the different voltage scales.⁵⁹ These characteristics can be achieved not only by adjusting the CC but also by modulating the reset voltages.⁶⁰ We have explored the multilevel characteristics experimentally in our optimized device by varying both the CC and reset voltages. Figure 6(a) shows the multilevel switching characteristics for the optimized device ISHI35/6. It is seen that as the compliance current increases, the set voltage exponentially increases, or in other words, a steady conductance state is realized.

Figure 6(b) shows the resistive switching of seven-level high resistance states that are achieved by applying several reset/stop voltages, i.e., from −1.0 to −1.6 V in steps of 0.1 V, and this RESET process is found to be gradual because of negative feedback. Figure 6(c) shows the gradual increase in set voltage with an increase in compliance current from 10 to 100 μA, and Fig. 6(d) shows the gradual variation of reset current at the voltages from −1.0 to −1.6 V. The inset in Fig. 6(b) depicts that the device has seven analog reset states with a CC of 100 μA and V_reset gradually decreases from −1 to −1.6 V with steps of 0.1 V after one set process with V_set of 1.3 V. These results conclude that the storage capacity is increased with the optimized set/reset voltages in the optimized device. Thus, the device has the potential to store multilevel information.⁶¹ 

To study the synaptic weight modulation of the memristors, three different trains of electrical pulse schemes with gradually varying amplitudes and pulse width of 10 μs are applied to the three samples. Since we have fabricated three different devices with variable thickness, three different training pulses are used to achieve a better synaptic modulation. Figures 7(a)–7(c) depict the response of the fabricated device in the light of potentiation (increasing conductance) and depression (decreasing conductance) after applying the optimized pulse schemes. For ISHI35/15 [Fig. 7(d)], an optimized pulse height of +1.9 V amplitude for potentiation and −1.9 V amplitude for depression (pulse width, 10 μs) is applied for the synaptic measurement. For ISHI35/10 [Fig. 7(e)], a pulse of +1.75 V amplitude for potentiation and −1.5 V amplitude for depression (pulse width, 10 μs) is applied. Similarly, for ISHI35/6 [Fig. 7(f)], a pulse of +1.6 V amplitude for potentiation and −1.46 V amplitude for depression (pulse width, 10 μs) is applied. For the read event, an equal pulse width of 1 ms and 0.1 V amplitude are used for all the devices. The pulse schemes applied to different devices showed a gradual increase (potentiation) and decrease (depression) in the conductance value.

The long-term potentiation (LTP) and depression (LTD) characteristics of ISHI35/15, ISHI35/10, and ISHI35/6 transristors are emulated as shown in Figs. 8(a)–8(c) by giving a continuous positive and negative pulses followed by read pulses 0.1 V/1 ms. For ISHI35/15, 100 consecutive 1.9 V/10 μs pulses are applied for potentiation, and 100 negative pulses of 1.9 V/10 μs are applied for depression. The pulse train is continued for 50 cycles. However, the last and first five cycles are shown in Fig. 8(a). The initial five cycles exhibit a gradual rise in conductance during potentiation, followed by a notable decline during depression. However, by the final five cycles, the conductance experiences substantial deterioration, suggesting poor stability and a diminished capacity to retain potentiated states over time. Similarly, for the ISHI35/10 device, 200 cycles are observed, as shown in Fig. 8(b). Each cycle consists of 500 pulses of potentiation 1.75 V/10 μs and depression −1.5 V/10 μs. In this case for the final five cycles, the conductance is significantly lower than in the earlier cycles, indicating some performance degradation, yet still showing improved stability compared to ISHI35/15.

For the ISHI35/6 device, 350 cycles are observed, as shown in Fig. 8(c), during potentiation 1.6 V/10 μs and depression −1.46 V/10 μs. The highest conductance ratio of 1 (ISHI35/6) is observed, whereas the other two devices show a conductance ratio of 0.08 (ISHI35/15 and ISHI35/10). It is also observed that the ISHI35/6 device remains quite stable up to 350 cycles with a large conductance ratio, whereas the other two devices ISHI35/15 and ISHI35/10, experience up to 50 and 200 cycles, respectively. Therefore, we can say that the device ISHI35/6 is optimized one owing to improved memory function and uniform conductance modulation. The comparison of non-linearity values and LTP/LTD cycles of the three devices is shown in Fig. 9.

Now, to measure the performance of HNN, an input pattern consisting of three characters (C, G, U) of size 10 × 10 pixels is chosen. At initial, i.e., at 0 epoch, noisy images with very poor recognition rate are observed in all the devices. However, adding weights/synapses, the pattern recognition rate improves in differentiating the pixels. Figure 10(a) shows the pattern recognition of the ISHI35/15 device after 0, 10, and 17 epochs. This device exhibits 100% recognition accuracy at 17 epochs. Figure 10(b) shows the pattern recognition of the ISHI35/10 device after 0, 10, and 15 epochs. This device exhibits 100% accuracy at 15 epochs. Figure 10(c) shows the pattern recognition of the ISHI35/6 device after 0, 10, and 14 epochs. This device exhibits an accuracy of 100% at just after 14 epochs, showing a significant improvement in the recognition of images as compared to the other two devices. So, based on the simulation results, the optimized device is found to be a good candidate for neuromorphic applications. The aforementioned characteristics have been compared with recent developments in different memristor synapses from various researchers mentioned in Table II.

We concisely demonstrated the characterization of a transristor device on a flexible substrate with the ITO/SnO_x/HfO_x/ITO/PEN structure. An excellent bipolar resistive switching mechanism is exhibited in the active layer of the optimized device ISHI35/6 with a minimum compliance current of 100 μA and lower V_set/V_reset of 1.3 V/−1.6 V. A high endurance stability up to 10 000 cycles is achieved. The investigation on multilevel characteristics showed that the optimized device has the potential for storing multilevel information. It has a good nonlinearity value of 1.53 (α_p)/1.46 (α_d). Also, the LTP/LTD lasts up to 350 cycles without any degradation. A good pattern recognition accuracy of 100% at 14 epochs is obtained. The characteristics presented in the optimized device justified that it has the potential to be used as a highly flexible material for making artificial synapses. SnO_x/HfO_x memristors hold great potential for several applications, particularly in neuromorphic computing, memory systems, and flexible electronics. These memristors can enable energy-efficient artificial intelligence (AI) computations that simulate brain-like processing. With their ability to retain patterns through resistive switching, SnO_x/HfO_x memristors can be used in image recognition, speech recognition, and sensor data analysis, reducing the need for external storage and computation. The work extends the understanding of flexible electronics by demonstrating the potential of memristive devices to perform reliable switching on flexible substrates.

See the supplementary material for the following figures: (i) Fig. S1 shows the formation for (a) ISHI35/6, Vforming = 2.3 V (b) ISHI35/10, Vforming = 4.6 V (c) ISHI35/15, Vforming = 5.7 V, (ii) Fig. S2: (a) I–V characteristics of single layer HfOx with a set voltage of 1 V and a reset voltage of −3 V, (b) endurance characteristics of ITO/10HfOx/ITO, and (iii) Fig. S3: I–V characteristics of the transristor with a thickness of 40 nm SnOx and 6 nm HfOx.

This work was supported by the Department of Science and Technology (DST), Science and Engineering Research Board (SERB), Government of India, under core Project Grant No. CRG/2023/001265. This work was also supported in part by the Department of Atomic Energy, Board of Research in Nuclear Sciences, Government of India (Research Project No. 202312BRE03RP07962).

The authors have no conflicts to disclose.

A.P. and D.P. contributed equally to this work.

Asutosh Patnaik: Formal analysis (equal); Software (equal); Visualization (equal); Writing – original draft (equal). Debashis Panda: Conceptualization (equal); Data curation (equal); Formal analysis (equal); Funding acquisition (equal); Investigation (equal); Methodology (equal); Project administration (equal); Resources (equal); Supervision (equal); Validation (equal); Visualization (equal); Writing – review & editing (equal). Ping-Xing Chen: Conceptualization (equal); Data curation (equal); Investigation (equal); Methodology (equal); Visualization (equal). Narayan Sahoo: Supervision (equal); Writing – review & editing (equal). Tseung-Yuen Tseng: Funding acquisition (equal); Project administration (equal); Resources (equal); Supervision (equal); Writing – review & editing (equal).

The datasets generated and/or analyzed during this study are not publicly available due to confidentiality but are available from the corresponding author upon reasonable request.