Structural changes in Ge_1−xSn_x and Si_1−x−yGe_ySn_x thin films on SOI substrates treated by pulse laser annealing

Currently, the industry’s main production lines of integrated circuits (ICs) are predominantly based on group-IV materials such as silicon (Si), germanium (Ge), Si_1−xGe_x, or silicon carbide (SiC). Two emerging newcomers in this class are tin (Sn) containing Ge_1−xSn_x and Si_1−x−yGe_ySn_x alloys. Adding Sn into Ge or Si_1−xGe_x lattice (i) modifies the band structure of the alloy and allows a transition from an indirect bandgap semiconductor to a direct bandgap semiconductor.^1–3 Such a band structure modification can be used to fabricate optoelectronic devices like light emitting diodes, lasers, and detectors.^2,4–6 Furthermore, these alloys showed the potential of superior mobilities of up to 6000 cm² V⁻¹s⁻¹ for electrons and 4500 cm² V⁻¹s⁻¹ for holes.^7–11 However, it requires a high material quality to achieve such performances. Typically, both alloys are epitaxially grown on Ge or Ge-buffered substrates by chemical vapor deposition (CVD)^1,12 or molecular beam epitaxy (MBE).^13,14 Ge is used since it is complementary metal-oxide-semiconductor (CMOS)-compatible, has a relatively large lattice parameter, and allows post-growth thermal treatments under equilibrium conditions.¹⁵ Unfortunately, pure Ge wafers are expensive and the more complex layer stack of Ge-buffered Si substrates complicates the fabrication and characterization of lateral ICs. Furthermore, for many device concepts, insulating substrates are desired.¹⁶ Recently, the first GeSnOI substrates were fabricated by direct wafer bonding and etch-back approach^16–18 or by underetching and layer transfer to insulating substrates.¹⁹ These methods are cost-intensive and technically challenging. A much simpler way to fabricate Ge_1−xSn_x and Si_1−x−yGe_ySn_x on an insulating platform would be the direct growth of these alloys on commercially available ultra-thin silicon-on-insulator (SOI) wafers. In the last few years, the feasibility of growing single-crystalline Ge_1−xSn_x directly on Si substrates^20–22 was shown, and defect densities of about ∼10⁷ cm⁻² were estimated.²² In this paper, we present the fabrication of Ge_0.94Sn_0.06 and Si_0.14Ge_0.80Sn_0.06 on commercially available SOI substrates and apply non-equilibrium post-growth pulse laser annealing (PLA) to mediate between the highly lattice-mismatched alloys and the SOI substrate beneath. Nanosecond PLA helps us to improve the crystal structure of the Ge_1−xSn_x and Si_1−x−yGe_ySn_x alloys.

A commercially available 300 mm-SOI wafer with a 20 nm-thick top Si and 100 nm-thick SiO₂ layer was used as a low-cost substrate. The wafer was diced into 35 × 35 mm² pieces, and the native SiO₂ was removed by a 2.5% HF:DI etching for 15 s. Afterward, four SOI pieces were simultaneously inserted for each of the alloys into a solid-source MBE system with a base pressure of 1 × 10⁻¹⁰ mbar. The substrate was heated up to 700 °C with a ramp of about 30 °K min⁻¹. Then, the temperature was kept constant for 5 min to eliminate hydrogen dangling bonds on the Si surface created by HF etching.²³ After thermal stabilization, the MBE growth was performed at around 180 °C for Ge_0.94Sn_0.06 and 200 °C for Si_0.14Ge_0.80Sn_0.06. Both 20 nm-thick layers are in situ doped with Sb with a targeted concentration of 5 × 10¹⁹ cm⁻³. The elements Ge, Sn, and Sb were evaporated using Knudsen effusion cells. Si was evaporated via electron beam. Post-growth PLA was performed under atmospheric conditions with single pulses. The PLA tool ‘Coherent VarioLas ECO 308 5 × 5 for COMPexPro200’ is equipped with a 308 nm wavelength XeCl excimer laser with a fixed pulse length of 28 ns. A ‘MaxBlack EnergyMax Sensor’ measured the laser energy from which the energy density for the homogeneously irradiated 5 × 5 mm² area was calculated.

Cross-sectional high-resolution transmission electron microscopy (HR-TEM) imaging to evaluate the layer crystallinity was performed using an image-C_s-corrected Titan 80-300 microscope (FEI) operated at an accelerating voltage of 300 kV. High-angle annular dark-field scanning transmission electron microscopy (HAADF-STEM) imaging and spectrum imaging analysis based on energy-dispersive x-ray spectroscopy (EDXS) were performed at 200 kV with a Talos F200X microscope equipped with a Super-X EDX detector system (FEI). Before (S)TEM analysis, the specimen mounted in a high-visibility low-background holder was placed for 10 s into a Model 1020 Plasma Cleaner (Fischione) to remove potential contamination. Cross-sectional TEM lamellae preparation was done by in situ lift-out using a Helios 5 CX focused ion beam (FIB) device (Thermo Fisher, Eindhoven, Netherlands). For each sample, to protect its surface, a carbon cap layer was deposited beginning with electron-beam-assisted and subsequently followed by Ga-FIB-assisted precursor decomposition. Afterward, the TEM lamella was prepared using a 30 keV Ga-FIB with adapted currents. Its transfer to a 3-post copper Omniprobe lift-out grid was done with an EasyLift EX nanomanipulator (Thermo Fisher). To minimize sidewall damage, Ga ions with only 5 keV energy were used for final thinning of the TEM lamella to electron transparency. X-ray diffraction (XRD) was performed on a Rigaku SmartLab x-ray diffractometer system. The system is equipped with a copper (Cu) x-ray tube and a Ge (220) two-bounce monochromator. High-resolution XRD (HR-XRD) θ–2θ scans were carried out on the symmetrical 0 0 4 reflections. Reciprocal space maps (RSMs) were generated for the 0 0 4 and the asymmetrical 2 2 4 reflections by scanning ω and measuring the diffraction intensity in dependence of 2θ with the detector in 1D single-exposure mode. The samples were aligned by their 0 0 4 and 2 2 4 Si substrate reflections for these measurements. The lateral and vertical lattice parameters of the epitaxially grown layers were determined from the 2 2 4 RSM. Rutherford backscattering spectrometry (RBS) in random (RBS-R) and channeling (RBS-C) directions were performed using a 2 MV Van de Graaff accelerator. The used He⁺ beam had an energy of 1.7 MeV and beam currents between 10 and 20 nA. An aperture with a diameter of about 1 mm was used. Each measurement was performed with a detector angle of 170°. The obtained RBS spectra were fitted with the software SIMNRA.²⁴ RBS-C was performed along the [001] crystal axis. Time-of-flight (ToF) secondary ion mass spectrometry (SIMS) measurements were conducted before and after annealing. The used IONTOF V tool is equipped with a ToF mass separator. The material was sputtered by Cs⁺ with an energy of 500 eV and a sputter area of 400 × 400 μm². The analysis was performed with Bi₁⁺ having an energy of 15 keV and an area of 200 × 200 μm². Variable-field Hall-effect measurements in van-der-Pauw configuration were performed at room temperature using an HMS 9709A system from LakeShore. Close to the sample corners, 50 nm-thick circularly shaped Ni contacts with a diameter of 1 mm were fabricated by lithography, 1% HF:DI oxide etching, thermal evaporation of Ni, and lift-off. The magnetic flux density was varied between −5 and 5 T.

The microstructure of the as-grown Ge_0.94Sn_0.06 and Si_0.14Ge_0.80Sn_0.06 on SOI was investigated by TEM-based analyses, as presented in Fig. 1. The superimposed EDXS-based element distribution maps in Figs. 1(a) and 1(b) confirm the targeted layer stack with a relatively homogeneous distribution of Sn within Ge_0.94Sn_0.06 and Si_0.14Ge_0.80Sn_0.06, respectively. As shown in Figs. 1(c) and 1(e), the microstructure of Ge_0.94Sn_0.06 appears to be partially crystalline, where only some of the defective grains grow up to the sample surface. The other layer regions are characterized by an amorphous microstructure. The presence of such amorphous inclusions indicates an epitaxial breakdown during the growth, which appears when the critical thickness of highly mismatched alloys is exceeded.²⁵ The Si_0.14Ge_0.80Sn_0.06 layer in Figs. 1(d) and 1(f) is mainly single-crystalline but contains many stacking faults. The top surfaces of Ge_0.94Sn_0.06 and Si_0.14Ge_0.80Sn_0.06 have a native oxide layer and seem to be slightly rougher compared to the Ge_1−xSn_x and Si_1−x−yGe_ySn_x/Si interfaces, respectively. This suggests a “layer-by-layer” plus “three-dimensional island”-based (Stranski–Krastanov) growth with a small island spacing rather than the targeted “layer-by-layer” (Frank–van der Merwe) growth mechanism.²⁶ Since the microstructures of the as-grown alloys are defect-rich, post-growth annealing is required to improve the crystallinity. On the other hand, these Sn-containing alloys are metastable and would decompose during long thermal treatments above the growth temperature. Consequently, we decided to use ns-range PLA.

The microstructure after PLA with 0.20 J cm⁻² (Ge_0.94Sn_0.06) or 0.25 J cm⁻² (Si_0.14Ge_0.80Sn_0.06) is shown in Fig. 2. Both materials have a highly improved crystal structure compared to their as-grown states. The Ge_1−xSn_x sample is fully crystalline after PLA at 0.20 J cm⁻² but shows local inhomogeneities in the Ge_1−xSn_x layer thickness [Figs. 2(c) and 2(e)]. The Si_0.14Ge_0,80Sn_0.06 sample PLA-treated at 0.25 J cm⁻² also shows a single-crystalline structure with only few defects [see Figs. 2(d) and 2(f)]. The EDXS-based element distribution maps in Figs. 2(a) and 2(b) suggest an out-diffusion of Sn (particularly for Si_0.14Ge_0,80Sn_0.06 after PLA at 0.25 J cm⁻²) and the formation of a thick Sn-containing oxide at the sample surface. Further details about the element redistribution can be found in Sec. C in the supplementary material. On the other hand, any formation of Sn clusters or filaments was not observed after PLA with low energy densities, which is significantly different compared to pulse laser melting results of Ge_1−xSn_x.^27–29 

The RBS-R/C results of the Ge_1−xSn_x and Si_1−x−yGe_ySn_x on SOI before and after annealing are shown in Figs. 5 and 6, respectively. The obtained spectra contain Sn superimposed with Sb (1460–1510 keV), Ge (1325–1390 keV), and Si (<1000 keV). Since the Sb concentration is only about 0.1 at. %, the signal in the spectra is mainly related to Sn. The Si contribution of Si_0.14Ge_0.80Sn_0.06, located between 950 and 1000 keV, is merged with the pure Si signal of the SOI layer and the high-energy tail of the buried SiO₂.

The RBS-R spectra of the as-grown Ge_0.94Sn_0.06 and Si_0.14Ge_0.80Sn_0.06 states were fitted by SIMNRA and confirmed the expected layer compositions and thicknesses.

The RBS-C spectrum of the Ge_0.94Sn_0.06 as-grown state in Fig. 5 is similar to its RBS-R counterpart since the layer contains amorphous inclusions. Analog channeling results were also obtained for the mildly treated PLA 0.12 J cm⁻² sample. Channeling effects in the Si, Ge, and Sn/Sb signals can be observed after PLA with 0.15, 0.18, and 0.20 J cm⁻².

The occurrence of channeling in Si, Ge, and Sn/Sb in the Si_0.14Ge_0.80Sn_0.06 as-grown state in Fig. 6 confirms the epitaxial growth of Si_1−x−yGe_ySn_x on the SOI wafer. This matches the TEM results in Figs. 1(d) and 1(f). PLA of Si_0.14Ge_0.80Sn_0.06 with E_d ≥ 0.15 J cm⁻² causes a slight de-channeling compared to the Si_0.14Ge_0.80Sn_0.06 as-grown state.

In general, the obtained χ_Si, χ_Ge, and χ_Sn/Sb of the fabricated Ge_1−xSn_x and Si_1−x−yGe_ySn_x in Table I are relatively high because of (i) the observed defects in Figs. 1 and 2 can displace the atomic lattice positions, (ii) the superposition of crystal channeling with de-channeling events from surface defects, and (iii) the formation of the thicker Ge_1−xSn_x- or Si_1−x−yGe_ySn_x-oxide layer after PLA [see Figs. 2(a) and 2(b)]. The presence of this oxide layer might be avoidable if the PLA process is performed under an inert gas atmosphere or in situ in an MBE cluster tool. The ξ_Sn/Sb,Si calculation results for the incorporation of Sn/Sb on Si substitutional sites are not presented since the superposition of the Si signal with the top Si and SiO₂ tail regions of the SOI causes errors in the χ_Si result.

The appearance of channeling in the Ge_1−xSn_x microstructure and the SOI beneath suggest epitaxial recrystallization or regrowth during the PLA process. The lowest channeling yields in Table I were achieved after PLA with 0.15 and 0.18 J cm⁻² with χ_Ge ≈ 60% and χ_Sn/Sb ≈ 75%. Additionally, the occupation of Sn/Sb on Ge lattice sites with ξ_Sn/Sb,Ge = 59.6% and 66.4% also suggests a reasonable amount of incorporated/activated Sn/Sb atoms on substitutional lattice sites. However, further increasing the PLA to E_d = 0.20 J cm⁻² causes de-channeling in Ge and Sn/Sb. For Si_0.14Ge_0.80Sn_0.06, the best channeling properties were observed for the as-grown state. However, the direct comparison of Figs. 1(f) and 2(f) clearly shows an improved crystal structure. Hence, the channeling in Ge_1−xSn_x and Si_1−x−yGe_ySn_x is most likely systematically overestimated due to the earlier-mentioned de-channeling effects (oxide layer, and surface defects).

The dopant concentration and distribution in dependence of the PLA E_d were investigated by SIMS and Hall-effect measurements. The SIMS results in Figs. 7 and 8 show the element depth distribution before and after annealing. All in situ-doped Ge_0.94Sn_0.06 and Si_0.14Ge_0.80Sn_0.06 on SOI samples have a relatively homogeneous Sb intensity profile despite the surface-related amplitude (see Fig. 7). Unfortunately, the Sn concentration appears as slightly reduced after PLA.

The Si and Ge profiles of the Ge_1−xSn_x samples in Fig. 8(a) are relatively homogenous, but the Si_1−x−yGe_ySn_x layers show a redistribution of Ge and Si after PLA in Fig. 8(b). Furthermore, the PLA 0.15 J cm⁻² state shows a small kink close to the SOI interface. This kink is related to the almost PLA-unaffected Si_1−x−yGe_ySn_x layer, which correlates with the weak intensity signal below the main SiGeSn 2 2 4 reflection in Fig. 4(b). The sample annealed with 0.20 J cm⁻² shows a relatively constant Ge concentration while Sn increases and Si decreases toward the surface. The slightly varying chemical composition across the layer thickness and the different crystal qualities influence the sputter yield and might reduce the accuracy in the quantitative SIMS analysis. This could be the reason for the slightly overestimated Sn concentration in the as-grown states in Fig. 7. After annealing with 0.15 and 0.25 J cm⁻², a redistribution of Si toward the SOI interface and a Ge diffusion toward the surface is visible.

The Hall-effect results of the Ge_1−xSn_x and Si_1−x−yGe_ySn_x layers before and after post-growth PLA are shown in Fig. 9. The carrier concentrations in the as-grown states are 1.8 × 10¹⁹cm⁻³ (Ge_0.94Sn_0.06) and 5.1 × 10¹⁷ cm⁻³ (Si_0.14Ge_0.80Sn_0.06). After PLA with E_d ≥ 0.15 J cm⁻², a significant amount of Sb could be activated in both alloys. In the case of Ge_1−xSn_x, active carrier concentrations of 3.9 × 10¹⁹ cm⁻³ (0.15 J cm⁻²) and 4.2 × 10¹⁹ cm⁻³ (0.18 J cm⁻²) were determined, which are close to the targeted absolute Sb concentration of 5 × 10¹⁹ cm⁻³. Additionally, the carrier mobility increased from 0.5 cm² V⁻¹s⁻¹ in the Ge_0.94Sn_0.06 as-grown state to 6.8 cm² V⁻¹s⁻¹ after PLA with 0.18 J cm⁻². The simultaneous increase of n_e− and μ_e− after PLA is related to the higher crystal quality. In the Si_1−x−yGe_ySn_x case, n_e− could be increased up to 2.3 × 10¹⁹ cm⁻³ (E_d = 0.15 J cm⁻²). However, a too high PLA energy density reduces the active carrier concentration, as shown for Si_1−x−yGe_ySn_x with E_d = 0.25 J cm⁻². On the other hand, the reduced n_e− increased μ_e− from 6.7 cm² V⁻¹s⁻¹ (PLA with E_d = 0.20 J cm⁻²) to 23.0 cm² V⁻¹s⁻¹ after PLA with E_d = 0.25 J cm⁻² due to a deactivation of dopants.

The studied Ge_0.94Sn_0.06 and Si_0.14Ge_0.80Sn_0.06 films grown on SOI substrates are almost strain-relaxed and contain many defects since the layer thickness exceeds the critical thickness for plastic strain relaxation. Partially replacing Ge by Si reduces the lattice mismatch between the alloy and the Si substrate from about 5.3% (Ge_0.94Sn_0.06) to about 1.9% (Si_0.14Ge_0.80Sn_0.06) and helps us to improve the crystal structure. Post-growth PLA improves the layer quality significantly and activates up to 80% of the Sb-donors. However, annealing under ambient conditions generates an Sn-containing oxide on the surface and slightly redistributes Si, Ge, and Sn, especially for the ternary Si_1−x−yGe_ySn_x alloy.

Overall, it can be concluded that the Ge_0.94Sn_0.06 and Si_0.14Ge_0.80Sn_0.06 grown directly on SOI layers contain many defects, which is a challenge for their application as an active component in opto- or nanoelectronic devices. Hence, it is suggested to use a post-growth treatment to mediate between the large lattice mismatch of the alloy and the substrate. Such a treatment should be performed in an inert atmosphere or vacuum to avoid oxide formation. The results show that PLA of Sn-containing group-IV alloys on SOI wafers is an efficient way to fabricate Ge_1−xSn_x and Si_1−x−yGe_ySn_x alloys compatible with CMOS technology on an insulating platform.

See the supplementary material for supplements that support the presented XRD findings. Section A discusses a possible tilt between the top silicon and the Si carrier substrate of the SOI wafer. Section B shows and explains additional 0 0 4 HR-XRD results, which support the discussed 2 2 4 XRD-RSM data. Furthermore, vertical EDXS line scans of Ge0.94Sn0.06 and Si0.14Ge0.80Sn0.06 in the as-grown state and after PLA are presented in Sec. C.

This work was partially supported by the Bundesministerium für Bildung und Forschung (BMBF) under the project “ForMikro”: Group-IV heterostructures for high-performance nanoelectronic devices (SiGeSn NanoFETs) (Project-ID: 16ES1075). We gratefully acknowledge the HZDR Ion Beam Centre for their support with RBS. The authors thank Annette Kunz for TEM specimen preparation. Furthermore, the use of the HZDR Ion Beam Center TEM facilities and the funding of TEM Talos by the Bundesministerium für Bildung und Forschung (BMBF), Grant No. 03SF0451, in the framework of HEMCP are acknowledged. We thank Dr. Olav Hellwig and his group at HZDR for providing access to the x-ray diffractometer.

The authors have no conflicts to disclose.

O. Steuer: Conceptualization (equal); Formal analysis (equal); Investigation (equal); Validation (equal); Visualization (equal); Writing – original draft (equal); Writing – review & editing (equal). D. Schwarz: Writing – review & editing (supporting). M. Oehme: Writing – review & editing (supporting). F. Bärwolf: Data curation (supporting); Formal analysis (supporting); Investigation (supporting); Validation (supporting); Writing – review & editing (supporting). Y. Cheng: Investigation (equal). F. Ganss: Data curation (equal); Formal analysis (equal); Validation (equal); Visualization (equal); Writing – review & editing (equal). R. Hübner: Data curation (supporting); Formal analysis (supporting); Validation (supporting); Visualization (equal); Writing – review & editing (supporting). R. Heller: Formal analysis (supporting); Writing – review & editing (supporting). S. Zhou: Formal analysis (supporting); Supervision (supporting); Validation (supporting); Writing – review & editing (supporting). M. Helm: Supervision (supporting); Writing – review & editing (supporting). G. Cuniberti: Supervision (supporting). Y. M. Georgiev: Funding acquisition (equal); Project administration (equal); Supervision (equal); Visualization (supporting); Writing – review & editing (supporting). S. Prucnal: Conceptualization (equal); Formal analysis (equal); Funding acquisition (equal); Investigation (equal); Supervision (equal); Visualization (equal); Writing – original draft (equal); Writing – review & editing (equal).

The data that support the findings of this study are available from the corresponding authors upon reasonable request.