Selecting alternative metals for advanced interconnects

Microelectronic circuits are central elements in myriads of electronic appliances in almost every aspect of today’s life. Logic circuits, memory cells, and sensors are used to process, store, and detect information in diverse applications, ranging from computers and smartphones to automobiles and medical equipment. The success of microelectronics relies on the relentless miniaturization of the underlying building blocks, which, in the case of logic circuits based on transistors, has been epitomized by the famed Moore’s law.¹ Similar scaling trends also apply to other devices, for example, to memory cells. The reduction of device dimensions in combination with the enormous increase of device density² has led to large performance benefits, but also to lower energy consumption per operation and, at least for older generations, much reduced cost per function. For instance, the cost to fabricate one transistor has been reduced by a factor of $10 9$ since 1970.³ 

In the public perception, Moore’s law has been historically connected to scaling transistors or memory cells. However, scaling interconnects is of equal importance to uphold Moore’s law. Interconnect lines and vias provide signal, power, and clock to the active components of the circuits, such as complementary metal–oxide–semiconductor (CMOS) transistors or memory elements, and, thus, are central in microelectronic circuits and systems with advanced functionality [Fig. 1(a)]. As an example, the area of a static random-access memory (SRAM) cell, used as cache memory in logic processors, is determined in one direction by the gate pitch (also termed “contacted poly pitch”) of the transistors (the transistor size), but by the pitch of the metal lines (the interconnect pitch) in the orthogonal direction [Fig. 1(b)]. Hence, to reduce the cell area, both transistor and interconnect dimensions should be scaled.

In earlier technology nodes, transistor performance traditionally improved as dimensions were scaled down, yielding the performance benefits described above. However, this trend does not extend to interconnects. Reducing the cross-sectional area of a wire inevitably increases its resistance per unit length, resulting in greater energy dissipation and higher resistive–capacitive delay (⁠ $RC$-delay). At current interconnect line widths, ranging from 12 to 15 nm (see Sec. I A), interconnect performance has become a primary constraint on the overall performance of advanced microelectronic circuits.^7–18 

For transistors, scaling has been accompanied by significant architectural innovations.^19–21 In contrast, architectural changes in interconnects are limited, and thus, performance enhancements mainly need to occur through materials and process innovation. One approach to reducing interconnect capacitance involves the use of dielectrics with lower permittivity (low- $κ$ dielectrics)¹⁰ or the introduction of air gaps.^22,23 However, these advancements have been hampered by the reduced mechanical stability of the resulting interconnect structures, leading to reliability issues during packaging.

Consequently, optimizing the metallization scheme has emerged as a critical focus of interconnect research in recent years.^{12,18,24–33} The current Cu dual-damascene metallization scheme (Fig. 2), which replaced Al-based metallization post-1999,^10,34–36 is facing growing issues for several reasons. First, Cu requires diffusion barriers and adhesion liners to ensure the interconnect reliability. Without diffusion barriers (typically TaN-based), Cu migration into surrounding dielectrics leads to dielectric breakdown and shorting between adjacent lines (see Sec. III). Moreover, Cu electromigration becomes an increasing issue at scaled dimensions (see Sec. III). This is mitigated by incorporating adhesion liner layers (typically Co/Ru) between the TaN barrier and Cu as well as by capping layers.^10,36–38 However, the combined thickness of barrier and liner layers cannot be reduced below 2 to 3 nm without compromising functionality. Hence, in narrow lines, the high-resistivity barrier and liner layers occupy an increasingly significant fraction of the total metallization volume, reducing the available space for Cu, while contributing minimally to the wire’s conductance.

Furthermore, as elucidated in Sec. II, the resistivity of Cu increases sharply at reduced dimensions due to the more pronounced effects of grain boundary and surface scattering. Both the increased resistivity and the decreasing volume fraction of Cu contribute to a rapid increase in the line and via resistances per unit length as interconnect dimensions are scaled down. This results in a significant deterioration of interconnect performance, even for relatively short lines. Additionally, the dual-damascene metallization integration process necessitates increasingly disruptive modifications to ensure void- and defect-free interconnects with robust mechanical stability.

These issues can be mitigated by selecting alternative metals that ideally do not require barrier and liner layers while exhibiting lower sensitivity of resistivity to nanoscale dimensions. Although this approach cannot reverse the increase in line resistance per unit length, we will demonstrate below that alternative metals and metallization schemes can outperform Cu at sufficiently small line widths. In this Tutorial, we will discuss the various aspects relevant for the selection of potential alternative metals for advanced interconnects. The selection process is multifaceted and must address the challenge from different angles. To this end, we have developed a multistage framework to identify, downselect, and benchmark alternative metals for interconnect applications (Fig. 3).

This Tutorial is organized as follows. We first examine the sensitivity of resistivity to nanoscale dimensions and introduce a material screening process. Next, we discuss reliability aspects, focusing on time-dependent dielectric breakdown as well as on electromigration. We then apply this selection process to elemental, binary, and ternary metals, highlighting current and future research directions. Given the strong connection between metal selection and future integration schemes, we will also briefly discuss integration and process considerations for alternative metals in upcoming technology nodes. Finally, with sustainability becoming increasingly crucial to minimizing the ecological footprint of the microelectronics industry, we introduce a life cycle assessment framework for interconnect metals and apply it to various promising candidates identified through our selection criteria.

Historically, interconnect scaling has been guided by industry roadmaps, such as the International Technology Roadmap for Semiconductors (ITRS),³⁹ presently called the International Roadmap for Devices and Systems (IRDS).⁴⁰ However, today, no industry-wide roadmap exists, and also, technology node nomenclature has become ambiguous. At present, commercial microelectronic chips feature minimum interconnect pitches around 25 nm, with further scaling anticipated to reach sub-20 nm metal pitches in the near future (see Table I). This implies that line widths, which are equivalent to half the metal pitch, will soon reach sub-10 nm dimensions. This is especially significant as the contacted poly pitch (transistor gate pitch) has become close to physical limits and is not expected to be scaled much further. Therefore, future area gains for CMOS circuits must primarily stem from transistor architecture innovation (e.g., CFET) as well as continued interconnect pitch scaling.

As previously noted, such small line widths may not be compatible with the Cu dual-damascene metallization scheme employed today in scaled interconnects (Fig. 2). While ongoing efforts to optimize Cu dual-damascene processing may yield incremental improvements, achieving the minimum interconnect dimensions in Table I will require disruptive approaches, potentially involving novel materials, processes, and integration schemes. As indicated in the table, the target critical dimensions for interconnect lines and vias, equivalent to half the metal pitch, fall within the range between 5 and 10 nm, providing guidelines for both metal selection and process development.

For decades, it has been well-established that the resistivity of metallic nanostructures, such as thin films and nanowires, is typically much higher than that of their bulk counterparts.^44–49 This presents a significant challenge for interconnect scaling, as the increase in line and via resistance occurs at a much faster rate than what would be predicted solely by the reduction in geometrical dimensions, particularly for critical dimensions below 10 nm.

The resistivity increase can be primarily attributed to the combined effects of scattering at rough surfaces or interfaces^44,45 and scattering at grain boundaries.^47,48 To quantitatively describe this behavior, several transport models have been developed for thin films, accounting for top and bottom surface/interface scattering.^48,50–59 However, it should be noted that no comprehensive one-dimensional transport model currently exists to describe nanowires, which are bounded by four surrounding surfaces. Despite this, the qualitative behavior of nanowires is expected to be similar to that of thin films, and thus, “thin-film-derived” resistivity models have been applied to understand the scaling behavior of nanowires as well.^60–68 

In this section, we introduce the basic physics governing the resistivity of metal nanostructures. We will demonstrate that the mean free path of charge carriers in bulk metals is a critical parameter to characterize how resistivity depends on nanostructure dimensions. Following this, we discuss additional scattering mechanisms present in compound metals. Finally, we introduce ab initio screening methods to calculate the mean free path and identify promising metals that may exhibit lower resistivity than Cu at the nanoscale.^69–71 

The most widely used approach to understand the increase in resistivity at reduced dimensions is based on the Boltzmann transport equation. The Boltzmann transport equation describes the statistical distribution of charge carriers in non-equilibrium conditions, e.g., when an electric field is applied.

The derivation of Eq. (7) relies on the applicability of Matthiessen’s rule for phonon and grain boundary scattering. However, this assumption may break down in nanocrystalline, nearly amorphous films with large disorder.^76–78 In such films, localization effects become prominent,^79,80 typically resulting in a notably reduced temperature coefficient of resistivity compared to bulk materials,^76,78 as well as in different transport mechanisms, which cannot be described by Eq. (7).

By contrast, the derivation of Eq. (7) does not require Matthiessen’s rule to apply for surface scattering. In fact, Matthiessen’s rule is typically not cromulent for surface scattering and grain boundary scattering in thin metallic films due to the renormalization of the mean free path by grain boundary scattering.⁴⁸ Consequently, the individual contributions of bulk, surface, and grain boundary scattering to the thin-film resistivity can be challenging to quantify.⁷⁰ Therefore, approximate versions of Eq. (7) that separate these contributions should be used with caution.

Equation (7) contains five independent material parameters: bulk single-crystal resistivity, electron mean free path, surface/interface scattering specularity, average grain size, and grain boundary reflection coefficient. In practice, the grain size often depends strongly on film thickness, introducing a secondary indirect source of thickness dependence of thin-film resistivity, in addition to surface scattering effects. The relationship between the grain size and film thickness, $d(h)$⁠, is highly sensitive to deposition parameters and is not an intrinsic property of the material. Although a linear dependence has historically been assumed in some cases, experimental data typically do not support this assumption over a wide range of thicknesses [see Fig. 4(a)]. Post-deposition annealing can further influence grain size, promoting grain growth or recrystallization.^81,82

As a consequence, it is not possible to quantitatively predict the resistivity of metallic nanostructures based solely on bulk properties. As previously mentioned, the relationship $d(h)$ is strongly influenced by deposition process parameters and thermal budget, and no predictive models currently exist for grain structures and grain sizes beyond general trends.^83,84 Given that experimental data indicate that grain boundary scattering can dominate thin-film resistivity,⁷⁰ the evaluation of metals should consider the potential for achieving large-grain films (or nanowires). However, this cannot be reliably predicted by ab initio calculations, requiring experimental studies on the grain size and annealing behavior to complement transport and reliability metrics for a more accurate assessment of alternative metals.

A second limitation is the difficulty in calculating or predicting realistic values for the parameters $R$ and $p$⁠. The parameter $R$ represents the electron reflection probability at a grain boundary, which generally depends on the relative orientation of grains on either side of the boundary and the atomic configuration of the grain boundary itself. Both theoretical calculations^85–88 and experimental studies^66,89 consistently show significant variations in $R$ between small-angle or coincidence grain boundaries (with low $R$⁠) and large-angle random grain boundaries (with higher $R$⁠). In polycrystalline films, the relevant value of $R$ is an effective average across all grain boundary configurations, making it strongly dependent on the film’s microstructure. While some trends suggest that larger cohesive energies lead to higher $R$ values,⁹⁰  $R$ should not be treated as an intrinsic property of the metal alone.

Similarly, the surface scattering specularity, $p$⁠, is influenced not only by the metal itself but also by the properties of the adjacent surfaces or interfaces. The cladding material^54,91–93 and surface or interface roughness are expected to play critical roles. While theoretical^52–57,59 and experimental^51,53 studies have explored surface scattering as a function of surface roughness, quantitative agreement between theory and experiment remains elusive. Hence, predictive calculations for screening purposes are not feasible. Furthermore, because surface scattering depends on both the cladding material and surface roughness, it cannot be regarded as an inherent material property neither.

However, Sec. II A 1 demonstrates that the increase in resistivity, whether due to surface or grain boundary scattering, scales with the bulk mean free path of the charge carriers, $λ$⁠. Therefore, the effects of high $R$⁠, small grains, or diffuse interfaces can be mitigated by a short $λ$⁠. This is illustrated in Fig. 4(b), which shows the dependence of thin-film resistivity on the grain size, calculated using Eq. (7), for $ρ 0=5.3μΩ$ cm, $R=0.45$⁠, $p=0$ (diffuse surface scattering), and a fixed film thickness of 20 nm as an example. The results indicate that a shorter mean free path, $λ$⁠, leads to a weaker dependence of resistivity on the grain size, thereby reducing the impact of grain boundary scattering. A similar trend can be observed for the dependence of thin-film resistivity on thickness in the presence of diffuse surface scattering.

This insight has driven the search for metals with short $λ$ as potential alternatives to Cu. At room temperature, the mean free path of Cu is as high as 40 nm,⁶⁹ which is large compared to typical state-of-the-art interconnect dimensions and grain sizes. Therefore, metals with much shorter $λ$ promise to be less sensitive to interconnect scaling. An ab initio methodology for screening short- $λ$ metals will be introduced in Sec. II C. The complete alternative metal screening process and its current status will be detailed in Sec. IV.

The thin-film resistivity models discussed above assume a spherical isotropic Fermi surface, effectively treating the metal as a free-electron gas with an effective mass. Consequently, both bulk and thin-film resistivities are independent of the crystallographic direction of the current, enabling the derivation of the Fuchs–Sondheimer and the Mayadas–Shatzkes equations in Eqs. (5) and (7), respectively. Due to the inherent complexity of the problem, no thin-film resistivity model currently exists that accounts for the detailed band structure of the metal while incorporating both surface and grain boundary scattering. While the Mayadas–Shatzkes model in Eq. (7) has been able to successfully describe experimental measurements,^{67,70,94–101} the lack of a quantitative understanding of key model parameters, such as $R$ and $p$⁠, limits the ability to accurately evaluate the validity of the spherical Fermi surface approximation across different metals.

From a macroscopic perspective, the resistivity of cubic crystal systems is isotropic, making the approximation of a spherical Fermi surface potentially valid for such metals. However, in less symmetric structures (e.g., hexagonal, tetragonal, orthorhombic, monoclinic, and trigonal), the resistivity becomes anisotropic in the bulk metal. For example, hexagonal Ru exhibits lower resistivity along the hexagonal axis compared to the two perpendicular (in-plane) directions.^102,103 To address this, a semiclassical model based on the Mayadas–Shatzkes framework was developed for ellipsoidal Fermi surfaces.¹⁰⁴ This model can describe metals with hexagonal, tetragonal, or orthorhombic crystal symmetries. While the mathematical details are beyond the scope of this Tutorial, the model reveals a significant influence of Fermi surface anisotropy on surface scattering without affecting grain boundary scattering.

This behavior is illustrated in Fig. 5, which shows the thin-film resistivity as a function of film thickness, with varying degrees of Fermi surface anisotropy, based on the model from Ref. 104. In these simulations, grain boundary scattering was neglected (⁠ $R=0$⁠), allowing surface scattering to dominate. The results demonstrate that in metals with low in-plane resistivity (corresponding to a small in-plane effective mass) and high out-of-plane resistivity (a large out-of-plane effective mass), surface scattering is progressively suppressed, leading to a reduction in the thickness dependence of the thin-film resistivity due to surface scattering.

In principle, this anisotropy effect could be exploited to reduce the resistivity of nanowires, and therefore, the use of two-dimensional and one-dimensional metals (with a single low-resistivity crystallographic direction) in interconnect applications has been proposed.¹⁰⁵ However, two important considerations must be noted. First, since Matthiessen’s rule does not generally apply, the presence of significant grain boundary scattering—which is unaffected by reduced dimensionality—can suppress the benefits of surface scattering reduction in two- or one-dimensional metals, particularly in small-grain microstructures. Second, the application of one-dimensional metals in interconnects would necessitate single-crystal materials to ensure that the current is always aligned with the low-resistivity crystallographic direction. Currently, there is no established integration route for incorporating single-crystal lines in commercial interconnects, limiting the practical application of such materials to fundamental material science at this stage.

Before introducing first-principles screening methodologies for identifying and selecting promising metals for interconnect applications based on the mean free path of charge carriers, $λ$⁠, it is essential to briefly discuss additional sources of scattering that are particularly relevant for compound metals. In crystalline materials, any deviation from periodicity can result in electron scattering.¹⁰⁶ In elemental metals, such deviations include vacancy or vacancy cluster defects as well as impurities. In high-quality polycrystalline thin films of relevant metals, vacancies and impurities primarily influence the resistivity at cryogenic temperatures, but their effects are generally negligible at room temperature, where scattering by phonons, grain boundaries, and surfaces dominates.

The situation can, however, be markedly different for compound metals. Alloys are inherently disordered materials, characterized by the random distribution of different atoms on lattice sites. As a result, the crystal lacks periodicity, leading to increased resistivity due to alloy scattering. This effect is illustrated in Fig. 6 for the seminal Cu–Au system.¹⁰⁷ In disordered Cu $x$Au $1 − x$ alloys, the resistivity is considerably higher than in the pure elemental metals Cu and Au, reaching a maximum at 50% Au content, where disorder is the greatest. By contrast, the system also forms two ordered intermetallic phases, Cu $3$Au and CuAu, near their respective stoichiometries. In these ordered phases, the resistivity shows a sharp minimum, significantly lower than that of the disordered alloys.

These observations highlight the necessity of minimizing alloy scattering to achieve resistivities relevant for interconnect applications in compound metals. As a result, in addition to elemental metals, for which such issues do not arise, only ordered intermetallics are of potential interest in alternative metal screening efforts. This challenge is further compounded by the difficulty of accurately measuring and optimizing intermetallic ordering in thin films. A more detailed discussion and the current state of the art can be found in Secs. IV C and IV D.

The discussions in Secs. II A 2 and II A 3 emphasize that accurately predicting the resistivity of thin films or nanowires is not feasible without detailed microstructural information, which is inherently dependent on deposition process conditions. Additionally, resistivity models, such as the Mayadas–Shatzkes model in Eq. (7), rely on the assumption of a spherical Fermi surface (free-electron gas), and metal-specific scaling is represented solely by a single mean free path value. While it is possible to compute the electron–phonon-limited resistivity of metals from first principles by considering detailed band structures,¹⁰⁹ such calculations remain computationally intensive, restricting feasible system sizes to only a few atoms per unit cell. The primary limitation is the computational cost of calculating the electron–phonon coupling and the corresponding relaxation times. Moreover, incorporating grain boundaries into this framework is highly challenging. To date, these factors constrain the development of a fully predictive downselection methodology capable of directly identifying the most promising metal candidates for interconnect applications.

Consequently, the metal selection problem must be approached in stages, as outlined in Fig. 3. Nevertheless, screening metals of potential interest remains feasible using a $ρ 0×λ$ figure of merit, which can be computed using ab initio methods with relatively low computational cost, as introduced below. The application of this methodology for screening elemental and compound metals will be discussed in Sec. IV.

As noted above, the calculation of the conductivity tensor requires the knowledge of the relaxation time $τ n k$⁠, which is costly to calculate by ab initio methods. In general, $τ n k$ of an electron depends on its wavevector $k$ and band index $n$⁠; therefore, metals typically show a broad distribution of mean free paths,^72,110 as illustrated in Fig. 7(a) for Cu along two crystallographic directions.

The key advantage of the constant relaxation time approximation is that the right-hand side of Eq. (9) depends only on the morphology of the Fermi surface, eliminating the need for detailed knowledge of electron–phonon interactions. As a result, the calculation of the $ρ 0 τ _ _$ transport tensor is computationally much less demanding, rendering it suitable for evaluating a wide range of metals.^69,71

One practical application of this approach involves the approximate determination of a single-valued mean free path $λ$ (or relaxation time $τ$⁠) of a metal when the bulk resistivity $ρ 0$ is known, for instance, from experimental data. It is noteworthy that for cubic systems, the $ρ 0 λ _ _$ and $ρ 0 τ _ _$ tensors are diagonal and, thus, reduce to a single isotropic value.⁶⁹ Many semiclassical thin film transport models, such as the Mayadas–Shatzkes model in Eq. (7),⁴⁸ assume a simplified isotropic free-electron gas and consequently neglect band structure effects, including their influence on the mean free path. For real metals with complex band structures, it may be possible to replace the exact $k$-dependent mean free path by an effective mean free path. However, rigorous calculations of the electron–phonon coupling are required for accurate determination of this effective value. Therefore, the $λ$ value extracted from the $ρ 0 λ _ _$ tensor (divided by the bulk resistivity $ρ 0$⁠) has been utilized as an effective mean free path in thin-film transport models. Given the experimental challenges associated with directly measuring the mean free path,¹¹¹ the accuracy of this approximation remains uncertain. Nevertheless, employing $ρ 0 λ _ _$-derived values for the mean free path has generally led to satisfactory agreement between semiclassical transport models and experimental observations.^{67,70,94–101}

Second, the $ρ 0 λ _ _$ tensor can serve as a figure of merit for a metal, indicating its potential for achieving low resistivity at nanoscale dimensions. Lower values of this tensor correspond to metals with greater scaling potential. Consequently, both the $ρ 0 λ _ _$ and $ρ 0 τ _ _$ tensors have been extensively employed to identify promising alternative metals for nanoscale interconnect applications. A significant advantage of this approach lies in its substantially reduced computational cost compared to independently calculating the electron–phonon mean free path and bulk resistivity, enabling the screening of a wide range of materials. However, given the inherent approximations, the screening results should be interpreted with caution, as they may not accurately predict the thin film resistivity (see also Sec. II A 2). Nevertheless, this screening methodology has proven valuable, and the current state-of-the-art techniques utilizing this approach for alternative metal screening are discussed in Sec. IV.

While the methodology introduced in Sec. II C has been successfully applied to screening both elemental and compound metals, its accuracy in predicting thin-film or nanowire resistivities is limited. In reality, the mean free path of charge carriers depends strongly on their wavevector $k$⁠. As depicted in Fig. 7(a) for Cu, the mean free path varies significantly along different directions on the Fermi surface. Consequently, incorporating the complete anisotropic band structure into transport calculations and screening efforts is essential for achieving a more accurate understanding of resistivity at nanoscale dimensions.

When grain boundary scattering is neglected (i.e., considering only phonon and surface scattering), the thin film resistivity can be predicted ab initio. The calculated relationship between thin-film resistivity and film thickness for Cu is shown in Fig. 7(b). It is important to note that Eq. (12) indicates that the resistivity of thin films (or nanowires) depends not only on the transport direction but also on the orientation of the surface normal (growth orientation). This holds true even for metals with isotropic bulk resistivity, such as cubic metals, including Cu, and can be explained by the reduced symmetry arising from dimensional confinement.

For single-crystal films with negligible grain boundary scattering, the results are, in principle, exact, apart from the usual approximations inherent to density functional theory (DFT). While grain boundary scattering in textured films could theoretically be incorporated via a grain-size-dependent mean free path, its accurate treatment relies heavily on the knowledge of the detailed microstructure and remains challenging for current ab initio techniques.

This figure of merit accounts for anisotropic transport effects, such as the suppression of surface scattering discussed in Sec. II A 3, making it particularly suitable for single-crystal wires, in which transport occurs in well-defined crystallographic directions. For certain crystalline orientations, this can result in highly favorable figures of merit for specific materials, in particular, one-dimensional metals.¹⁰⁵ However, it is important to note that in random polycrystalline films and nanowires, surface scattering is averaged over all grain orientations. Additionally, in films or nanowires where resistivity is predominantly governed by grain boundary scattering (e.g., in small-grain polycrystalline films), the suppression of surface scattering is significantly reduced (see Sec. II A 3). Under these conditions, benchmarking metals using Eq. (10) remains the most appropriate approach.

A second critical aspect in selecting new metallization schemes for interconnects is the reliability of both the metal and the surrounding dielectric materials. Interconnect failure can originate from degradation in either the metal or the dielectric. Analogous to line resistance, interconnect reliability tends to deteriorate as wires and vias are miniaturized. Initially, the limited electromigration resistance of Al led to the adoption of Cu as the primary interconnect metallization more than two decades ago.³⁴ However, the reliability of Cu metallization is now facing increasing challenges. As elaborated in Secs. III A and III B, barrier and liner layers are essential for maintaining reliability but must be scaled alongside interconnect dimensions to leave sufficient room for the Cu conductor. Due to the limited scalability of these layers, they eventually occupy a substantial fraction of the interconnect volume while contributing minimally to the overall conductance. As demonstrated in Sec. V using calibrated line resistance models, barrier- and liner-less metallization is essential for realizing low-resistance interconnects, outperforming current Cu-based metallization schemes. In Secs. III A and III B, we will delve into the fundamentals of both metal and dielectric reliability. The current state of the art regarding the reliability of specific elemental and binary alternative metals will be explored in Sec. IV.

Time-dependent dielectric breakdown (TDDB) is a physical degradation process in which a dielectric material, subjected to a constant electric field below its intrinsic breakdown strength, progressively deteriorates and ultimately fails over time. This failure can be attributed to the formation of conductive paths (filaments) within the dielectric, which can short-circuit adjacent metallic electrodes.¹¹² Rapid failure may result either from gradual intrinsic damage to the dielectric material (e.g., vacancy formation) or from the drift of metal from nearby interconnect lines or vias. In the latter scenario, metal ions drift through the dielectric under the influence of the applied electric field, contaminating the dielectric, increasing leakage currents, and ultimately causing dielectric breakdown and shorting between interconnect lines.^113,114

The time-dependent dielectric breakdown behavior depends on the materials used, both metals and dielectrics. For metals, there exists a thermodynamic barrier that determines the detachment of ionized metal atoms and their subsequent drift or diffusion into the low- $κ$ dielectric. This barrier generally scales with the metal’s cohesive energy. Consequently, refractory metals, which exhibit significantly higher cohesive energies compared to Cu, present a higher barrier, thereby suppressing the drift and diffusion of metal ions into the dielectric and resulting in a substantially longer time-dependent dielectric breakdown lifetime. It is important to note that the drift and diffusion of metal ions within the dielectric are less influenced by the cohesive energy of the metal and are instead primarily dependent on the binding energy of metal impurities in the dielectric. Nevertheless, for metals relevant to interconnects, the dominant thermodynamic barrier arises from the detachment energy. Therefore, metals with high cohesive energy (i.e., refractory metals) are expected to exhibit significantly improved time-dependent dielectric breakdown lifetimes.

Moreover, the selection of dielectrics also influences the time-dependent dielectric breakdown performance of interconnects. Advanced interconnects utilize low- $κ$ materials to minimize interconnect capacitance.^115–118 The low dielectric permittivity $κ$ of these dielectrics is typically associated with a reduced dipole density, either intrinsically due to their composition or by decreasing physical density, such as through the introduction of porosity. This can have a pronounced impact on time-dependent dielectric breakdown behavior, as it is well-established that Cu readily detaches and diffuses in such dielectrics, leading to rapid dielectric breakdown. As a result, Cu interconnects require the use of refractory barrier layers between the dielectric and the Cu metallization to prevent Cu detachment and drift into the dielectric. In general, amorphous barrier materials are preferred over polycrystalline counterparts, as grain boundaries can act as diffusion pathways. Currently, TaN is employed as the primary barrier material, with the potential for being scaled down to thickness around 1–1.5 nm without compromising functionality.^119,120 Ongoing research has explored alternative barrier materials, such as Zn-doped Ru,¹²¹ though their integration poses challenges and is not expected to yield significant improvements over TaN barriers.

Beyond intrinsic material properties, process limitations and dimensional scaling can further compromise time-dependent dielectric breakdown behavior. Factors, such as narrow gaps, line-edge roughness, plasma-induced damage, and misalignment (see Fig. 8), can all contribute to dielectric degradation. Therefore, selecting a suitable alternative metal for advanced interconnects should not only be based on its intrinsic properties (such as the metal detachment barrier) but also on its compatibility with integration processes, as the introduction of new materials can exacerbate dielectric breakdown. It is, thus, crucial to experimentally evaluate time-dependent dielectric breakdown performance using appropriate test structures, such as planar capacitors (PCAPS)¹²² or sidewall capacitors (SWCAPS),¹²³ to facilitate the downselection of promising alternative metals.

Accelerated time-dependent dielectric breakdown testing can also provide insights into the underlying failure mechanisms, such as whether breakdown occurs via dielectric failure or through the formation of metal filaments. Typical bias-temperature stress experiments employ PCAPs or SWCAPs at elevated temperatures, using methods, such as triangular voltage sweeps or the application of constant voltage (see Fig. 10). For capacitors with different electrodes—one consisting of the metal of interest and the other of a refractory metal—metal drift can be identified and distinguished from intrinsic breakdown by comparing results under positive and negative bias. For instance, under positive voltage stress applied to the weak top electrode in a PCAP [Fig. 10(a)], and in the absence of an effective diffusion barrier, metal ions will drift into the dielectric [Fig. 10(b)]. In contrast, no metal drift is observed under negative voltage stress [Fig. 10(c)]. This allows for the differentiation between the metal drift and intrinsic dielectric breakdown mechanisms, as the latter are not dependent on bias polarity [Figs. 10(d) and 10(e)].

Alternatively, during triangular voltage sweeps, metal drift can be detected when the leakage current increases during the initial sweep but disappears in subsequent sweeps, indicating that metal ions have migrated through the dielectric [Figs. 10(f)–10(i)]. Time-dependent dielectric breakdown measurements conducted at various temperatures and voltages enable the study of conditions associated with intrinsic breakdown, metal filament growth, and filament formation.¹³¹ Given that these mechanisms are influenced by the metal, the dielectric material, and their respective thicknesses, it is crucial to continuously refine testing methodologies for alternative metals and advanced interconnects.

From a dielectric breakdown perspective, the primary limitation in scaling Cu interconnects is the requirement for barrier layers to prevent metal detachment and drift into the surrounding dielectrics. As interconnect dimensions shrink, these barriers—having significantly higher resistance than Cu—occupy a substantial fraction of the interconnect volume, which ultimately impedes effective metal fill at ultrasmall dimensions. As discussed further in Sec. V, this results particularly in a sharp increase in line resistance for interconnects with widths below 10 nm, necessitating the adoption of barrierless alternative metallization strategies.

Electromigration (EM) is a well-documented main failure mechanism in integrated circuits. When an electric current flows through a conductor, the metal atoms are subjected to two opposing forces: the direct force exerted by the electric field and the force arising from a momentum transfer (the “electron wind”) from the moving electrons [see Fig. 11(a)].

Over time, the electron wind can induce metal atoms to migrate in the direction of electron flow, from the cathode to the anode. This migration results in metal atom depletion at the cathode, leading to the formation of voids [Figs. 11(b) and 11(c)] and ultimately causing open circuits. Conversely, metal atoms accumulate at the anode, promoting hillock formation [Fig. 11(b)] and potentially leading to short circuits.¹³² 

In a metal line, atoms can diffuse through various pathways: within the bulk of the line, along grain boundaries, and at the interface between the metal and the dielectric. The predominant diffusion path is material-dependent and is determined by its activation energy $E A$⁠, which, in turn, is governed by the bonding energy of the crystal metal lattice. In Cu interconnects, voids arising from electromigration typically nucleate at the top interface between Cu and the dielectric barrier (typically SiN or SiCN), and void growth subsequently proceeds through grain boundaries.^136–139 

One of the critical challenges of downscaling interconnect dimensions is the rapid increase in the relative volume of atoms diffusing along interfaces and grain boundaries, coupled with a decrease in the overall metal volume. This combination leads to a pronounced degradation in the electromigration lifetime of scaled Cu interconnects.^140,141 As a result, the maximum current densities that can be carried reliably (with a 10-year lifetime at 135  $°$C) steadily decrease in scaled interconnects, imposing increasingly stringent constraints on circuit design and layout.

The reduction in electromigration lifetimes for scaled interconnects has been mitigated (slowed) by the introduction of liner layers between TaN barriers and Cu conductors, particularly at the top interface of the line. Co has been the primary liner material in recent technology nodes, with Ru/Co bilayer liners emerging. However, similar to the TaN barrier, which prevents Cu drift into surrounding dielectrics, the thickness of liner layers poses significant challenges for scaling.^119,120,142 Prefill techniques offer a potential alternative to improve reliability, although they introduce additional process complexities.^143,144 Analogous to the TaN diffusion barriers, liners contribute minimally to the overall line conductance while occupying an increasing fraction of the line volume. This reduces the available space for the primary conductor (i.e., Cu), leading to a sharp rise in line resistance as interconnect dimensions are scaled down.

An alternative approach to liner scaling is the use of conductor metals with intrinsically high resistance to electromigration, offering significantly better electromigration performance than Cu. Since the activation energy $E A$ for electromigration generally scales with the cohesive energy of the metal, refractory metals with high melting points present a promising solution. It is noteworthy that metals with high cohesive energies are also advantageous for barrierless dielectric reliability, suggesting that the material properties influencing the different reliability aspects are related. The critical importance of selecting alternative metals with high potential for barrier- and liner-free, reliable metallization schemes is further explored in Sec. V.

As previously discussed, the reliability of metal interconnects is heavily influenced by the absolute temperature at critical points within the interconnect structure, as well as the temperature gradients present throughout the metal stack. The temperature in the interconnect is determined by several factors: the thermal resistance of the interconnect structure, the thermal coupling between the interconnects and the heat-generating transistors, self-heating within the interconnect, and the thermal interactions between adjacent metal lines.

As interconnect dimensions continue to shrink and low- $κ$ dielectrics are introduced, thermal management becomes increasingly critical. Due to the typically low thermal conductivity of low- $κ$ interlayer dielectrics (as low as 0.3 Wm $− 1$ K $− 1$ for OSG 3.0, an organosilicate glass with a dielectric constant of $κ=3.0$⁠),^145,146 heat dissipation within the interconnect stack predominantly occurs through metal lines and vias and is highly dependent on the thermal conductivity of the metals and their connectivity scheme.¹⁴⁷ The scaling of metal linewidth and thickness leads to a reduction in thermal conductivity, an increase in electrical resistivity (see Sec. II), aggravating self-heating, and an enhanced contribution of barrier thermal resistance.¹⁴⁷ As a result, the interconnect stack exhibits higher thermal resistance, with interconnect thermal resistance becoming the dominant factor in overall thermal resistance for advanced packages, leading to increased self-heating of the metal interconnects.¹⁴⁸ 

Given that the thermal behavior of interconnect structures is primarily governed by the metallization, accurately predicting the thermal properties of alternative metals is crucial. Interconnect-level thermal models^149,150 can account for factors, such as the metal line density, the via density, and the connectivity between various metal layers. However, these models must also incorporate the size-dependent behavior of the materials to provide a comprehensive understanding of thermal performance.

To account for the influence of reduced metal dimensions on thermal conductivity, a thin-film model based on the Mayadas–Shatzkes framework⁴⁸ (see Sec. II A 1) has been employed to estimate the size-dependent thermal conductivity for various metals (or metal stacks). Experimentally calibrated reflection coefficients and surface specularity parameters (see Sec. IV) were used. This model allows for the separation of phonon and electron contributions to total thermal conductivity.

As shown in Fig. 12(a), phonon contributions remain below 15% for relevant interconnect dimensions, indicating electron-dominated thermal transport and (approximate) applicability of the Wiedemann–Franz law. Figure 12(b) illustrates the thickness dependence of the thermal conductivity for several metals. Size-dependent thermal conductivity behavior is influenced by an electron mean free path, grain boundary scattering, and surface scattering characteristics.^153,154 The extent to which the Lorenz number is modified in nanoscale metal films and wires is an ongoing area of research. While theory and experiments suggest a possible reduction from bulk values, conclusive evidence is still lacking.^155–159 

Due to the complexity and high cost associated with fabricating nanoscale interconnect lines at target dimensions, direct experimental identification of the most auspicious metals among numerous candidates is impractical. Therefore, a simplified procedure needs to be devised to identify and select the most promising candidates based on easily measurable parameters for a wide range of materials. While the specific set of criteria may vary, recent approaches have focused on both nanoscale metal resistivity and reliability.^24,160,161 Further insights into candidate metal properties can be gained through thin-film experiments, which can serve as initial approximations of expected line performance, following the workflow in Fig. 3. Sections IV A–IV D discuss the current state of understanding for elemental, binary, and ternary metals based on this workflow.

Considering the discussions in Secs. II and III, the following three material properties have been identified as representative indicators of the overall performance of metals in scaled interconnects.

• the bulk resistivity, $ρ 0$⁠;

• the mean free path of the charge carriers $λ$ or, alternatively, the product of the bulk resistivity and the mean free path of the charge carriers, $ρ 0×λ$⁠; and

• the cohesive energy or, alternatively, the melting temperature.

The first two indicators represent the potential for low resistivity at small dimensions, as discussed in Sec. II. The third parameter can be considered an indicator for electromigration resistance and barrierless reliability, as more refractory metals generally exhibit better performance (see Sec. III).

Values for the first indicator (i) can be found in the literature. While ab initio calculations of $ρ 0$ are feasible, they are computationally intensive and unsuitable for screening a large number of metals. Similarly, calculating the mean free path $λ$ is resource-intensive. However, the product $ρ 0×λ$ (or the related transport tensor components) can be obtained relatively easily from ab initio calculations, as explained in Sec. II C. The third proxy can be either obtained from the literature (melting point) or calculated (cohesive energy). A strong correlation between melting points and cohesive energies has been observed [Fig. 13(a)], justifying their interchangeable use.^160,161

In practice, the product of bulk resistivity and mean free path, $ρ 0×λ$⁠, has been preferred as a figure of merit for metals. However, it is essential to consider parameter (i), the bulk resistivity $ρ 0$⁠, in conjunction with $ρ 0×λ$⁠. While this is straightforward for elemental metals, it can be challenging for binary and ternary metals due to limited knowledge of their fundamental properties.

The primary limitation of using the $ρ 0×λ$ figure of merit alone is the inherent correlation between $ρ 0$ and $λ$⁠: short mean free paths (short relaxation times) lead to high resistivities, as evident from Eq. (3). Figure 13(b) demonstrates this relationship by plotting the mean free path deduced from the $ρ 0×λ$ product against bulk resistivity $ρ 0$ for various elemental metals. As shown in Fig. 14, a short $λ$ can result in a less pronounced thickness-dependent resistivity compared to Cu, leading to a resistivity crossover at a finite dimension. However, even with a constant $ρ 0×λ$⁠, a lower bulk resistivity $ρ 0$ in an alternative metal is still advantageous, as it typically results in a crossover with Cu resistivity at larger dimensions compared to metals with higher $ρ 0$ (see Fig. 14). While metals with the smallest $λ$ may eventually exhibit the lowest resistivity, the crossover with Cu resistivity might occur at dimensions that are not practical for interconnect applications.

The proposed indicators can be applied to all metallic elements in the periodic table. Using the $ρ 0×λ$ product of Cu (⁠ $ρ 0×λ=6.8× 10 − 16Ω$ m), a bulk resistivity of 10  $μΩ$ cm, and the melting point of Cu (1358 K) as cutoff values, the most promising elemental metals can be identified, as shown in Table II. For reference, the properties of Cu are also included. The list includes several transition metals, among them Pt-group metals, such as Ru, Rh, and Ir.

The limited number of promising elements allows for experimental thin-film studies on all candidates, following the workflow outlined in Fig. 3. Figure 15 illustrates the thickness-dependent resistivity of various elemental metal thin films. As expected due to its long mean free path, Cu exhibits a rapid increase in resistivity with decreasing thickness, particularly below 10 nm. In contrast, many alternative elemental metals demonstrate a much less pronounced increase, resulting in comparable or even lower thin-film resistivities at thicknesses below 5–10 nm, depending on the metal. Notably, several Pt-group metals, including Rh, Ir, and Ru, exhibit low resistivities, making them promising candidates for future interconnect applications. Resistivity modeling⁷⁰ has confirmed that the weaker film thickness dependence and ultimately lower thin-film resistance compared to Cu can indeed be attributed to shorter mean free paths.

Another promising metal candidate is Mo,^{24,31,69,101,165} which, despite exhibiting slightly higher thin-film resistivity, offers several advantages for interconnect integration and is significantly more cost-effective than the expensive Pt-group metals. Consequently, Mo has emerged as a potential candidate for both logic and memory interconnects.^{101,166–168}

A metal-spacer-defined metal-etch short-loop vehicle, developed at imec, has provided additional insights into the resistivity of ultrasmall nanowires and expected line resistance scaling. This vehicle enables the fabrication of nanowires with cross-sectional areas below 100 nm $2$⁠.^169–172 The results in Fig. 16 demonstrate that Ir interconnects exhibit superior resistivity scaling compared to state-of-the-art Cu damascene interconnects, while Ru and Co (to a lesser extent) show similar resistivities for sufficiently narrow lines. These results confirm the potential of these materials as alternatives to Cu for interconnect metallization. It is noteworthy that, despite comparable resistivities, Ru can offer significantly better line resistance than Cu when integrated without barriers and liners due to its larger conducting volume. This aspect will be discussed further in Sec. V.

Beyond thin-film and short-loop nanowire resistivity evaluations, selected alternative metals have been integrated into scaled interconnect lines to assess their line resistance scalability as well as their reliability, particularly with regard to the need for barrier layers. Specific results are now available for Co, Ru, and Mo.

Co metallization has been the subject of extensive recent research and has been integrated into commercial high-volume circuit manufacturing.^174–176 However, Co migrates into surrounding low- $κ$ dielectrics, requiring a barrier layer (typically TiN) analogous to Cu.¹⁷⁶ In advanced technology nodes with ultrathin low- $κ$ films, maintaining hydrophobic interfaces and continuous thick barriers are, however, crucial to prevent metal drift, posing significant challenges to the integration and scalability of Co metallization in advanced interconnects.^177,178

In contrast to Co, Mo has emerged as a promising candidate for barrierless integration, eliminating the need for an adhesion layer or diffusion barrier on SiO $2$⁠, low- $κ$ organosilicate glasses, or SiCO dielectric films. This finding has been corroborated by multiple studies.^179,180

Ru is another potential barrierless alternative to Cu. Its high cohesive energy and excellent oxidation resistance allow for barrierless integration, although a thin adhesion-promoting layer might be necessary. However, this adhesion layer (typically TiN) can be scaled down to a few Å, well below the minimum thickness required for functional diffusion barriers.¹⁸¹ Further research has confirmed that the reliability of Ru is not compromised when integrated with a 0.3 nm TiN adhesion layer, with no evidence of metal drift. Additionally, Ru combined with dense low- $κ$ dielectrics (⁠ $κ=3.0$⁠) has demonstrated a 10-year lifetime based on damascene time-dependent dielectric breakdown results.^167,182

Both Mo and Ru interconnects exhibit exceptional electromigration performance. As a matter of fact, observing electromigration failures in Mo and Ru interconnects has been challenging due to the extreme temperatures and current densities required.^166,183 Figure 17 illustrates an example of electromigration testing for Mo interconnects, where no failures were observed even after more than 600 h of stressing at 330  $°$C.¹⁶⁶ 

Furthermore, Hu et al.³⁸ demonstrated excellent reliability in 36 nm wide Ru interconnect lines. Additionally, Varela Pedreira et al.¹⁸³ reported unsuccessful attempts to induce electromigration failures in barrierless 21 nm metal pitch Ru interconnects, even at high current densities exceeding 30 MA/cm $2$⁠. In the same study, the authors subjected barrierless Ru lines to even more extreme conditions, driving current densities of 150–200 MA/cm $2$⁠, which resulted in significant self-heating (⁠ $∼$260  $°$C). Only under these extreme conditions, void formation was observed at the grain boundaries and the dielectric interface (Fig. 18).¹⁸⁴ Moreover, Beyne et al.¹⁸⁵ investigated scaled Ru wires with rough surfaces and no barrier using low-frequency noise measurements. Their findings suggest that the metal/dielectric interface serves as the primary diffusion path.

The results of the combined modeling and experimental screening process for elemental metals, following the workflow outlined in Fig. 3, are summarized in Table II. Six elemental metals have emerged as promising candidates for advanced interconnect metallization: the platinum-group metals Rh, Ru, and Ir, along with the transition metals Ni, Co, and Mo. Among these, Co has already been integrated into local interconnects of commercial CMOS technologies.^174–176 Mo and Ru have garnered the most attention for use in highly scaled lines and vias, due to their demonstrated reliability, even in barrierless configurations. Currently, barrierless Ru metallization combined with airgap structures is considered the leading candidate for logic interconnects with sub-20 nm pitches,^{16,18,25,26,186,187} while Mo is also being actively investigated as a viable alternative, particularly for memory applications.^{16,18,166–168}

In addition to conventional metals, graphene has also been proposed as a potential conductor for advanced interconnects.^188–191 Graphene exhibits high carrier mobility and can support large current densities while demonstrating excellent resistance to electromigration.^192,193 However, pristine graphene is a semimetal with a low charge carrier density, resulting in high sheet resistance, which limits its direct applicability in interconnects.¹⁹⁴ To overcome this, multilayer graphene structures and doping are required to reduce resistivity to practical levels.

One effective doping method is intercalation [see Fig. 19(a)], which has demonstrated considerable lowering of thin-film resistivities.^195,196 Notably, FeCl $3$-intercalated graphene has recently achieved resistivity values comparable to, or even lower than, those of Cu.^197–200 The intercalation process preserves the integrity of the graphene Dirac cone while modulating the Fermi level, thereby increasing the charge carrier concentration. Nevertheless, despite the much improved resistivity in doped intercalated graphene, the high contact resistance when co-integrated with metallic vias remains a significant challenge. Future advancements may arise from exploring alternative $n$-type intercalation species,¹⁹⁹ but further research is necessary to demonstrate the successful integration of intercalated multilayer graphene into scaled interconnect architectures.

In addition to intercalated graphene, graphene–metal hybrid composite metallization is another promising approach for interconnects. For instance, studies of Ru thin films capped with multilayer graphene have demonstrated a reduction in both sheet resistance and effective resistivity by approximately 10%–20% compared to uncapped Ru films [see Fig. 19(b)].²⁰¹ This improvement has been attributed to a 0.5 eV reduction in the Fermi level, indicative of $p$-type doping in the graphene layer, likely driven by charge transfer from Ru.²⁰² Similar reductions in sheet and line resistance have been observed in Cu–graphene hybrid metallization schemes as well.^203,204 While many studies have focused on hybrids incorporating single-layer graphene, the use of bilayer or multilayer graphene may yield even greater resistance reductions, although the potential benefits could be limited by charge screening effects and interlayer resistance.

Beyond thin-film studies, the integration of graphene–metal hybrid composite materials presents several challenges. The deposition temperatures required to produce high-quality graphene typically exceed the thermal budget for interconnect processing, which is constrained to around 400  $°$C. Therefore, the development of low-temperature processes for defect-free graphene deposition is essential.²⁰⁵ Moreover, when integrated, e.g., in a metal patterning scheme, graphene should ideally be deposited selectively on the sidewalls of patterned interconnect lines to avoid shorts between adjacent lines. Alternatively, graphene integration within damascene interconnect architectures has also been explored,²⁰⁶ resulting in substantial improvements in electromigration resistance.²⁰⁷ However, further research is needed to validate the performance benefits of such hybrid systems in realistic scaled interconnect structures.

The preceding analysis of elemental metals can be considered exhaustive, encompassing all metals of potential interest. To expand the range of materials of potential interest, recent research has focused increasingly on compound metals. Among binary or ternary metal systems, disordered compounds (alloys) typically exhibit high resistivities due to strong alloy scattering (see Sec. II B). In contrast, numerous ordered intermetallic systems have demonstrated experimentally low resistivities, typically within a specific narrow composition range.¹⁰⁸ 

Figure 6 illustrates a well-known example of the Au–Cu system,¹⁰⁷ which includes the intermetallics AuCu $3$ and AuCu. The figure shows that the resistivities of these intermetallics can be significantly lower than those of random alloys within the same material system and may even approach the resistivities of the constituent elemental metals.

To benchmark and downselect binary intermetallics, the criteria discussed for elemental metals in Sec. IV A can be applied equally. However, a comprehensive benchmarking and downselection process, similar to that conducted for elemental metals, remains beyond reach due to the vast number of potential intermetallic compounds and the limited available data for many of them. Nevertheless, the $ρ 0×λ$ figure of merit can be calculated for selected intermetallics using ab initio methods, as described in Sec. II C. It is important to note that many intermetallics possess non-cubic crystal structures, often requiring tensor formulations. Melting points can generally be found in the literature, such as, e.g., binary phase diagrams, or replaced by calculated cohesive energies when not readily available.

Thus far, ab initio screening studies have identified numerous binary intermetallics with low $ρ 0×λ$ values and cohesive energies exceeding those of Cu (Fig. 20); however, only few surpass Ru. A significant obstacle in evaluating intermetallics is the frequent absence of accurate reported bulk resistivities $ρ 0$⁠. As a result, a downselection process as comprehensive as that for elemental metals is not readily achievable.

Experimental investigations have primarily focused on several aluminide intermetallics due to their low bulk resistivities (below 10  $μΩ$ cm), higher melting points compared to Cu, and notable oxidation resistance.²⁰⁸ Among the most promising candidates are NiAl, AlCu, Al $2$Cu, AlRu, and Al $3$Sc. The properties of these aluminide intermetallics are summarized in Table III and can be directly compared to those of the promising elemental metals listed in Table II. For these aluminides, experimental studies have demonstrated low resistivities,^209,210 although this has predominantly been observed for relatively thick films with thicknesses $≫$10 nm.

Among the most promising aluminide intermetallics, NiAl has emerged as the most extensively studied compound.^{209,211–214} In physical vapor-deposited films on 300 mm Si substrates, a resistivity of 13.9  $μΩ$ cm was achieved at a film thickness of 56 nm after post-deposition annealing at 600  $°$C.²⁰⁹ This resistivity can be further reduced by depositing NiAl at an elevated temperature of 420  $°$C, followed by an in situ Si capping layer to prevent surface oxidation. Under these conditions, a resistivity of 18  $μΩ$ cm was obtained for a 22 nm thick film.²¹³ To achieve even lower resistivities at reduced thicknesses, epitaxial NiAl films on Ge (100) have been explored, resulting in a resistivity as low as 11.5  $μΩ$ cm for a 7.7 nm thick film.²¹⁵ However, integrating such epitaxial layers into scalable and manufacturable interconnects remains a substantial challenge.

AlCu and Al $2$Cu films^{210,212,216–218} with thicknesses around 10 nm have demonstrated resistivities below 20  $μΩ$ cm, and below 10  $μΩ$ cm for films around 30 nm in thickness, after post-deposition annealing at 500  $°$C. The resistivity of Al $2$Cu is lower than that of Ru for film thicknesses of 10 nm and above, while both AlCu and Al $2$Cu outperform Mo across the entire studied thickness range from 5 to 30 nm. Additionally, these compounds exhibit resistivities comparable to TaN/Cu/TaN for thicknesses below 8 nm. Al $2$Cu also displays excellent gap-filling capabilities and promising reliability metrics in time-dependent dielectric breakdown, electromigration, and bias temperature stress tests.²¹⁹ However, further investigation is required to fully validate the potential of AlCu and Al $2$Cu for advanced interconnects with high reliability.

A resistivity of 12.6  $μΩ$ cm has been reported for a 24 nm Al $3$Sc thin film following post-deposition annealing at 500  $°$C.²²⁰ The resistivity was limited by a combination of grain boundary scattering and point defect (alloy) scattering, which presents significant challenges for further improvements. AlRu has also been identified as a potential candidate to replace Cu; however, experimental resistivities for AlRu have remained comparatively high thus far compared to those of the other aluminides discussed here, primarily due to challenges in producing highly ordered films with large grains.²²¹ 

For Cu $2$Mg, a resistivity of 25.5  $μΩ$ cm has been reported for a 5 nm thick film, along with excellent gap-filling performance achieved via sputtering reflow. However, a thick MgO layer is formed within the underlying SiO $2$ due to interfacial reactions between Cu $2$Mg and SiO $2$⁠. This interfacial reaction raises significant concerns regarding the feasibility of integrating Cu $2$Mg into scaled interconnects, where (near-)zero interface formation is essential to achieve low-resistance lines, casting doubt on its suitability for such applications.²²² 

In contrast to elemental metals, binary intermetallics present several additional challenges, including crystalline order and the minimization of point defect densities, precise control of composition and its uniformity, the formation of secondary phases, agglomeration, (interface) reactivity, and nonstoichiometric surface oxidation, as exemplified in Fig. 21. A primary challenge lies in controlling the composition of binary intermetallics, as reported for the Al $1 − x$Ni $x$ and Al $x$Sc $1 − x$ systems.^211,220 As shown in Fig. 22(a), the resistivity of Al $x$Ni $1 − x$ exhibits a pronounced minimum at the stoichiometric composition of Al $0.50$Ni $0.50$⁠. A similar observation for Al $x$Sc $1 − x$ is depicted in Fig. 22(b).

As discussed in Sec. II B, the increase in resistivity can be attributed to the generation of nonstoichiometric substitutional or vacancy point defects, which introduce strong disorder scattering. The experimental findings indicate that compositional control at a level of better than 1 at. % over the entire wafer is essential to achieve low and uniform resistivities, a demanding requirement for high-volume manufacturing. Furthermore, in both cases shown in Fig. 22, low resistivities were only observed after high-temperature post-deposition annealing, likely due to thermally activated ordering (point defect reduction) and grain growth. Consequently, the compatibility of these annealing steps with the thermal budget of the device fabrication process must be carefully evaluated.

As a further illustration of the challenges associated with binary intermetallics, Fig. 23 presents a cross-sectional transmission-electron micrograph and the corresponding energy-dispersive x-ray spectroscopy chemical analysis of an NiAl film after air exposure. The chemical analysis reveals the presence of a native surface oxide, which deviates from the bulk NiAl stoichiometry, exhibiting a composition close to pure Al $2$O $3$⁠.²⁰⁹ This phenomenon can be attributed to element-specific surface processes, specifically metal outdiffusion governing the formation of the native oxide. This can significantly complicate compositional control, particularly for ultrathin films.²²⁵ 

The tendency of forming nonstoichiometric native surface oxides has been observed in various aluminide intermetallics, although the specific oxide compositions may vary depending on the material system.^33,218,220 Therefore, in situ surface passivation techniques may be essential for the successful integration of (aluminide) intermetallics into scaled interconnects, both after deposition and potentially after patterning also.

Beyond binary intermetallics, several ternary compounds have been explored for advanced interconnect metallization. Given the vast combinatorial space of ternary intermetallics and the limited knowledge of their properties, a comprehensive screening approach, akin to that employed for elemental or binary systems, is computationally prohibitive. Consequently, research has, thus far, focused on specific material classes, with particular attention given to MAX phases.^28,226 MAX phases are layered hexagonal carbide or nitride metallic ceramics, described by the generic formula M $n + 1$AX $n$ [Fig. 24(a)], where $1≤n≤3$⁠; M is an early transition metal, A is an A-group element, and X is either C or N.^227–232 

MAX phases typically exhibit significant thermal and electrical conductivities, along with high melting points. Certain MAX compounds, such as Cr $2$AlC and V $2$AlC, demonstrate bulk in-plane resistivities on the order of 10  $μΩ$ cm at room temperature [Fig. 24(b)].²³³ An ab initio screening study has identified low $ρ 0×λ$ products (see Sec. II C) for several MAX phases, confirming their potential for scaled interconnect metallization.²³⁴ 

Another material system of potential interest are metallic delafossite oxides, particularly PdCoO $2$ and PtCoO $2$⁠.²³⁵ These layered hexagonal compounds [see Fig. 24(c)] exhibit ultralow bulk resistivities comparable to that of Al,^235–238 along with exceptionally long mean free paths.²³⁹ Recent experimental studies have reported thin films with thicknesses within the target range for interconnect applications.^240–243 However, further experimental investigation is required to thoroughly assess the scalability and suitability of these delafossite oxides for interconnect line integration.

Ternary compounds, like their binary counterparts, are likely to encounter additional challenges in terms of composition control and processing. Furthermore, both MAX phases and delafossite compounds are highly anisotropic conductors, exhibiting low resistivity in the in-plane directions. While this anisotropy could be advantageous by suppressing surface scattering at top surfaces or interfaces (see Sec. II A 3),^104,105 achieving the desired crystallographic orientation becomes critical. Specifically, fully (001)-textured films without misoriented grains must be realized to harness these properties. Therefore, extensive experimental validation is still required to confirm the viability of these ternary metals for interconnect applications.

As discussed in Sec. II A 3, anisotropic resistivity and reduced dimensionality can mitigate surface scattering. One-dimensional conductors, in particular, have been proposed as ideal interconnect materials due to their ability to suppress surface scattering at the top, bottom, and sidewalls of interconnect lines.¹⁰⁵ Unlike two-dimensional layered metals (MAX, delafossite oxides), which exhibit low resistivity in two directions but higher resistivity in the perpendicular direction, one-dimensional metals possess a single direction of low resistivity with significantly increased resistivity in the two orthogonal directions.

The suppression of surface scattering in one-dimensional metals can be incorporated into both resistivity simulations⁷² and material benchmarking (see Sec. II D).¹⁰⁵ Similar to the $ρ 0×λ$ tensor introduced in Sec. II C, a figure of merit for nanowires has been defined in Eq. (14) that accounts for the reduction in surface scattering.^72,105 Potential one-dimensional metal candidates include binary hexagonal intermetallics (e.g., CoSn, OsRu), orthorhombic intermetallics (e.g., VPt $2$⁠, MoNi $2$⁠), and ternary borides (e.g., YCo $3$B $2$⁠).¹⁰⁵ 

However, it should be noted that no thin-film results have yet unambiguously demonstrated the suppression of surface scattering in such materials. Furthermore, integrating such materials into interconnects will necessitate single crystals with the low resistivity axis aligned with the interconnect wires. Currently, no viable manufacturing pathways exist for producing such interconnects, indicating that significant research and development are still needed to realize the potential of these materials.

Additionally, topological semimetals, which encompass both Weyl and multifold-fermion semimetals, have recently emerged as promising candidates for future interconnect technologies. Weyl semimetals are distinguished by their unique electronic structure, characterized by linear band dispersion, degenerate Weyl nodes, and topologically protected surface states.²⁴⁴ These surface states exhibit high conductivity and are robust against disorder. Examples of Weyl semimetals include TaAs,²⁴⁵ TaP, NbAs,²⁴⁶ MoP,²⁴⁷ and NbP, while CoSi,^248,249 RhSi, and AlPt represent multifold-fermion semimetals.

In the case of CoSi, calculations have shown that the effective resistivity (resistance normalized by the cross-sectional area) decreases as wire dimensions are reduced, even in the presence of grain boundaries, due to the dominance of surface-driven transport channels.²⁵⁰ Experimental evidence for the topological semimetal NbAs suggests that indeed the effective resistivity can decrease as the cross-sectional area decreases,²⁴⁶ although further investigations are required to confirm these findings in interconnect-relevant structures. Similar to one-dimensional metals, topological semimetals will require the fabrication of single-crystal (epitaxial) wires. Furthermore, the reliability of interconnects based on topological semimetals remains uncertain, necessitating further fundamental research to evaluate their viability for scalable interconnect applications.

The resistivity trends presented in Fig. 16 can be leveraged to develop calibrated models for interconnect line resistance, enabling benchmarking against (projected) Cu line resistance values at scaled dimensions. A simplified geometrical model for Ru and Ir interconnects, defined by a width $w$⁠, height $h=w× AR$⁠, and aspect ratio (AR), has recently been introduced based on the data from Fig. 16.²⁸ To project barrierless line resistance as a function of line width $w$⁠, resistivity trends as a function of cross-sectional area were derived from the data for Ru (after post-deposition annealing at 420  $°$C). The Ru metallization scheme also incorporated a 0.3 nm thick adhesion liner.¹⁸¹ For comparison, Cu resistivities were taken from an established line resistance model at an aspect ratio of 2, characteristic for dual damascene interconnects.¹⁷³ 

The projected line resistances for Ru and Cu metallization, considering different combined diffusion barrier and liner thicknesses, are shown in Fig. 25 for aspect ratios of 3 [Fig. 25(a)] and 5 [Fig. 25(b)]. The data demonstrate a significant potential for lower line resistances with Ru interconnects compared to Cu, even with scaled barrier and liner layers, particularly at higher aspect ratios. For instance, the model suggests that Ru interconnect lines could achieve a threefold reduction in line resistance over Cu when the total barrier and liner thickness is 2 nm, with a linewidth of $w=8$ nm and an aspect ratio of 3.

Moreover, these resistance models can provide insights into the mechanisms driving the crossover in line resistance between Cu- and Ru-based interconnects. A quantitative comparison of Ru and Cu resistivities (see Fig. 16) indicates that the scaling advantage of Ru does not arise from a lower resistivity but from the increased conductor volume when the barrier and liner layers required for Cu are replaced by a much thinner adhesion layer. Nevertheless, resistivity scaling remains a crucial factor as high resistivities at low dimensions due to poor resistivity scaling can negate the potential benefits of increased conductor volume. Therefore, barrierless metallization and favorable resistivity scaling must complement each other to realize low line resistances in scaled interconnects.

A second factor contributing to reduced line resistance is an increased aspect ratio.¹⁶ While the aspect ratio is not an intrinsic material property, it is strongly influenced by the integration process. Conventional dual-damascene Cu interconnects (Fig. 2) are limited to aspect ratios of 2 to 3 due to the challenges of Cu filling. However, alternative process schemes, such as semidamascene integration (Fig. 26), can enable higher aspect ratios by combining damascene via filling with direct metal etching. While Cu etching of scaled high-aspect-ratio lines remains difficult, Ru and Mo are much better suited for reactive-ion etching (see Sec. IV C and Table IV). Specifically, Ru lines with aspect ratios up to 6 and metal pitches as small as 18 nm have been demonstrated.²⁵² As shown in Fig. 25(b), increasing the aspect ratio to 5 can result in a fivefold reduction in line resistance for Ru compared to Cu (at an aspect ratio of 2) with a 2 nm barrier/liner thickness and a linewidth of 8 nm. Therefore, the combination of alternative metals with novel integration schemes offers significant potential for reducing line resistance in scaled interconnects.

Integrating alternative metals into scaled interconnects often requires the development of novel unit processes and metallization modules within the final stages of the alternative metal workflow depicted in Fig. 3. While a comprehensive review of available process technologies, their maturity, and their limitations is beyond the scope of this Tutorial, we will introduce several topics that become increasingly critical in the development of scaled interconnect line manufacturing. This section will conclude with a brief evaluation of the current maturity of key unit processes for selected alternative metals.

A fundamental property of interconnect metallization is its adhesion to surrounding low- $κ$ dielectrics. Metal–dielectric interfaces often exhibit weaker adhesion compared to metal–metal or dielectric–dielectric interfaces, potentially leading to metal film delamination and catastrophic failure. While deposition conditions impact adhesion, it can be considered a material-dependent property. Noble metals generally exhibit weaker adhesion to dielectrics than base metals due to weaker interfacial bonding. High-quality graphene also suffers from poor adhesion due to weak van der Waals interactions with surrounding dielectrics or metals.

Adhesion can be enhanced by incorporating adhesion liners between the main metal (e.g., a noble metal) and the surrounding dielectrics. However, like diffusion barriers, adhesion liners occupy interconnect volume and typically contribute minimally to conductance. Therefore, minimizing their thickness is crucial. Experimental studies have demonstrated that base metals, such as Mo, exhibit strong adhesion to common dielectrics.¹⁰¹ This allows for Mo metallization without the need for additional barriers or liners.

In contrast, the more noble metal Ru requires an adhesion liner (e.g., TiN or TaN) due to its weaker adhesion to dielectrics. Nevertheless, studies have shown that the liner thickness can be reduced to as little as 0.3 nm without compromising its effectiveness.¹⁸¹ This suggests that even non-continuous films can function as adhesion liners and may be more scalable than diffusion barriers. Even more noble metals, such as Ir and Rh, however, require further investigation to ensure adequate adhesion and prevent delamination.

Delamination can be exacerbated by high built-in stress within the metallization stack, further weakening the interface between metals and dielectrics. Additionally, the combination of high compressive stress and capillary forces during filling can lead to nanostructure deformation, such as line wiggling.²⁵³ Stress is not an intrinsic material property but is mainly determined by the deposition method. Physical vapor deposited films often exhibit high (tensile) stress after deposition, which is typically generated during island coalescence at the initial stages of nucleation and growth. However, the overall stress behavior can be complex, in particular during thermal cycling.^{83,84,254–257}

For instance, as-deposited PVD Mo films have been observed to have built-in tensile stress as high as 1500 MPa depending on the film thickness.¹⁰¹ Post-deposition annealing and associated grain growth can significantly modify stress, even leading to compressive stress after cooling within certain temperature ranges.^101,258 While stress management is primarily a topic for deposition process development, it is particularly critical for metals with inherently weak adhesion.

During interconnect patterning, certain metal surfaces may be exposed to air or other reactive environments, making chemical inertness, particularly oxidation resistance, a critical consideration. Even self-limiting surface oxidation processes result in the formation of native oxide layers, typically around 2 nm thick, consuming approximately 1 nm of metal.¹⁰¹ For scaled metal lines with dimensions on the order of 10 nm, surface oxidation must, therefore, be avoided. Noble metals are inherently more chemically inert than base metals and, thus, offer greater resistance to oxidation. While this also leads to weaker adhesion, it renders noble metals more compatible with interconnect process flows.

For compound metals, the situation is even more complex. As discussed in Sec. IV C for NiAl (see Fig. 23), surface oxides of binary metals can be nonstoichiometric, leading to compositional changes in the region immediately beneath the surface oxide.^209,220 In such material systems, controlling the composition of scaled interconnect lines is extremely challenging, and surface oxidation must, thus, be strictly avoided. While in situ patterning and passivation or capping can potentially address these issues, they introduce significant process complexity and should be carefully considered during metal selection.

As mentioned above, a comprehensive review of the state-of-the-art process technology for Cu and alternative metal integration is beyond the scope of this Tutorial. However, from a general perspective, both dual-damascene (Fig. 2) and semidamascene integration routes (Fig. 26) require critical unit processes for manufacturing scaled interconnects. These include metal trench and via filling, typically accomplished through electroplating or chemical vapor deposition. Line definition requires chemical–mechanical polishing (CMP) for dual-damascene and reactive-ion etching (RIE) for semidamascene integration. While Cu is well-suited for dual-damascene integration due to the availability of mature chemical–mechanical polishing processes, its suitability for semidamascene integration is limited by the challenges associated with Cu reactive-ion etching.

For alternative metals, the availability of chemical–mechanical polishing and/or reactive-ion etching processes, in addition to deposition techniques, is, thus, crucial. Ru has demonstrated excellent results with reactive-ion etching, enabling scaled lines with high aspect ratios and precise sidewall control.^187,251,252 However, for many other alternative metals, both chemical–mechanical polishing and reactive-ion etching remain underdeveloped. Rh, for example, offers low resistivity, a high melting point, and potential for high electromigration resistance.²⁶⁰ Adhesion engineering remains, however, a challenge, particularly when minimizing the thickness of adhesion liners to avoid reducing conductor volumes. Rh can be electroplated,²⁶¹ and the filling of sub-40 nm wide lines and vias with high aspect ratios has been demonstrated (Fig. 27).²⁵⁹ Yet, dual-damascene integration requires chemical–mechanical polishing, which is not well-established for Rh and requires aggressive abrasives and oxidizers.²⁵⁹ Moreover, the lack of manufacturable reactive-ion etching processes for Rh hinders semidamascene integration, making it a significant obstacle to realizing the potential of Rh metallization in high-volume manufacturing CMOS circuits.

Table IV provides a summary of the process readiness for selected elemental metals, as well as binary and ternary compounds. The table provides the authors’ assessment of the process maturity for each material as of the time of publication: a “+” indicates a mature process suitable for high-volume manufacturing, an “o” signifies the availability of a risk process, and a “ $−$” denotes a process that is currently at the research stage. The table highlights the intricate and lengthy journey required for the successful integration of alternative metals into manufacturable interconnects. Mo and Ru processes appear to be the most mature ones, making them leading candidates for high-volume manufacturing, as already outlined in Sec. IV. In contrast, many critical process steps are still lacking for other metals.

Traditionally, the selection of alternative interconnect metals has mainly considered technological, physical, and economic factors. However, recognizing the increasing importance of sustainability, this section introduces a streamlined framework for assessing the sustainability of alternative interconnect metals. This framework incorporates seven sustainability aspects (SAs) and evaluates examples of selected current and emerging interconnect metals (Cu, Al, Ni, Ru, Co, Mo, Ir, Rh). To avoid shifting environmental burdens, a life cycle approach is essential, requiring consideration of the integration method for alternative interconnect metals. Understanding material and energy flows during integration is crucial for assessing overall sustainability. While processes with fewer steps may reduce environmental impact, energy requirements during integration must also be carefully considered. This section discusses these integration considerations and provides a condensed overview of the sustainability assessment framework detailed in Ref. 262.

The proposed sustainability assessment framework for alternative interconnect metals is categorized into seven sustainability aspects (SAs), each with at least one indicator to quantify its impact. SA1 focuses on supply risk, using the Herfindahl–Hirschman index (HHI) to assess market concentration.^263,264 The Herfindahl–Hirschman index values in Table V were extracted from Refs. 265 and 266. SA2 addresses criticality and conflict, considering metals listed as critical raw materials (CRMs) in the US²⁶⁷ and EU,²⁶⁸ as well as those on the EU conflict mineral list.²⁶⁹ SA3 evaluates metal circularity within integrated circuit manufacturing processes and acknowledges the challenges of calculating the site material circularity index (CI).²⁷⁰ SA4 assesses climate change impact through global warming potential (GWP) values,²⁷¹ while SA5 focuses on water scarcity using the EF 3.1 methodology²⁷² for upstream water use. SA6 examines the impact on natural resources through abiotic resource depletion potential (ADP) values,²⁷³ and SA7 assesses human health impacts using EF 3.1 methodologies, such as “human toxicity cancer and non-cancer” and “particulate matter.” These indicators collectively provide a comprehensive evaluation of the sustainability of alternative interconnect metals. For more detailed information on each SA and its associated indicator(s), please refer to Ref. 262.

Table V provides a summary of the sustainability performance of the examined interconnect metals, presenting a nuanced perspective on the seven proposed indicators. The sustainability impacts (SA4–SA7 in Table V) are calculated based on the cradle-to-gate impact to produce 1 cm $3$ of metal. This calculation assumes that the volume of the final deposited layer of an interconnect metal is independent of the metal. However, the volume ratio required to achieve the desired final volume deposited should be considered.