Design of SRAM cell using an optimized D-latch in quantum-dot cellular automata (QCA) technology

Over the last few decades, the complementary metal–oxide semiconductor (CMOS) has influenced the application of digital circuits. CMOS transistors have become smaller in size, reaching the nanoscale due to increasing demand.¹ However, this scaling has led to multiple issues, such as power consumption, scaling limits, heat dissipation, less switching speed, interconnect delay, rising manufacturing cost, higher area, and high clock cycle delay, which can impact its overall performance and reliability. Therefore, the search for a viable alternative for this technology has increased. As a result, a wide range of technologies have been studied, including quantum-dot cellular automata (QCA), single electron transistors (SETs), and carbon nanotube field effect transistors (CNTFETs). From all of the technologies mentioned, quantum-dot cellular automata (QCA) provide a potential future substitute over CMOS technology.² By implementing this cutting-edge nanotechnology technique, we can significantly minimize power consumption as it eliminates current flow within the circuit. This makes it an incredibly attractive option for anyone looking to reduce the footprint area and energy usage.³ The technology behind QCA is based on quantum dots instead of transistors, which allows for a significantly greater density of logic units. Because they do not have the same physical constraints as CMOS, QCA circuits are, therefore, a better option for sustaining the scaling trend. In QCA, information spreads by polarization shifts rather than electrical impulses, reducing the delays brought on by the RC interconnects in CMOS. QCA functions at the nanoscale by nature, overcoming the constraints CMOS encounters as it gets closer to the atomic size. QCA is still in its early phases of development, providing chances for advances in computation models, design topologies, and manufacturing processes, in contrast to CMOS, which is approaching its physical constraints. QCA technology has been utilized by many researchers to create their designs due to its low power consumption, fast speed, compact area, and small dimensions.⁴ Digital circuits must operate at low power to produce more energy-efficient devices, which is crucial for battery-operated systems, such as laptops, smartphones, and IoT devices. By extending the battery life and decreasing the need for frequent recharging, efficient power utilization enhances user experience. Devices with lower power consumption can be more compact, light, and wearable while maintaining excellent performance. Power optimization is not only important for performance but also cost, sustainability, and user experience.^5,6

Among the electronic circuits most frequently used in processors and digital components are latches. The above-mentioned circuits are extensively utilized in the memory structure and even in the building of shift registers, flip-flops, and counters.⁷ A fundamental idea in low-power and quantum computing is reversible logic, which has important ramifications for QCA technology. Since the input can be uniquely retrieved from the output thanks to reversible logic gates, no information is lost during computing, which theoretically lowers energy dissipation to almost zero. The common reversible logic gates are the Feynman gate (CNOT gate), the Fredkin gate, and the Toffoli gate.⁸ The novel full adder, the full subtractor, the half subtractor, the half adder, and the ripple carry adder were designed using the XOR gate using the QCA technology.^9–11 Additionally, integrating digital signal processing (DSP) with QCA presents promising opportunities for the nanoscale implementation of high-performance, low-power signal processing units. The mathematical operations of filtering, convolution, Fourier transforms, and other operations involving multiplication, addition, and accumulation are largely relied upon in traditional DSP processors. The core of many DSP algorithms is the Multiply-Accumulate (MAC) unit, and the advancement in the MCA unit circuit is explained.^12,13

Considering the significance and uses of the D-latch circuit, D-latch designs were previously created in QCA technology, although with certain limitations. For instance, the suggested design in Ref. 14 has a larger area along with a high number of cell counts. In contrast to Ref. 14, the design suggested in Ref. 15 has a high clock delay while managing to decrease the number of cell counts at a certain level. Moreover, contrasted to the prior designs, the design suggested in Ref. 16 had a reasonably decent improvement that significantly lowers the number of cell counts, the layout area, and latency compared to the two former research works, but this problem persisted with excessive consumption of power. Despite having a large area and the number of cell counts, the D-latch design with a reset pin that was developed in Ref. 17 was able to effectively regulate the clock delay. All the earlier versions generally had issues with either an issue with the cell counts, the clock delay, or the area of the circuit.

The most important and basic random access memory (RAM) device is the static random access memory (SRAM). It is used in both microcontrollers and microprocessors and is quick and reliable. The need for higher-density, higher-speed SRAM cells as well as larger, more efficient microprocessors has risen due to the expansion of transistors. In today's world, where power efficiency and high-density applications are becoming increasingly important, the need for designing effective SRAMs cannot be overemphasized. It is pivotal to develop SRAM cells that are tailored to meet the growing demands of less power and less area applications, which are essential for ensuring optimal performance.

When comparing the SRAM cell to the D-latch, it can be seen that D-latches are more compact, faster, and simpler in QCA designs than SRAM cells, which are slower and more complex because of the extra circuitry required for data retention. Despite their higher resource needs, SRAM cells are vital for non-volatile storage, which makes them important in memory applications. The QCA area, cell counts, and clock cycle delay (latency) of the SRAM cell are more and more extensive than those of the D-latch.

In this work, an optimized D-latch circuit is proposed. Subsequently, a novel SRAM cell is proposed using the optimized D-latch, which has a smaller area, lower latency, and fewer cell counts compared to previously proposed SRAM designs. The D-latch and SRAM cell circuits are designed using QCA Designer 2.0.3; after that, the overall area, the total number of QCA cells, and the clock cycle delay are calculated. The potential power consumption for both semiconductor and molecular QCA for the SRAM cell circuit was then evaluated using QCA Designer-E.

The remaining part of the paper is arranged into six sections: The fundamental design and operation of the QCA cell are explained in Sec. II, along with an explanation of the primary gates and clocking operations of the QCA. Section III explains the existing QCA D-latch circuits with the problem of the same circuits. Section IV explains the recent work on QCA-based SRAM cells and the challenges faced by the same circuits. In Sec. V, the proposed optimized QCA-based D-latch and the SRAM cell are explained. Section VI shows the simulation results of the proposed circuits and the comparison with the existing circuits based on the number of cell counts, the QCA layout area, the clock delay, and the QCA cost. In the end, Sec. VII provides a conclusion and future work of the research.

A QCA cell's logic state is immediately affected by its neighboring QCA cell. QCA cells can, therefore, be arranged in many ways to convey the reason for their arrangement. One way to build a QCA wire is to arrange QCA cells in a single line. Electromagnetic exchanges can convey information in a binary form between QCA cells under this circumstance. The data are continuous in a 45° wire and continuous in a 90° wire due to the Coulomb repulsion force. The transfer of data in a 90° wire is demonstrated in Fig. 2(a), while the transfer of data in a 45° wire is demonstrated in Fig. 2(b). Two layers can be used in QCA design, which are coplanar and multilayer.²¹ 

A logic inverter can be created through a collective interaction among the cells. All you need to do to design a basic inverter is arrange two cells diagonally. Observations reveal that electrons are deposited in quantum dots by interaction with the cell's corners, which results in a change in electrostatic interactions. Figure 4 shows the two possible designs for an inverter. In Fig. 4(a), the design is simple, but the output may only sometimes be accurate; in Fig. 4(b), the design is more complex, but the output is more accurate.^23,24

By utilizing the clock stage approach, QCA technology can efficiently operate the circuit and effectively manage information transfer through a wired connection. This approach ensures that data are transmitted accurately and promptly, making it an essential element in the overall performance of the QCA technology. QCA cells in a clock stage maintain certain polarity because of the addition of this technique.^25,26 There are four phases in the one-clock delay: switch (zone 0), hold (zone 1), release (zone 2), and relax (zone 3). There is a 90° phase variation between each clock cycle delay. During the switch phase (zone 0), the cell's available electron energy boundary increases to the point that neighboring cells can alter the polarity of the cell, ultimately leading to the QCA cell achieving its ultimate binary data. The hold phase (zone 1) is characterized by an increase in the internal point energy to such an extent that the QCA cell maintains its polarity and electrons do not interact with those of its neighboring cells. The energy of the cell's interior points diminishes throughout the release phase (zone 2) to the point when the cell loses its charge. A cell has no impact on its surrounding cells and lacks inner point energy during the relax phase (zone 3).²⁷ The QCA tool displays four distinct clock stages, each with a unique color as seen in Fig. 5.

D-latch is a basic circuit to design an SRAM cell. The D-latch circuit can be created in two ways: the traditional way is shown in Fig. 6 and another using a 2 × 1 multiplexer, which is used in our circuit [shown in Fig. 7(a)]. Designing a D-latch using a multiplexer is easier and simpler in QCA technology as compared to the traditional method. Many researchers have developed a D-latch circuit using a multiplexer in QCA technology using different methods.^28–31 

The D-latch circuit presented in Ref. 28 uses 35 QCA cells, has a one-clock cycle delay, and occupies 0.04 μm² of the QCA layout area. This D-latch is built using two 3-input majority gates (3MG), one 5-input majority gate (5MG), and an inverter gate. This circuit design uses misalignment of the block. The problem with the circuit is that it requires a high number of QCA cell counts, a high clock cycle delay, and a larger area, and due to all of this, the QCA cost function also increases.

The D-latch circuit presented in Ref. 29 needed 24 QCA cells, has a 1 clock cycle delay, and occupies 0.02 μm² of the QCA layout area. This D-latch is built using 3 three-input majority gates (3MG) and an inverter gate. It is better than the one in Ref. 28 in all characteristics, but still, it has a high number of QCA cell counts, a high clock cycle delay, and a larger area, and due to these, the QCA cost function also increases.

The D-latch circuit presented in Ref. 30 is built using 23 QCA cells, has a 0.5 clock cycle delay, and occupies 0.02 μm² of the QCA layout area. This D-latch is also built with the same number of gates in Ref. 29. It is better in terms of the clock cycle delay of the above-mentioned D-latch circuits. Due to better clock cycle delay, both QCA cost functions are also decreased.

The D-latch circuit presented in Ref. 31 involves 19 QCA cells, has a 0.75 clock cycle delay, and occupies 0.01 μm² of the QCA layout area. This D-latch circuit design is like the one in Ref. 29. It also required 3 three-input majority gates (3MG) and an inverter gate. It is superior to all the above-mentioned D-latch circuits in all the characteristics except the QCA cost function through Eq. (5) because it requires more numbers in the gate counts.

Earlier published papers have several problems, including high QCA cell counts, a large QCA area, an increased clock cycle delay, and gate counts. These designs incorporated more complex and expensive circuits. In terms of cell counts, clock delay, circuit area, and QCA cost function, our novel optimized QCA D-latch circuit in this paper is superior. Table I shows the comparison between the previously published QCA D-latch circuits.

Line-based memory cells³² and loop-based memory cells are the two varieties of QCA-based memory cells. Loop-based memory uses a QCA cell loop with a four-zone clock signal to store the previous value.³³ On the other hand, the prior value is sent in and out across a QCA line to be stored in line-based memory. Due to the need for an additional clock area for data bit travel, line-based memory implementation becomes more challenging. Implementing line-based memory gets more difficult since more clock regions are required for data bit transit. Researchers have developed SRAM cell circuits in QCA technology using a variety of techniques, including majority voter, multiplier, and SR latching device cells.^34–39 

In Ref. 40, an SRAM cell is described that uses four 3-input majority gates and one 5-input majority gate with the four-line driver. The SRAM cell has achieved low energy consumption, high efficiency, and a simple design, but the problem with the circuit is that it requires more counts of cell numbers. In Ref. 41, the first design of the SRAM cell circuit was introduced in QCA. Its overall performance is better and easy to extend, but the problem with this is that it requires just 158 cell counts, has a 2-clock cycle delay, and occupies 0.16 μm² of QCA SRAM cell size. Due to this, the overall cost is also increased.

Maximizing the efficiency of the QCA SRAM cell circuit is crucial for enhancing the overall performance of digital circuits. The use of a 2 × 1 multiplexer with a three-input and five-input majority gate is a proven technique to achieve this goal.⁴² This design was superior to the SR and D-latch-based SRAM cell in terms of the number of counts of cells, overall size, and clock delay. However, the disadvantage of this circuit is that to achieve good performance, it requires more QCA cell numbers, an increase in the area, and high clock delay, and due to these, the QCA cost increases. One more disadvantage of this circuit is that it consumes high power for semiconductor and molecular QCA as seen in Table VI.

Another QCA SRAM cell circuit suggested has a RESET/SET function with a 0.08 μm² QCA SRAM cell size, a 1.5 clock cycle delay, and 88 QCA cell counts.⁴³ Additionally, the number of QCA cell counts, QCA cost II (A × T²), and SRAM cell size are high. The design's additional disadvantage is its high power requirement in both molecular and semiconductor QCA.

Another D-latch-based QCA SRAM cell circuit was offered in Ref. 37. They displayed two QCA designs, the most effective of which is based on the number of counts of cells. The second design required 63 cells and a 1-clock cycle delay, while the first design required 100 QCA cells and 2 clock cycles. However, it has the advantage that it requires only one clock cycle, and due to this, its QCA cost II (A × T²) is less.

In Ref. 38, an SRAM cell circuit with a 0.06 μm² QCA SRAM cell size and 55 cell counts were suggested. This design has higher power utilization, and also, it needs 2.5 clock cycles to operate. This SRAM cell circuit is built using a loops-based method. An additional loop-based SRAM cell circuit in Ref. 39 requires 52 cell counts, has a 1.5 clock cycle delay, and occupies 0.05 μm² of QCA SRAM cell size. This circuit has a problem that requires a high number of cell counts, a larger area, and a high clock cycle delay with the further disadvantage of the circuit is that it requires more power loss.

The designs incorporated more complex and expensive circuits as a high number of QCA cells, a larger QCA area, a high clock cycle delay, inverters, and a high number of majority gates. Additionally, they use more power usages and have a lower throughput.^{37–39,41–43} Table II shows the comparison between the previously published QCA SRAM cell circuits.

The proposed optimized D-latch is used to create a SRAM cell, which ultimately decreases the overall number of cell counts, reduces the overall layout area, and a lesser clock delay than the earlier proposed circuit.

The traditional D-latch design is seen in Fig. 6.⁴⁴ Due to its intricacy, this design is generally hard to execute in QCA. The D-latch can be implemented without difficulty in QCA by connecting feedback from the output cell to one of the inputs of a multiplexer. The multiplexer presented in Ref. 45 serves as a basis for the construction of the suggested D-latch. The output of the earlier stage will reach the circuit identically with CLK and D via feedback from the output cell to “0” of MUX with the required clock delay along the feedback path, as illustrated in the standard D-latch circuit of Fig. 7(a). The input is transferred to the output when the clock value equals logical to 1, and when the clock value is equal to 0, the value of output that has been saved by feedback stays constant. Figure 7(b) illustrates the novel D-latch in QCA technology developed using a multiplexer approach. The novel D-latch design only requires a 0.5 clock delay to produce appropriate outputs and only utilizes 18 QCA cell counts in a 0.01 μm² layout area. In the proposed design, all inputs and outputs of a QCA circuit can be externally accessible. Table III illustrates the functionality of a D-latch.

An optimized SRAM cell design is described in this section. A proposed SRAM cell uses one AND gate and one multiplexer as shown in Fig. 8. The proposed circuit design of an SRAM cell is substantially easier than the previously presented ones since they aim to employ the least number of gates acceptable. Table IV presents the QCA SRAM cell's function. It has three input values: Read/Write (R/W), Data (D), Enable (EN), and Output (OUT). The read operation is carried out if Read/Write (R/W) is logic 0. At the read operation, the memory loop is unchanged and the output (OUT) cell value is equal to the saved value in the memory loop if enable is equal to logic 1. The write operation is carried out if Read/Write (R/W) is logic 1. At the write operation, the value of the data (D) input value will be saved in the memory loop of the SRAM cell circuit and the output value will be the same as the data (D) input value if enable is equal to logic 1. In the given SRAM cell, the read/write (R/W) cell is an extremely important input value. Considering that the output value changes depending on the Read/Write (R/W) value. If the enable (EN) input cell is equal to logic 0, then the output cell value will be also equal to logic 0. This condition is known as a hold operation since no read or write operations are carried out at that time. The output (OUT) cell value will be the stored value present in the memory loop only if the enable (EN) input is equal to logic 1.

Figure 9 illustrates the proposed SRAM cell in QCA technology developed using a D-latch create multiplexer and an AND gate. Create an AND gate with any of the 3-input majority gate's inputs set to logic 0. It used a D-latch to write and read the given data value. As long as the enable (EN) input cell is set to logic 1, the value that passes through the D-latch equals the output (OUT) cell value. If the enable (EN) input cell equals 0, then the output (OUT) cell value will be directly equal to logic 0.

Simulation engine coherence vectors and QCA Designer version 2.0.3 are used to simulate the novel D-latch and the SRAM cell. The QCA Designer tool's simulation parameters and conditions are configured using the predefined values. The simulation parameters that were employed are listed in Table V of this research paper. The fixed dimensions of a single QCA cell are 18 × 18 nm² and therein are 5 nm-diameter quantum dots and two electrons free to move as per the Coulomb repulsion force.⁴⁶ The results of the simulation of the proposed D-latch are shown in Fig. 10. Two input values, clock (CLK) and data (D), and one output (OUT) value create a D-latch circuit. If the clock (CLK) is logic 0, the value of the output is the same as the previous value, and if the clock (CLK) is logic 1, the value of data (D) is transferred to the output cell.

Figure 11 shows the results of the simulation for the suggested SRAM cell circuit. In this, a total of three input cells and one output cell is used. If the enable (EN) input cell is equal to logic 0, then the output (OUT) cell is equal to logic 0 and this state is called a hold operation. When the read/write (R/W) cell value is equal to logic 1, then the write operation executes and the data (D) cell value will be stored in the memory loop. Then, the output (Out) cell value is equal to the data (D) cell value if the enable (EN) cell value is equal to logic 1. When the read/write (R/W) input cell value is equal to logic 0, then the read operation executes and the memory loop is unchanged. Then, the output (Out) cell value is equal to the saved value in the memory loop if the enable (EN) input cell value is equal to logic 1.

Table VII shows comparisons of performance between the proposed QCA SRAM cell circuit with the existing QCA SRAM cell circuits. We consider these vital comparison measures, such as the number of QCA SRAM cell counts, the QCA cost, the QCA SRAM cell area, and the clock delay. When compared to the other current QCA SRAM cell circuits,^{34–39,41–43} the proposed QCA SRAM cell circuit indicates significant efficiency improvements in performance. There are 26 QCA cell count numbers, and their QCA area is 0.02 μm². Our design has a 0.75 clock cycle delay. The QCA cost II (A × T²) for our proposed SRAM cell is 0.01125, and the QCA cost calculated through Eq. (5) is equal to 3.

This paper proposed a novel QCA D-latch circuit using 18 QCA cell counts with a 0.01 μm² circuit layout area and with a clock delay of 0.5 clocks. By using the proposed QCA D-latch, a new QCA SRAM cell circuit is proposed, which uses 26 QCA cells and has a 0.02 μm² of an SRAM cell layout area with a clock delay of 0.75. In comparison with the earlier designs, power consumption, area, cell counts, and clock delay are likewise reduced in the proposed circuit of the D-latch and the SRAM cell. Our proposed D-latch is suitable to design using a 2 × 1 multiplier rather a traditional design of a D-latch. The results showed that the SRAM cell, which was proposed in our paper, performed extremely well. Compared to the other existing SRAM cells, our SRAM circuit is more stable and robust. In our simulation results as shown in Fig. 11, it is observed that there is no distortion and there are no glitches compared to the existing designs. The creation of QCA circuits has the potential to completely transform the electronic design in the future by allowing ultra-low power consumption, increased computational density, and nanoscale scaling, opening up options for smaller, more energy-efficient devices. This may result in smaller, more effective electronic devices that push the boundaries of miniaturization and enhance the performance while using less energy. The possible limitations of fabrication techniques for future QCA-based circuits are its fabrication challenges and temperature sensitivity, and due to the quantum nature of QCA, error rates during data transmission or logic operations could be higher than in conventional CMOS circuits, requiring further error-correction mechanisms. This work can be developed in the future to construct an X × Y bit memory array with the lowest achievable clock cycle, a less layout area, and a high switching rate.

The authors have no conflicts to disclose.

Nitesh Kumar Rathore: Conceptualization (equal); Formal analysis (equal); Investigation (equal); Methodology (equal); Software (equal); Validation (equal); Visualization (equal); Writing – original draft (equal). Pooran Singh: Conceptualization (equal); Formal analysis (equal); Investigation (equal); Methodology (equal); Supervision (equal); Validation (equal); Writing – review & editing (equal).

The data that support the findings of this study are available within the article.