Thermoelectric performance of high aspect ratio double-sided silicon nanowire arrays Open Access

The world is facing numerous challenges related to pollution from industrialization and overpopulation along with a growing concern for the impact of greenhouse gas emissions on the environment.¹ Roughly, 50% of primary energy is wasted as heat.² Therefore, there is tremendous interest in waste heat conversion to electricity as a carbon-free source of electricity.² Thermoelectrics (TE) are very promising in converting waste heat to electricity.³ Economic conversion of waste heat is viable at higher temperatures (⁠ $> 150 °$C) due to increased conversion efficiency.

The unique properties of SiNWs, such as compatible fabrications with microelectronics and tunable thermal and electrical conductivities and dimensions, make them ideal for use in micro thermoelectric generators (⁠ $μ$-TEGs).^4,5 These $μ$-TEGs devices can be used in wearable electronics,^6,7 infrastructure monitoring systems,^8,9 biomedical devices,^10,11 and satellite technology,¹² where compact size, efficiency, and the ability to harvest energy from temperature gradients are crucial.

In the field of TE materials, ZT is used as an indicator of their performance. ZT is defined as $S 2 σ T κ$⁠, where S is the Seebeck coefficient, $σ$ is the electrical conductivity, $κ$ is the thermal conductivity, and T is the average absolute temperature. An ideal TE material acts as a “phonon glass electron crystal,” with glass-like low thermal conductivity and crystal-like high electronic properties.¹³ Heavy-element-based TE materials, such as bismuth telluride and Lead(II) telluride, are currently the best performing, but they suffer from cost, toxicity, and scalability limitations operating under 1000 K.¹⁴ In comparison, silicides and oxides are cheap, abundant, and environmentally friendly but suffer from poor TE performance.¹⁵ The lack of TE materials meeting all the necessary requirements has limited the large-scale application of TE devices. The commercial bismuth telluride materials with a ZT of 1 can only work at low temperatures (⁠ $< 200 °$C), while the application of high-temperature-compatible silicon-germanium alloys is limited due to high cost.^16,17 While n-type TE materials such as $AgP b m SbT e 2 + m$⁠, $P b 1 − x S n x Te − PbS$⁠, and $I n 4 S e 3 − σ$ achieved $ZT>1$ under 600–900 K, there is also a gap in the cost-effective p-type TE materials operating under such temperature range using none heavy-element-based materials, which is crucial for improving the efficiency and competitiveness of TE devices.^16,18,19

Silicon nanowires (SiNWs) have been studied extensively as promising TE materials due to their unique electronic and thermal properties.²⁰ It is been more than 10 years since breakthroughs in achieving ZT = 0.6 at room temperature and ZT = 1 at 200 K in p-type SiNWs.^4,5 Recently, we demonstrated that porous single silicon nanowire can achieve 0.71 ZT at 700 K temperatures, which outperforms most other silicon nanostructures.²¹ However, so far, no ZT measurement has been reported on modules made from multiple SiNWs due to enormous fabrication, characterization, and measurement challenges. Lee et al.²² and Elyamny et al.²³ fabricated modules with short SiNWs (10  $μ$m) with an aspect ratio of 10 and 1375, respectively, which is shorter than the long SiNWs (100  $μ$m) with an aspect ratio of 1936 reported in this paper. Lee et al.²² and Elyamny et al.²³ were not able to measure the electrical conductivity and conducted the experiments at lower temperatures.

Fabrication of SiNWs with controlled morphology, size, and doping concentration is critical to achieving high TE performance. However, it is challenging to fabricate uniform and reproducible SiNWs on a large scale.²⁴ The growth of SiNWs can be influenced by several factors, including the substrate, precursor concentration, temperature, and pressure.^25–27 Thus, optimizing the growth parameters for reproducibility and uniformity is critical. In addition, the doping concentration of SiNWs needs to be carefully controlled to achieve optimal TE performance as demonstrated by our previous work.²¹ High doping concentration can lead to an increase in the electrical conductivity but a decrease in the thermal conductivity, while low doping concentration can lead to low electrical conductivity and low thermopower. Characterization of the SiNW array also presents challenges. Measuring the electrical conductivity and thermopower of the SiNWs is complicated by the small size of the wires and contact resistance between the measurement contacts and the wires. Inaccurate measurements of electrical conductivity and thermopower can lead to incorrect values for the ZT. Furthermore, measuring the thermal conductivity of SiNWs is challenging due to the small size and the thermal contact resistance between the wires and the surrounding environment.

In this paper, we report on the first multi-array SiNW-based device with device-level ZT value by overcoming fabrication, characterization, and measurement challenges. Our findings reveal that the enhanced surface-to-volume ratio of the array geometry along with its unique physical properties, resulted in a significantly improved ZT to 0.24 at 700 K for SiNW in TE modules. The high aspect ratio (1936) of the double-sided SiNW array, combined with its non-agglomerated wire tip engineering and Ohmic contact formations, resulted in SiNWs with significantly enhanced TE properties.

For TE device applications, the desired SiNWs arrays should be (1) ultralong SiNWs to minimize bulk Si part (substrate) and to minimize the impact of contact resistances, (2) have controlled morphology and doping concentration to optimize ZT, (3) have materials filled in between for mechanical integrity and electrical insulation, and (4) have vertical alignment to allow all tips contacted by metals on top/bottom to minimize interfacial thermal and electrical resistance.

Figure 1 illustrates the fabrication process for our ultralong SiNW array devices, which have three important features, double-sided structure [Figs. 1(b) and 1(e)], non-agglomeration SiNW tip [Figs. 1(c) and 1(f)], and Ohmic contact formations [Figs. 1(d) and 1(g)]. First, we patterned the Si wafer with Ag and Au on both sides [Fig. 1(a)] using nano-imprint lithography (NIL), as demonstrated in our previous work.²¹ After metal-assisted chemical etching (MACE) and boron (B) post-doping, we have double-sided SiNW arrays with controlled doping concentration [Figs. 1(b) and 1(e)]. The SiNW arrays need to be filled with spin-on-glass (SOG) to achieve mechanical integrity but the drying process of SOG leads to agglomeration of the tips of SiNWs due to the capillary force, which makes it difficult to form metal contact on SiNWs. To overcome this problem, we first wrap around the tip of SiNWs with the chemical vapor deposited (CVD) $Si O 2$ as physical barriers [Figs. 1(c) and 1(f)] to limit potential agglomerations, which increases the metal contact with the SiNW tips from 5% to 40% (areal coverage was calculated with 100% maximum value), as shown in the top-view SEM image in Figs. 1(a) and 1(b) in the supplementary material. After the tip $Si O 2$ deposition and the spin-on-glass (SOG) filling, the SiNW tips are exposed by $Si O 2$ reactive ion etching (RIE), and the resulting silicon nanowires (SiNWs) are globally connected by the SOG $Si O 2$⁠, and locally separated due to the CVD of $Si O 2$ around the tips. Finally, the Ni film is deposited on both sides of the SiNW arrays, followed by the deposition of the Ag paste to form the top and bottom metal contact [Figs. 1(d) and 1(g)]. To form a better Ohmic contact, a rapid thermal annealing process [Figs. 2(h) and 2(i) in the supplementary material] was used to form SiNi or $SiN i 2$⁠,²⁸ improving the contact quality between the SiNW tip and the Ni metal.

In this study, we characterized the SiNW/SOG and the SiNW stack (SiNW/SOG+ bulk Si) part. The stack part includes the bulk Si part which is unavoidable in real device applications, so the characterizations give a realistic prediction of the future TE device using p-type SiNWs. At the same time, the characterizations of SiNW/SOG part demonstrate the potential of using p-type SiNW materials in the TE application with the exceptional ZT value.

This study uses various characterization techniques to investigate the TE properties of the double-sided SiNW arrays. First, the intrinsic thermal conductivity (⁠ $κ$⁠) of the SiNW arrays from room temperature up to 700 K was measured using the $3ω$ method (Fig. 3 in the supplementary material). It should be noted that our SiNW arrays contain two sides of SiNWs and a middle bulk Si part. This unique structure minimizes the presence of undoped Si substrate in the middle, which exhibits electrical conductivity two orders of magnitude lower than that of the SiNW array component. As presented in Fig. 2(a), our measurements revealed that the thermal conductivity of the SiNW stack (SiNW/SOG + bulk Si) (0.671 W/mK at 700 K on average) is higher than that of the SiNW/SOG (0.644 W/mK at 700 K on average), and the thermal conductivity of the SiNW/SOG was consistent with the calculated value based on the single SiNW measurement (0.650 W/mK at 700 K) in our previous work.²¹ Stack $κ$ is higher than SiNW/SOG because bulk Si (⁠ $∼10$–20  $μ$m) has a much higher $κ$ than SiNW/SOG part.

Second, the electrical conductivity (⁠ $σ$⁠) of the SiNW arrays was measured by the FOUR-probe technique (Fig. 4 in the supplementary material). Measurement of electrical conductivity for such geometries has been very challenging in the past due to contact resistance between the probe and the sample.²⁹ We devised a technique to eliminate this contact resistance by stacking multiple units together [Fig. 4(a) in the supplementary material]. Figure 2(b) shows that the SiNW/SOG part has a higher electrical conductivity when the middle bulk Si layer was excluded. The reason is that the bulk Si has lower electrical conductivity than SiNW/SOG due to THE lower doping level. The electrical conductivity of the bulk Si is 100 times lower than that of the heavily doped SiNW part. The lines in Fig. 2(b) are calculated using the electrical conductivity data obtained from our single SiNW measurement.²¹ However, the measured electrical conductivity of the SiNW stack (1551 S/m at 700 K on average) was lower than the theoretical value (2301 S/m at 700 K) calculated using the single SiNW results from our previous work,²¹ which we attribute to the presence of contact resistance between the stacked SiNW arrays. Although we minimized the contact resistance between the stacked SiNW arrays in our experimental setup, some unavoidable resistance such as the contact resistance between the $Si O 2$ and the nanowires or the Ni/Ag paste electrode-to-electrode resistance due to surface roughness still affected our electrical conductivity measurements.

Third, to determine the Seebeck coefficient (S) of the SiNW arrays, we induced a potential gradient with an applied temperature difference (Fig. 5 in the supplementary material). We found that the Seebeck coefficient was comparable regardless of whether we excluded the middle Si part or not. Figure 2(c) shows that the Seebeck coefficient of the SiNW stack (224  $μ$V/K at 700 K on average) is higher than the calculated value (211  $μ$V/K at 700 K) based on the single SiNW measurement from our previous work.²¹ This could be attributed to the difference between the nanowires in the single SiNW and the SiNW stack. Some of the potential differences are different nanowire lengths and etch times. The doping concentration and porosity can change due to these differences which affects the Seebeck coefficient.

Finally, we calculated the ZT of the double-sided SiNW arrays in Fig. 2(d). The ZT of SiNW/SOG calculated based on the SiNW measurement is 0.316 at 700 K. Experimental ZT is 0.211, $∼70%$ of the calculated value at 700 K. Figure 2(d) also shows the ZT can reach 0.084 for stack (SiNW/SOG+ bulk Si) at 700 K, which is lower than SiNW/SOG due to lower electrical conductivity of the bulk Si as compared to SiNW/SOG. Our results demonstrate the potential of porous SiNW arrays to achieve high ZT values, and our approach can be used to investigate the influence of various parameters, such as contact resistance between stacked SiNW arrays, on the TE performance of the material.

To understand the individual contributions of various components in the double-sided SiNW array device toward its TE efficiency, we conducted an in-depth analysis of the ZT value changes from a single SiNW to SiNW stacks at 700 K, as illustrated in Fig. 3(a). Our study revealed that the introduction of the array structure and the middle bulk Si connection part led to a decrease in the ZT value of the SiNW. The theoretical ZT value of the SiNW/SOG is lower than that of the single SiNW as the area density of SiNW is approximately 15%. Except for the single SiNW case, the total cross-sectional area including both the SiNW and filler was used in the calculation of electrical and thermal conductivities. Since the electrical insulator glass SOG (85% fill fraction) has more than four times lower thermal conductivity than that of single SiNW as calculated in the supplementary material,³⁰ the calculated ZT of the SiNW/SOG is $∼50%$ of the single SiNW. We also observed a minor decrease in the measured SiNW/SOG ZT (obtained by removing the contribution of bulk Si obtained from stack experimental data) compared to the calculated SiNW/SOG ZT. However, the incorporation of the middle bulk Si part resulted in a significant decrease in the SiNW stack’s ZT value, as the bulk Si part had an electrical conductivity of approximately 1000 S/m, which is 100 times lower than that of the heavily doped SiNW part.

To visualize the individual contributions of bulk Si thickness and Ni contact layer thickness to different TE parameters, we summarized our results in Figs. 3(b) and 3(c). Our findings suggested that the bulk Si thickness had a significant role in determining the SiNW stack’s ZT value, with a thinner bulk Si layer leading to a higher ZT value. Specifically, as illustrated in Fig. 3(b), we found that the thermal conductivity increased as the bulk Si thickness increased, while the electrical conductivity decreased. As shown in Fig. 3(c), the Ni contact layer thickness also played a critical role in the SiNW stack’s ZT value, with a thicker Ni layer resulting in higher electrical conductivity, thereby leading to a higher ZT value. The rapid thermal annealing process shown in Fig. 2 in the supplementary material was useful to ensure the contact quality between the SiNW tips and the Ni layer.

These observations indicate that optimizing the bulk Si thickness and the Ni contact layer thickness could potentially enhance the TE performance of double-sided SiNW array devices. Therefore, our study provides valuable insights that could pave the way for the development of high-performance TE devices for various practical applications.

We further compared the TE performance, including thermal conductivity, electrical conductivity, Seebeck coefficient, and ZT, of our double-sided SiNWs with others reported in the literature, and the results are summarized in Table I. Our double-sided SiNW structure exhibits a thermal conductivity of 0.644 W/mK at 700 K, which is significantly lower than that of single-sided vertical SiNWs (10.1 W/mK at 300 K) of Lee et al.²² The electrical conductivity of our double-sided SiNWs is 4288 S/m at 700 K, which is substantially higher than the resistivity reported in the study of Uesugi et al.³¹ for the core-shell SiNWs. The Seebeck coefficient of our SiNWs is 225  $μ$V/K at 700 K, which is within the range of values reported in the literature but lower than the $−284$  $μ$V/K for the SiNW/SOG composite from Curtin et al.³² Our study is the only one that reports a ZT value at 700 K.

The double-sided structure of SiNW arrays, as presented in our study, is a better option than the single-sided SiNW structures. As we etch for longer time to obtain longer SiNWs and reduce the thickness of bulk Si, the porosity of the SiNWs also increases, which decreases the ZT of single SiNWs significantly. The double-sided structure is introduced to balance the need for having suitable porosity for SiNWs and minimizing the bulk Si thickness portion. The bulk Si part has higher thermal conductivity, and it is less doped, so it exhibits lower electrical conductivity compared to the heavily doped SiNW part, thus affecting the overall TE performance. In our study, we observed that the ZT of the SiNW stack (SiNW/SOG + bulk Si) is lower than that of the SiNW/SOG, which can be attributed to the increased thickness of the bulk Si part.

While our current study focuses on the fabrication and TE characterization of the double-sided SiNW arrays, further integration of those SiNW arrays into a TE module requires comprehensive investigations. Those studies need to determine the power output under various controlled temperature gradients to calculate the efficiency of energy conversion from heat to electricity. Power density needs to be evaluated to understand the potential of applying these devices under the constraints of space and weight limitations. Primary challenges at the device level include managing the thermal and electrical contact resistances at the junctions and ensuring the stability of these joints under varying thermal conditions. Additionally, it is challenging to accurately measure the small power outputs typical of micro-scale devices, which will require more precise measurement techniques, such as low-noise differential thermocouples and precision micro-voltmeters, to accurately capture the small temperature difference, voltage, and power outputs. Therefore, future studies will be needed before integrating these SiNWs into practical TE modules for real-world applications, such as waste heat recovery systems.

In conclusion, we have demonstrated the successful fabrication of high-quality double-sided SiNW arrays using advanced techniques. The engineering innovations in the double-sided structure, non-agglomeration wire tip engineering, and Ohmic contact formations have enabled us to overcome various challenges in the fabrication process and achieve uniformity in the SiNWs. The resulting high aspect ratio SiNW arrays exhibit excellent TE performance, with a maximum $Z T 700 K$ of 0.24 (SiNW/SOG), compared with the bulk Si $Z T 300 K=0.01$⁠.³³ In this work, we first reported the ZT of device made from the SiNW array.

The double-sided structure of the SiNW arrays, which allows for an increased surface area and a greater number of TE junctions, is a key factor in enhancing the TE energy conversion efficiency. The non-agglomeration wire tip engineering using the wrap-around CVD of $Si O 2$ on the SiNW tip area ensures that the wire tips are well-separated and that the SiNW tip contact area coverage increases, leading to reduced electrical resistance and increased TE performance. The Ohmic contact formations ensure that there is low electrical resistance and high thermal conductivity at the contact points of the devices, further contributing to the overall TE efficiency of the devices. Our study suggests that by optimizing the thickness of both the bulk silicon and nickel contact layer, the thermoelectric performance of double-sided silicon nanowire array devices can be improved.

In general, our results highlight the potential of high aspect ratio double-sided SiNW arrays as a promising material for efficient TE energy conversion. The advanced fabrication techniques and engineering innovations demonstrated in this work could pave the way for the development of high-performance TE devices based on SiNW arrays for various energy harvesting applications.

In general, the fabrication of double-sided SiNW arrays is shown in the schematics in Fig. 2 in the supplementary material. We fabricated double-sided SiNW array modules using the same MACE conditions as the best-performing individual nanowires. The double-sided SiNW array will help with the final TE generator device by improving the effective TE area (SiNW part). Because the SiNW part has better TE properties compared with the Si wafer part. The process of forming the double-sided SiNW array is similar to the single-side SiNW array fabrication process in the supplementary material using the NIL patterning method followed by MACE, except for the additional patterning on the second side of the Si wafer. Figure 6 in the supplementary material shows SEM side views of two double-side Si nanowire array samples after MACE. The SiNW array has a nanowire length of 180–220  $μ$m due to variation during the chemical etching process and the middle Si wafer thickness is around 20  $μ$m. The double-side SiNW array followed by post-doping will be filled with SOG and the top and bottom contact electrodes will be created. The additional fabrication processes of the double-sided SiNW array with boron doping, tip separation, and Ohmic contact formation are shown in Figs. 2(b)–2(i) in the supplementary material. The PD process for the SiNW array includes the dip coating with a high concentration boron solution (SOD, 2–2.5 wt. % boron in SOG solution). The coated samples were then annealed in a tube furnace (Ar 95 vol. %/ $O 2$ 5 vol. %) at $900 °$C for 30 min, and the excess dopant solution was removed using 2 wt. % HF solution for 10 min [Fig. 2(5i) in the supplementary material]. For higher doping levels, this process was repeated under the same conditions as shown in Figs. 2(b)–2(d) in the supplementary material. After PD, the SiNW array merged in IPA was dried through with the critical point dryer (Tousimis Automegasamdri-915B). The SiNW array after CPD was coated with 600 nm $Si O 2$ using the PlasmaTherm Shuttlelock PECVD System at $350 °$C for 10 min as shown in the schematic in Fig. 2(e) in the supplementary material. Then, the SiNW array was filled with 4.5 wt% SOG solution (250F, Filmtronics, USA) using the repeated dip coating method until the SiNW array is completely filled as shown in Fig. 2(f) in the supplementary material. The SOG solution was evaporated in the fume hood on a $100 °$C hotplate. The top $Si O 2$ layer SOG-filled SiNW array was etched by the RIE [PlasmaPro 80 (Oxford)] using $CH F 3$/ $O 2$/Ar under 350 W, 35 mTorr, 30–120 min (depending on the top $Si O 2$ thickness) as shown in Fig. 2(g) in the supplementary material to expose the tips for metal contact layer formation. The Ohmic contact is formed with 600 nm Ni deposition using e-beam evaporation (Kurt J. Lesker) with rapid thermal annealing (AllWin 610 RTA) at $850 °$C for 30 s in $N 2$ environment as shown in Fig. 2(h) in the supplementary material. The Ag paste (PELCO High-Performance Silver Paste, Product No. 16 047) with 2 h cure at $93 °$C coating on both sides of the SiNW array as shown in Fig. 2(i) in the supplementary material.

The morphologies of SiNWs samples were characterized with scanning electron microscopy (SEM) (FEI Magellan 400 XHR under 5 kV accelerating voltage and 50 nA beam current).

Different measurement setups were built to determine the thermal conductivity, electrical conductivity, and Seebeck coefficient of SiNW arrays. For the measurement from 300 to 700 K, the ambient temperature was controlled using a hot plate. (1) A standard $3ω$ technique^34–37 was used for the thermal conductivity measurement [see Fig. 3(a) in the supplementary material for the schematic of the $κ$ measurement setup]. With $3ω$ measurement, we can extract the intrinsic thermal conductivity of SiNW arrays by simultaneously determining both the intrinsic $κ$ and the thermal contact resistance between the sensor and the array. This advantage originates from the capability of varying the frequency and thermal penetration depth, which enables extracting thermal properties at different locations. Figure 3(b) in the supplementary material shows a representative fit to the frequency-dependent data and the extracted room temperature k (0.71 W/mK) agrees well with the predicted $κ$ using single nanowire results. (2) The effective electrical conductivity of SiNW arrays was measured using the four-probe method. Two-probe measurements were typically performed for this type of measurement due to the difficulty of placing voltage probes across the thin SiNW array of 500  $μ$m. To overcome this challenge and avoid the effects of contact electrical resistance, we prepared a stack of SiNW arrays so that the voltage can be measured using additional voltage probes [Fig. 4(a) in the supplementary material]. Silver paste was used to bond the SiNW arrays for a minimized electrical contact resistance in between. During the measurements, a range of AC current was applied using a current source and the voltage was measured with a lock-in amplifier. Figure 4(b) in the supplementary material displays the linear I–V feature of the stack which verifies the ohmic contact in our SiNW array samples. (3) For the measurement of Seebeck coefficient, the temperature difference across the array was controlled by varying the thermal convective conditions, e.g., a high heat transfer coefficient on the array surface results in a large temperature difference [Fig. 5(a) in the supplementary material]. The voltage was measured using a multimeter and the Seebeck coefficient can be determined by calculating the slope of voltage vs temperature difference [Fig. 5(b) in the supplementary material].

Additional calculation, process flow, and characterization can be found in the supplementary material.

The authors acknowledge the support and funding provided by the California Energy Commission (CEC) for this research project. Part of this work was performed at the Stanford Nano Shared Facilities (SNSF) and supported by the National Science Foundation (NSF) under Award No. ECCS-2026822.

The authors have no conflicts to disclose.

Rui Ning and Yuqiang Zeng contributed equally to this work.

Rui Ning: Conceptualization (equal); Data curation (equal); Formal analysis (equal); Investigation (equal); Methodology (equal); Project administration (equal); Resources (equal); Validation (equal); Visualization (equal); Writing – original draft (equal); Writing – review & editing (equal). Yuqiang Zeng: Conceptualization (equal); Data curation (equal); Formal analysis (equal); Investigation (equal); Methodology (equal); Project administration (equal); Validation (equal); Visualization (equal); Writing – original draft (equal); Writing – review & editing (equal). Vi Rapp: Conceptualization (equal); Data curation (equal); Formal analysis (equal); Funding acquisition (equal). Buyi Zhang: Conceptualization (equal); Formal analysis (equal); Methodology (equal). Lin Yang: Conceptualization (equal); Data curation (equal); Formal analysis (equal). Ravi Prasher: Conceptualization (equal); Data curation (equal); Formal analysis (equal); Funding acquisition (equal); Investigation (equal); Methodology (equal); Project administration (equal); Resources (equal); Supervision (equal); Writing – review & editing (equal). Xiaolin Zheng: Conceptualization (equal); Data curation (equal); Formal analysis (equal); Funding acquisition (equal); Investigation (equal); Methodology (equal); Project administration (equal); Resources (equal); Supervision (equal); Validation (equal); Writing – review & editing (equal).

The data that support the findings of this study are available from the corresponding authors upon reasonable request.