Continuously tunable uniaxial strain control of van der Waals heterostructure devices

Strain is a powerful tool for directly manipulating the crystal lattice of materials, and consequently for tuning their electronic properties. For example, uniaxial strain can break the in-plane rotational symmetry of a lattice, potentially generating new electronic phases. Over the past decade, a powerful technique has been developed for applying continuously tunable uniaxial strain to three-dimensional bulk quantum materials using a device based on three piezoelectric stacks.¹ This technique has been widely used to study and tune superconductivity,^2–5 topological phases,^6,7 and nematicity^8–11 in a variety of bulk quantum materials and to investigate their thermodynamic properties.^12,13 Over the past few years, van der Waals (vdW) heterostructures have emerged as exciting new platforms for exploring related strongly correlated and topological states in two dimensions. Flat electronic bands arise when two or more vdW sheets are properly stacked and can host a wealth of emergent states including superconductivity, nematicity, ferromagnetism, generalized Wigner crystals, and both integer and fractional Chern insulators.^14–25 However, technical constraints have so far severely limited the extension of existing strain-tuning techniques to the study of these states in vdW heterostructures.

Although there have been a number of approaches developed for applying strain to vdW materials, so far none are compatible with standard electrical transport measurements of dual-gated vdW devices assembled on a silicon/silicon dioxide (Si/ $SiO 2$⁠) wafer substrate.^26–32 Prior methods have mostly focused either on suspended vdW samples, which are mechanically fragile, or devices with limited numbers of gate and contact electrodes. In this paper, we introduce a novel method that integrates traditional vdW heterostructure device fabrication on silicon substrates with a three-piezo-stack-based strain cell.^1,8,33–36 We quantify the induced strain in the active layer of the vdW heterostructure by Raman spectroscopy and corroborate this value with estimates from metallic strain gauges either glued onto the piezo stack or evaporated onto the silicon wafer near the vdW device. We further characterize the strain transmission through multilayer vdW heterostructures by characterizing the strain induced hexagonal boron nitride (hBN) for different flake thicknesses and for twisted hBN multilayers. Our measurements indicate that strain is effectively transmitted from the silicon wafer into many layers of vdW flakes residing on top. Finally, we also showcase the capabilities of our strain technique by measuring the electrical transport properties of a twisted bilayer graphene (tBLG) device near the magic angle and show that strain can induce large changes in the device resistivity. Our technique is compatible with additional experimental probes beyond optics and transport and opens up new avenues for future experiments in vdW heterostructure devices.

Our experimental design combines the well-established piezoelectric-based strain technique for bulk samples^1,8,36 with the standard dry-transfer technique for fabricating vdW heterostructure devices.³⁴ We first discuss the challenges inherent to integrating these two techniques and overview our solution of creating a bowtie-shaped silicon substrate.

vdW heterostructure devices are typically fabricated on 500  $μ$m thick Si/ $SiO 2$ wafer substrates.^34,37,38 A simple way to induce strain to the vdW heterostructure is to directly strain the substrate wafer. However, single crystalline silicon is a rigid material, with Young’s modulus of $≈130$– $180$ GPa.³⁹ Hence, the force required to strain a millimeter size wafer to $≈1$% is approximately 750 N, far exceeds what can be achieved in existing piezo-based strain devices. Therefore, it remains an open challenge to identify a suitable substrate that is flexible enough to achieve high levels of the strain, yet rigid enough to be compatible with the fabrication of state-of-the-art vdW heterostructure devices. One approach is to replace the silicon wafer with a flexible substrate, such as a thin metal or a polymer.^40–44 For example, large tensile and compressive strains were previously induced in a vdW material by using a two- or three-point bending geometry with flexible substrates such as polyimide-coated phosphor bronze or soft polyethylene-based thin films.^40,43,44 However, bending the substrate can additionally induce an unintentional vertical strain gradient in multilayer vdW heterostructures.

Developments of piezoelectric strain cell technology over the past decade have significantly advanced experimental capabilities for uniaxial strain tuning of bulk crystals.¹ The key innovation was the arrangement of three parallel piezo stacks, which compensates for the large (and inverse) thermal contraction of the piezo stacks. This geometry further enables the application of much larger strain values than previously possible (up to $≈±$1%) owing by the counter motion of the central and outer piezo stacks. This strain cell is now commercially available, and it has been successfully integrated with different experimental probes including nuclear magnetic resonance,⁴⁵ x-ray scattering,^4,9 AC specific heat,¹² and the elastocaloric effect.¹³ This development naturally leads to the possibility of using the piezoelectric strain cell to apply uniaxial strain to a silicon substrate.

However, the very high Young’s modulus of silicon still presents a significant challenge. Without any modification, inducing a one percent strain in a regular silicon wafer requires a force that far exceeds the blocking force of the typical piezo stacks used in commercial strain cells. Several approaches have been developed so far in an attempt to circumvent this issue. One approach is to suspend a sample across a micrometer size gap (⁠ $∼$3–5  $μ$m), which is created by carefully cleaving the silicon wafer.⁴⁶ Although this approach can result in the application of strain exceeding 1% to a thin vdW flake, it is extraordinarily difficult to fabricate complex vdW device architectures that are suspended across the gap.

Another approach is to transfer the vdW onto a thin silicon wafer strip, ideally only a few hundred micrometers wide. The small cross section of the thin strip greatly reduces the amount of force required to strain the substrate.^46,47 However, the extremely small size of thin strip makes the fabrication of conventional vdW heterostructure devices very difficult. To address this issue, we developed a new approach in which we first shape the silicon wafer into a bowtie shape. This geometry is inspired by a similar titanium platform structure used in Refs. 8 and 36 to strain bulk crystals. The key advantage of this design is the narrow bridge of the bowtie greatly reduces the amount of force required to induce strain in that region, while the large area at two ends of the wafer simultaneously enables the fabrication of arbitrarily complex vdW heterostructure devices with top and bottom gates and many electrical contacts.

We use a home-built piezoelectric strain cell with a design similar to the one introduced by Hicks et al.¹ As depicted in Fig. 1, the device comprises three piezo stacks (⁠ $5×5×9$ mm, with high stiffness constant and blocking force⁴⁸) and custom-machined titanium frames. We further include a beam holder that affixes the strain cell to a printed circuit board (PCB) sample mount, which allows us to easily wire up the strain cell for use in different cryostats (we have so far used a PPMS from Quantum Design, Inc., and a top-loading dilution refrigerator from Bluefors⁴⁹). Viewed from above the strain cell, the bowtie-shaped silicon chip (colored purple) is glued with Stycast epoxy⁵⁰ onto a titanium chip carrier (colored orange), which is prefixed onto the titanium sample mount by screws on each end. The glue covers roughly half of the top of the tab area of the bowtie to ensure robust mechanical anchoring, while leaving enough space for around eight electrical contacts on each side. The gold electrical pads are wired to a custom PCB that is mounted on the side of the strain cell. A commercial strain gauge⁵¹ is glued onto one of the piezo stacks and is used to estimate the displacement of the titanium chip carrier by the piezo stacks. A small carbon resistor is adhered to the titanium frame of the strain cell in order to monitor the local temperature.⁵² 

We fabricate our vdW heterostructure devices atop a 50  $μ$m thick silicon wafer with a 285 nm $SiO 2$ capping layer.⁵³ This wafer is ten times thinner than those conventionally used for vdW heterostructure devices. The reduced thickness is important for lowering the spring constant and enabling the application of larger strain.⁴⁶ We first laser-cut two rectangular holes out of the wafer in order to create the bowtie shape. In contrast to previous methods used for laser cutting titanium and quartz plates,^8,36 additional steps are needed to protect the surface of $SiO 2$ layer when laser cutting the silicon wafer since the vdW heterostructure is extremely sensitive to the surface cleanliness. Therefore, prior to the cutting, we glue the thin wafer atop a thicker silicon substrate using polymethyl methacrylate (PMMA) as the bonding adhesive. The $SiO 2$ surface of the thin wafer is arranged to face downward, in contact with the PMMA adhesive. There are two benefits of doing this: first, to provide mechanical stability for the fragile thin wafer, and second, to protect the $SiO 2$ layer from silicon dust generated during the laser cutting process. The substrate wafer is affixed onto an aluminum plate with double-sided tape, and the plate is mounted on the laser cutting board. We employed a laser cutting system (LPKF ProtoLaser) to cut the silicon wafer. We note that the laser power is critical since over cutting can also damage the $SiO 2$ layer or result in poor detachment from the PMMA. Here, we use a laser power of 1.2 W with a beam diameter of 10  $μ$m and 1000 times cut repetition for each pattern. The square silicon wafer is cut into the designated pattern outlined by the dashed lines shown in Fig. 2(a). Note that this pattern includes two outer bridges in addition to the central bridge of the bowtie, as shown in Fig. 2(b). These outer bridges are temporary, but they are essential for providing mechanical stability during the transfer and fabrication of vdW heterostructure device. These two outer bridges are cut by hand after mounting the wafer onto the piezoelectric strain cell. The bridges of the bowtie are aligned along <110> directions of a (100) wafer.

After laser cutting, the small three-bridge-patterned thin silicon chips are detached from the Si substrate wafer by sonicating in acetone. The three-bridge-patterned chip is then glued to another rigid silicon substrate with PMMA, this time with its $SiO 2$ layer facing upwards [Fig. 2(b)]. A vdW heterostructure is assembled layer-by-layer using the standard dry-transfer technique with a poly-carbonate (PC) stamp. After the stack is assembled, the PC stamp is melted onto the central bridge of the thin silicon wafer and soaked in chloroform to dissolve the PC, leaving behind only the vdW heterostructure. Since the patterned wafer detaches from the thicker Si/ $SiO 2$ substrate wafer in chloroform, it must be re-affixed to a new rigid substrate for further processing. The vdW heterostructure is then processed into a Hall bar geometry and contacted electrically following a standard series of steps involving electron beam lithography, plasma etching, and metal deposition. The bowtie pattern created in the silicon wafer does not impede PMMA spin coating and electron-beam lithography; thus, these procedures are essentially the same as in the standard fabrication process for vdW heterostructures. We arrange the Hall bar such that it is aligned along the direction of uniaxial strain. Figure 2(c) shows a typical three-bridge chip with a tBLG device at its center. In addition to the gold electrodes connected to the device, we also evaporate gold along the laser-cut edges of the chip. These gold strips are essential; otherwise, the rough wafer edges resulting from laser cutting can prevent a smooth metal liftoff procedure. Additionally, the roughness can make the wafer more prone to breaking under tensile strain, but these can be smoothed and potentially strengthened through chemical etching. We also evaporate a meander-shaped gold wire near the device, which serves as a custom local strain gauge. The three-bridge silicon chip is then epoxied to the titanium chip carrier pre-mounted on the strain cell, as described above. The final step is to cut the outer two bridges [at positions indicated by the black crosses in Fig. 2(d)] using a scalpel blade after the epoxy has cured.

In most piezoelectric strain cell experiments, the strain level of the sample was estimated by measuring the displacement of piezo stacks using a capacitance strain gauge.^8,36 The measured displacement was then converted to the strain of the sample by using a strain transmission factor or an effective length determined by the finite element analysis. We performed similar measurements and analysis and present the results in  Appendix A. We have also developed two methods to directly measure the amount of strain induced in the vdW heterostructure as we bias the piezo stacks. We discovered that these two methods provide more accurate and reliable measurement of the strain, which we discuss below.

In the first method, we perform Raman spectroscopy on both the silicon wafer and on a monolayer graphene encapsulated in hBN. We use a laser power of 300  $μ$W, with integration times of 160 s for graphene and 10 s for silicon. These Raman spectra allow us to precisely determine the magnitude of uniaxial strain independently of graphene and silicon using the relationships previously established in Refs. 40 and 54. Figures 3(c) and 3(d) show the Raman spectra of silicon substrate and graphene taken at different piezo voltages at a temperature of 2 K. Both peaks systematically blueshift due to the effect of compressive uniaxial strain, as shown in Figs. 3(e) and 3(f). We note that the strain cell applies uniaxial stress, which induces both symmetric (⁠ $A 1 g$ irrep) and antisymmetric (⁠ $E g$ irrep, in the case of graphene) components of strain. The linear shift of Raman peak energy is due to the symmetric component of strain. The in-plane Poisson’s ratio along <110> directions of a (100) silicon is only 0.064, indicating a nearly uniaxial strain along the stress direction. This uniaxial strain condition is the same as the Raman measurement performed in Refs. 40 (Si) and 54 (graphene), hence we can reliably use the data in previous work to extract the strain value. We convert the wavenumber of the Raman peak to uniaxial strain following the previously established relationships and plot the measured strain value as a function of piezo voltage in Fig. 3(e). We note that a higher bias up to 300 V, if allowed by the instrumental setup, can be safely applied to the piezo stack at cryogenic temperatures and would likely induce a larger strain.^1,36 The strain induced in the graphene and silicon both vary linearly as a function of piezo voltage, and overlap almost perfectly. The slightly reduced strain in graphene compared with the silicon indicates that $≈80$% of the strain induced in the silicon wafer is transferred to graphene.

In order to demonstrate the power of our strain technique, we measure the strain-dependent transport of a vdW heterostructure device consisting of a twisted bilayer graphene device. The twist angle of the device is $θ= 1.2 °$⁠, very near the magic angle at which superconductivity and other correlated states are prominent. The rich correlated and topological physics of magic-angle tBLG has been explored in great detail elsewhere;^20,21 here, we use it as a model system to test our technique, given that the band structure is expected to be highly sensitive to strain. The device consists of tBLG encapsulated by flakes of hBN, all resting on a flake of graphite (further details on this device can be found in Ref. 55). The graphite acts as a back gate and can change the charge carrier density in the tBLG when a voltage is applied between the graphite and tBLG. Figure 4(c) shows a measurement of the longitudinal resistivity, $ρ$ of the device as a function of the band filling factor, $ν$ (⁠ $ν=4$ corresponds to fully filled moiré bands, where the factor of four reflects the spin and valley degeneracy of graphene). In our measurements performed at a temperature of 5 K, we see a resistive state at $ν=0$ indicative of the charge neutrality point, as well as resistive states at other selected integer values of $ν$ indicative of incipient correlated insulating states. As we apply uniaxial strain by changing the bias on the piezo stacks, we see that the resistivity of the device can change by hundreds of ohms, depending on the precise value of $ν$⁠.

The effect of strain is especially prominent around $ν=−2$⁠, which corresponds to a developing correlated insulating state at half filling of the moiré valence band in the tBLG. Figure 4(d) shows how $ρ$ evolves both as a function of temperature and strain at a fixed band filling factor of $ν=−1.99$⁠. Overall, the temperature dependence is characteristic of tBLG devices previously reported.^23–25 By comparing $ρ(T)$ at different values of applied strain, we see that there is a monotonic decrease of the resistivity at all temperatures up to 20 K as compressive strain is applied. Figure 4(e) shows the relative resistivity, $Δρ$⁠, as a function of compressive strain at values of $ν≈−2$⁠. In all cases, we see a nearly linear change in resistivity as strain is applied. Although future work is necessary to unravel the physics underlying the strain-tuning of these states, the large linear elastoresistance we see clearly illustrates the ability of strain to manipulate the electronic properties of tBLG.

In summary, we have reported the development of a new technique for applying continuously tunable strain to vdW heterostructure devices of ultrahigh quality and arbitrary complexity. The strain device is based on a commercially available three piezo stack design, with custom PCBs added in order to electrically connect to vdW heterostructure devices. We achieved a large strain in excess of $−0.15$% by appropriately modifying the silicon substrate. We are able to demonstrate efficient strain transfer from the piezo stacks to the vdW heterostructure. As shown in Fig. 3(e), the measured strain is linear in the applied piezo voltage over the entire range we studied. This linearity implies that the total strain we can achieve can very likely be increased by further improvements in epoxying both the top and bottom surfaces of the silicon wafer to the sample mount, and by applying larger voltages to the piezo stacks up to 300 V. Our technique paves the way for future characterization and control of the correlated and topological physics of a variety of vdW heterostructures. The technique is readily compatible with a range of other characterization tools, including scanning probe microscopes.

This work was mainly supported by the NSF MRSEC at UW under Grant No. DMR-2308979; the Gordon and Betty Moore Foundation’s EPiQS Initiative, Grant No. GBMF6759 to J.-H.C.; and the U.S. Department of Energy, Office of Science, Office of Basic Energy Sciences under Award No. DE-SC0023062. The vdW heterostructure device fabrication was partially supported by the Army Research Office under Grant No. W911NF-20-1-0211. J.-H.C. acknowledges support from the David and Lucile Packard Foundation. M.Y. and J.-H.C. also acknowledge support from the State of Washington-funded Clean Energy Institute. This work made use of shared fabrication facilities provided by NSF under No. MRSEC 1719797.

The authors have no conflicts to disclose.

Z.L. and X.M. contributed equally to this paper.

Zhaoyu Liu: Conceptualization (equal); Data curation (equal); Formal analysis (equal); Investigation (equal); Methodology (equal); Project administration (equal); Supervision (equal); Validation (equal); Visualization (equal); Writing – original draft (equal); Writing – review & editing (equal). Xuetao Ma: Conceptualization (equal); Data curation (equal); Formal analysis (equal); Investigation (equal); Methodology (equal); Validation (equal); Visualization (equal); Writing – original draft (equal); Writing – review & editing (equal). John Cenker: Data curation (supporting); Formal analysis (supporting); Writing – review & editing (supporting). Jiaqi Cai: Data curation (supporting); Writing – review & editing (supporting). Zaiyao Fei: Data curation (supporting); Writing – review & editing (supporting). Paul Malinowski: Conceptualization (supporting); Data curation (supporting); Writing – review & editing (supporting). Joshua Mutch: Conceptualization (supporting); Data curation (equal); Writing – review & editing (supporting). Yuzhou Zhao: Conceptualization (supporting); Data curation (supporting); Formal analysis (supporting); Writing – review & editing (supporting). Kyle Hwangbo: Data curation (supporting); Writing – review & editing (supporting). Zhong Lin: Conceptualization (supporting); Writing – review & editing (supporting). Arnab Manna: Data curation (supporting); Writing – review & editing (supporting). Jihui Yang: Funding acquisition (equal); Writing – review & editing (equal). David Cobden: Funding acquisition (supporting); Methodology (supporting); Writing – review & editing (supporting). Xiaodong Xu: Funding acquisition (supporting); Writing – review & editing (supporting). Matthew Yankowitz: Conceptualization (equal); Formal analysis (equal); Funding acquisition (equal); Investigation (equal); Methodology (equal); Project administration (equal); Resources (equal); Supervision (equal); Validation (equal); Visualization (equal); Writing – original draft (equal); Writing – review & editing (equal). Jiun-Haw Chu: Conceptualization (equal); Formal analysis (equal); Funding acquisition (lead); Investigation (equal); Methodology (equal); Project administration (equal); Resources (equal); Supervision (equal); Validation (equal); Visualization (equal); Writing – original draft (equal); Writing – review & editing (equal).

The data that support the findings of this study are available from the corresponding authors upon reasonable request.

To estimate the strain transmission factor $μ$⁠, we performed FEA using ANSYS Academic Research Mechanical software to investigate the strain distribution in the bowtie-shaped silicon chip model, as shown in Fig. 5(a). Young’s modulus and Poisson’s ratio of the silicon along the <110> directions of a (100) wafer in the simulation are 169 GPa and 0.064, respectively.³⁹ Young’s modulus of the $SiO 2$ layer is 70 GPa. The narrow bridge of the silicon chip is 0.3 mm in width and 50  $μ$m in thickness. Using $k=Y A L$⁠, we estimated the effective spring constants of Si and $SiO 2$ layers on a strip substrate matching the dimensions of the central bridge of the bowtie-shaped chip. The effective spring constant of the silicon substrate is $k=5.1 N / μ m$⁠, which is significantly larger that of the $SiO 2$ layer, $0.012 N / μ m$⁠. Hence, the $SiO 2$ layer can be safely ignored in our FEA simulation.

In this simulation, a 5  $μ$m displacement was applied to both sides of the titanium plate, which results in a total 2% nominal uniaxial strain. We assume the thickness of the epoxy layer to be 50  $μ$m. In Figs. 5(b) and 5(c), we present both the top and cross-sectional views of the strain distribution. Notably, the strain primarily aligns along the white dashed center-line of the silicon wafer. The highest strain region (colored in red) is located at the center, where the vdW heterostructure was fabricated. As shown in Fig. 5(d), in the simulation the strain at the center of the silicon bridge is 1.04%, resulting in a strain transmission factor $μ FEA=52%$⁠. Nevertheless, this simulation does not take into account that the titanium strain cell itself may also deform. Using the effective spring constant of $12 N / μ m$ for the strain cell³⁶ and $5.1 N / μ m$ for the substrate, we estimate that only 70% of the displacement induced by the piezo actuator is transferred to the silicon substrate. Taking this factor into account, the strain estimated by this method is within a factor of two of the strain measured by the Raman spectroscopy [Fig. 3(e)].

Additionally, we simulate the strain at the center of the bridge as a function of the epoxy thickness, $t$⁠. The results, presented in Fig. 5(f), demonstrate that the applied strain gradually decreases as the epoxy thickness exceeds 100  $μ$m. However, in practice, achieving a precise thickness of epoxy presents a challenge. We attempt to minimize the thickness by using as little epoxy as possible and by carefully pressing the wafer down in order to extrude excess epoxy out from underneath.