We propose a main mechanism of large valley splitting experimentally observed at the interface of buried oxide (BOX)/silicon-on-insulator (SOI) structures. Silicon metal-oxide-semiconductor field effect transistors fabricated on a SIMOX (001) substrate, which is a kind of the SOI substrate, that is annealed at high temperatures for a long time are known to exhibit large valley splitting, but the origin of this splitting has long been unknown. Extended zone effective-mass approximation predicts that strain significantly affects valley splitting. In this study, we analyzed valley splitting based on this theory and found that the shear strain along [110] of approximately 5% near the BOX interface is a promising source for large valley splitting.

## I. INTRODUCTION

Valley splitting at the interface of Si/thermally grown SiO_{2} has been studied from the early stage of silicon-based electronics and is still gaining a great deal of attention because it can be a fatal source of decoherence for silicon-based spin qubits.^{1,2} The decoherence problem is almost unavoidable because the magnitude of the typical splitting in Si/SiO_{2} or Si/SiGe systems is several tens of microelectron-volts and differs from device to device. Therefore, controlling valley splitting in this system is urgent. Research on valley splitting has a long history. In the integer quantum Hall effect in silicon, a splitting caused by the valley degrees of freedom was observed.^{3–5} At this time, basic theories on valley splitting based on effective-mass approximation (EMA) were developed, and valley splitting at the Si/thermally grown SiO_{2} interface was well explained by these theories.^{6–12}

In the 1990s, papers reporting valley splitting several tens to thousands of times larger than that at the Si/thermally grown SiO_{2} interface^{13,14} attracted much attention, where MOSFETs were fabricated on SIMOX (001) substrates annealed at high temperatures for a long time. We have reported on this large valley splitting^{15} and studied its principle and applications.^{16} Since large valley splitting has the potential to solve the serious issue of valley degeneracy in spin qubits, several other researchers have focused on its importance and have been investigating its origin. Although the principle is different from ours, a technique to achieve large valley splitting by applying a strong electric field using a high-k dielectric has recently been demonstrated^{17} to overcome this problem. Large valley splitting was verified based on various theories such as tight binding models,^{18,19} EMA incorporating an additional perturbation term fitted by a tight binding theory so as to avoid the problems in describing microscopic phenomena,^{20} and EMA combined with first-principle calculations.^{21} There were also theories incorporating interface states,^{22,23} abrupt interfaces,^{24} and superlattices.^{25,26} However, none of these theories have provided a clear answer to the origin of large valley splitting.

In this paper, we analyze experimental results on large valley splitting based on the theoretical framework of the extended zone EMA reported in Ref. 6. This paper incorporates the effects of strain that have not been addressed in many previous papers demonstrating that the introduction of shear strain significantly enhances valley splitting caused at the X point. Based on this theory, it is predicted that a compressive strain of approximately 5% along [110] is introduced near the buried oxide (BOX) and silicon-on-insulator (SOI) interface of the SIMOX substrate. In addition, it was confirmed that large valley splitting could be reproduced by the EMA theory incorporating the strain even in multiple devices with different film thicknesses. These results are very important findings because they may provide a solution to valley degeneracy and variation of valley splitting, which are critical issues in actualizing silicon spin-qubit quantum computers.

## II. ORIGIN OF VALLEY SPLITTING

Here, we briefly explain the basic principle of valley splitting. Bulk silicon has six equivalent conduction-band (CB) minima on the three orthogonal ⟨100⟩ axes as shown in Figs. 1(a) and 1(b). If we introduce [001] spatial confinement to form a so-called quantum well (QW), the electrons split into two groups of valley states. The valleys with lighter EM along [001] become fourfold degenerate, and the remaining valleys with heavier EM are doubly degenerate. This doubly degenerate state is the ground state of the QW. By applying an external field or introducing a physical structure to establish even stronger confinement along [001], the doubly degenerate state exhibits further splitting. This energy splitting is referred to as valley splitting. Valley splitting is fundamentally attributed to the allowance of valley degeneracy due to the difference in wavenumber k. When a very strong confinement is introduced, the wave functions belonging to states −k_{0} and +k_{0} superimpose a wide range of wavenumber states in the momentum space. The probability densities of electrons in each valley eventually overlap in the momentum space as shown in Fig. 1(b). When an overlap of valley states occurs, the respective states interfere, hybridize, and exhibit energy splitting.

## III. DEVICE STRUCTURES

Figure 1(c) shows the device structure. This device uses a SIMOX (001) substrate^{27} as the starting material. First, the SIMOX substrate is annealed at 1350 °C for 40 h in an atmosphere of 0.5% O_{2} in Ar to improve the flatness of the BOX/SOI interface.^{28,29} The surface oxide film formed by 40 h annealing is then removed using hydrofluoric acid, and after adjusting the thickness of the SOI (t_{SOI}), the front gate oxide (FOX) film is formed by thermal oxidation at 900 °C. Next, by depositing gates on both sides of the FOX and the substrate, we fabricate double-gate structure MOSFETs. Using the front gate (FG) and back gate (BG), we adjust the spatial distribution of the electron-wave function inside a thin SOI, i.e., a QW, and observe the valley splitting at the FOX or BOX interface. The thicknesses of the FOX (t_{FOX}) and BOX (t_{BOX}) are 20 and 400 nm, respectively, and that of the QWs (t_{SOI}) are 6 or 9 nm. The gate length (L_{g}) and width (W_{g}) are 400 and 200 *μ*m, respectively. Note that the BOX and FOX formation methods are remarkably different because the formation of the BOX is performed around unique temperatures exceeding the glass transition of SiO_{2} or temperatures near the melting point of silicon.

## IV. EXPERIMENTAL RESULTS: I-V CHARACTERISTICS

Figure 2(a) shows typical drain current I_{D} vs FG voltage V_{FG} characteristics of the fabricated MOSFETs (t_{SOI} = 9 nm). All of the following measurements were conducted at 4.5 K. For BG voltage (V_{BG}) > 0 and V_{FG} < 0, only the channel at the BOX interface is open, where a distinct kink structure is observed (indicated by arrows). This structure reflects the two-dimensional density of states (2D-DOS) in the valley-coupled condition. This structure is related to valley splitting that we focus on in this paper. A negative differential structure appears at V_{FG} ∼ 0 V, indicating a channel opening at the FOX interface. In contrast, for V_{BG} < 0, only the FOX interface channel is open and no particular structure appears. Figure 2(b) shows a contour plot of ∂^{2}I_{D}/∂V_{FG}^{2}. For V_{BG} < 0, a single-line structure due to the threshold of the FOX interface channel is observed, while for V_{BG} > 0 a distinct splitting structure appears. This structure originates from the I_{D}−V_{FG} kink described above, which corresponds to valley splitting. The lower line of ∂^{2}I_{D}/∂V_{FG}^{2} represents the onset of the electron occupation of the 2D state originating from the bonding orbital of the valley-coupled state, and the upper line represents its antibonding orbital.

Figure 2(c) shows the V_{BG} dependence of the valley splitting for each t_{SOI} thickness. The sizes of valley splitting are obtained by 2D-DOS of silicon and electron densities, which are given by the capacitance of FG (C_{FG }= ε_{SiO2} ε_{0}/(t_{FOX }+ t_{SOI}ε_{SiO2}/ε_{Si})) and the V_{FG} difference (ΔV_{FG}) in ∂^{2}I_{D}/∂V_{FG}^{2}, where ε_{SiO2}, ε_{Si}, and ε_{0} represent the relative permittivity of SiO_{2}, silicon, and the permittivity in a vacuum, respectively. This figure also shows the electric field of the SOI (F_{SOI}) corresponding to each V_{BG}. This V_{BG} to F_{SOI} conversion is obtained by comparing the V_{BG} dependence of the transverse optical phonon peak given by electroluminescence with the numerical simulation of the quantum confined Stark shift,^{16} where electroluminescence is observed using the pn contacts of the same device. In the device with t_{SOI} = 6 nm shown in Fig. 2(c), valley splitting is indeed several hundred times larger than that expected at the SOI/thermal-SiO_{2} interface. For V_{BG} < 0, electrons are squeezed at the SOI/thermally grown SiO_{2} interface (FOX), resulting in an energy splitting of a few hundred microelectron volts the value of which is so small that we were unable to observe a distinct structure. On the other hand, when V_{BG} > 0, electrons are squeezed at the BOX/SOI interface, and in this state, a huge valley splitting occurs that cannot be explained by conventional theory. Figure 2(c) shows that the difference in valley splitting due to the difference in t_{SOI} is small. This is because, even theoretically, the valley splitting dependence on thickness appears only near a zero electric field, and the thicker the film, the lower the film-thickness dependence. Therefore, the difference in film thickness is almost negligible on the scale we are measuring.

## V. VALLEY SPLITTING BY EXTENDED ZONE EMA INCORPORATING SHEAR STRAIN

_{15}, $ \Gamma 1 u$, and $ \Gamma 1 l$.

^{30}In the extended zone EMA by Ohkawa and Uemura, the state of $ \Gamma 1 l$ is further perturbatively treated, and the lowest CB is expanded only with the two states of Γ

_{15}and $ \Gamma 1 u$. According to this theory, valley splitting is expressed by

_{Γ}and ΔE

_{X}represent valley splitting originating from the valley coupling via the Γ and X points, respectively. Here, ΔE

_{Γ}is expressed by

_{Γ}represents the energy difference between $ \Gamma 1 u$, and Γ

_{15}as shown in Fig. 3(a). Here, S

_{Γ}represents the overlap integral of envelope function ξ(z) corresponding to the +k

_{0}and −k

_{0}valley states in the QW, which can be interpreted as the Fourier transform of the square of the envelope function [Fig. 1(b)]. Term k

_{0}is the wavevector that gives the valley minimum point, k

_{0}= 0.85[001]2π/a

_{0}, where a

_{0}is the lattice constant of silicon. Therefore, valley splitting resulting from the Γ point is proportional to the 2k

_{0}component of the Fourier coefficients of the envelope function squared multiplied by ε

_{Γ}.

_{//}is sufficiently small,

_{u}is the shear-strain deformation potential and e

_{xy}represents the shear strain along ⟨110⟩. In silicon, the CB is degenerate at the X point due to glide symmetry, and this symmetry is broken when shear strain is applied as shown in Fig. 3(b). Note that hydrostatic strain has no effect on the valley splitting via the X point because it only shifts the Δ

_{1}and Δ

_{2}bands in the same direction.

^{31}In the extended zone scheme, the neighboring energy minima of the second Brillouin zone (BZ) across the X point corresponds to the valley of −k

_{0}as shown in Fig. 3(b).

Comparing ΔE_{Γ} and ΔE_{X} in Eqs. (2) and (4), respectively, both equations contain overlap integral S between the envelope functions corresponding to −k_{0} and +k_{0}. Since the real-space wave function is confined in the QW, the envelope function ξ(k) is dispersed in the wavenumber-space based on the confinement strength around −k_{0} and +k_{0} as shown in Fig. 1(b). The magnitude of this overlap integral is inversely proportional to the distance in the wavenumber-space (Δk) of these valleys. The distance at the Γ point is 2k_{0} = (2π/a_{0}) × 17/10, while at the X point it is |2k_{0}–4π/a_{0}| = (2π/a_{0}) × 3/10, which is approximately six times closer to the X point. Consequently, S_{X} is approximately two orders of magnitude larger than S_{Γ}, and the valley splitting via the X point becomes significant when the strain along ⟨110⟩ (e_{xy}) is nonzero.

## VI. COMPUTATIONAL METHODS OF VALLEY SPLITTING

^{7}provide a solution for valley splitting by solving a two-band effective mass (EM) equation, i.e., real-space envelope function ξ(z) in Eqs. (3) and (5) that is obtained by solving the two-band EM equations below simultaneously,

_{15}(z) and $ \xi 1 u(z)$, are obtained using the variational method. However, this solution is laborious to solve. Therefore, in this paper, valley splitting is calculated using the envelope function obtained from the numerical solution of the single-band EM equation.

^{9}where the valley splitting is given by

_{SOI}dependence on valley splitting in the infinite QWs expressed by Eq. (7) and ΔE

_{Γ}, which is obtained using Eq. (2) and real-space envelope function ξ(z). Here, ξ(z) is calculated based on the numerical solution of the following single-band EM equation using the finite element method with the EM of silicon along [001] as m

_{l}, its SiO

_{2}as m

_{SiO2}, and the barrier height as V

_{B}. Table I gives the parameters used in the numerical calculation. Here, V

_{B}is set to 10 keV to reproduce the infinite QW,

_{l}or m

_{SiO2,}q is the elementary charge, F(z) is electric fields along [001], and V(z) = 0 or V

_{B}. We adopted m

_{l }= 0.98 m

_{0}in the silicon region according to Ando.

^{11}Figure 4 shows that the numerical calculation obtained from the single-band agrees very well with the two-band analytical solution. Figure 4 also shows that the valley splitting oscillates with respect to t

_{SOI}. This is an interference effect observed between the well width (t

_{SOI}) and the wavelength given by the inverse of k

_{0}.

m_{l }= 0.98 m_{0} |

m_{SiO2 }= 0.98 m_{0} |

V_{B} (finite/infinite) = 3.1 eV/10.0 keV |

$ \u03f5 \Gamma $ = 3.65 eV |

$ \Xi u \u2032$ = 5.7 eV |

a_{0 }= 5.43 Å |

m_{l }= 0.98 m_{0} |

m_{SiO2 }= 0.98 m_{0} |

V_{B} (finite/infinite) = 3.1 eV/10.0 keV |

$ \u03f5 \Gamma $ = 3.65 eV |

$ \Xi u \u2032$ = 5.7 eV |

a_{0 }= 5.43 Å |

Since the valley splitting at the X point is obtained from the overlap integral S_{x} via the X point and shear strain e_{xy}, it is calculated using ξ(z) obtained by solving Eq. (8) in the same way as the Γ point.

## VII. COMPARISON BETWEEN EXPERIMENTAL RESULTS AND SIMULATIONS

Figures 5(a) and 5(b) show the calculated electric field dependence of ΔE_{Γ} and ΔE_{X} at each t_{SOI}, respectively. In ΔE_{X}, shear strain e_{xy} is set to 5%. Both graphs show that valley splitting increases as t_{SOI} decreases or F_{SOI} is increased. This is because under both conditions, the 2k_{0} component of the overlap integral on k-space takes a large value due to the stronger confinement of the electrons in the QW. When focusing on t_{SOI} dependence near the zero electric field, the large t_{SOI} exhibits linearity in terms of F_{SOI} dependence, while the extremely small t_{SOI} exhibits nonlinearity. This is because when t_{SOI} is small, the barrier potential becomes the main cause of electron confinement, but as t_{SOI} increases, the triangular potential caused by the electric field becomes the primary factor for electron confinement. Therefore, when t_{SOI} is small, nonlinearity is confirmed because the effective well width changes as it transitions from well confinement to electric-field confinement. Additionally, comparing ΔE_{Γ} and ΔE_{X} in Figs. 5(a) and 5(b), ΔE_{X} is much larger than ΔE_{Γ}. This is because the shear strain is set to a large value and the Δk of each valley at the Γ and X points described above, where Δk is much closer to the X point.

Figure 5(c) shows the F_{SOI} dependence on each shear strain of the overall valley splitting, which is the sum of the valley splitting due to the Γ and X points expressed in Eq. (1). For a near zero electric field, valley splitting is strongly affected by the valley splitting through the X point and it exhibits a nonlinear change with respect to the electric field, but basically the size of the valley splitting is simply proportional to the shear strain.

Figure 6 shows valley splitting overlaid on a contour plot with shear strain chosen to fit the experiment. Although nonlinearities are noticeable in the theoretical value near the zero electric field, the experimental and theoretical values for 6 and 9 nm are in relatively good agreement. If a similar fitting is performed with valley splitting through only the Γ point, the electric field exceeds 1.15 GV/m, which is much larger than for the breakdown field of SiO_{2.}^{32} This would not be consistent with the experiment. We suppose that nonlinearity is caused by the transition of the wave function from the unstrained region to the strained region. We assume that a strained region exists at the BOX interface. For small positive values of V_{BG} from 0 V, the wave function transitions from the unstrained region to the strained BOX interface. Therefore, nonlinearity appears due to transition from the Γ point to X point induced valley splitting. Figure 6 shows that introducing a strain along [110] of 4.5% at t_{SOI} = 6 nm and 5% at t_{SOI }= 9 nm as the shear strain agrees well with the experiment results, indicating that shear strain along [110] near the BOX interface is promising as the origin of large valley splitting. This strain value is very large from a general strain viewpoint, but this would not cause silicon to fracture.^{33,34}

## VIII. DISCUSSIONS

Here, we discuss the validity of considering strain as the origin of the large valley splitting. The results obtained by Niida *et al.,*^{35} who measured the mobility of MOSFETs with both polarity (p/n) contacts fabricated on SIMOX substrates subjected to high-temperature annealing similar to the conditions presented herein, revealed the following characteristics. They found that the electron mobility decreased and conversely the hole mobility increased under the condition where electrons and holes were squeezed at the SOI/BOX interface compared with the condition where both carriers were squeezed at the SOI/thermally grown SiO_{2} interface (FOX). According to Refs. 36 and 37, the application of compressive strain along [110] on silicon (001) results in a decrease in electron mobility and an increase in hole mobility in [110] channel MOSFETs. This behavior aligns with the electron and hole mobility observed by Niida *et al.* at the SOI/BOX interface. Since the mobility can vary due to various factors such as interface quality and impurity concentration, it is difficult to compare mobility by itself. However, the agreement between the Ohkawa theory and experiments, and the consistency of the changes in both electron and hole mobility when [110] directional compressive strain is applied suggest that the [110] directional compressive strain near the BOX interface is a promising candidate as the origin of large valley splitting. The origin of the massive strain near the BOX interface remains unclear, and further detailed investigation is needed to determine whether strain actually exists and, if so, its physical origin. Finally, we note that high reproducibility in the size of large valley splitting has been obtained among the multiple devices measured so far even among different wafers.

## IX. CONCLUSION

We demonstrated that large valley splitting observed in SIMOX substrates subjected to high-temperature long-duration annealing can be explained by the extended zone EMA proposed by Ohkawa *et al.* In the theory, valley splitting via the X point may play an important role and have a significant impact on transport phenomena in the presence of shear strain in the inversion layer of MOSFETs. Further analysis based on this theory shows that the experimental large valley splitting is well reproduced when a shear compressive strain of approximately 4%–5% along [110] is introduced into the SOI layer at the BOX interface.

## ACKNOWLEDGMENTS

We thank Professor Y. Tokura (Tsukuba University) and Professor H. Kageshima (Shimane University) for their helpful discussions.

## AUTHOR DECLARATIONS

### Conflict of Interest

The authors have no conflicts to disclose.

### Author Contributions

**Jinichiro Noborisaka:** Conceptualization (lead); Data curation (lead); Formal analysis (lead); Investigation (lead); Methodology (lead); Resources (lead); Software (lead); Validation (lead); Visualization (lead); Writing – original draft (lead); Writing – review & editing (lead). **Toshiaki Hayashi:** Conceptualization (equal); Formal analysis (supporting); Investigation (supporting); Validation (supporting); Writing – original draft (supporting); Writing – review & editing (supporting). **Akira Fujiwara:** Validation (supporting); Writing – original draft (supporting); Writing – review & editing (supporting). **Katsuhiko Nishiguchi:** Funding acquisition (lead); Project administration (lead); Resources (supporting); Supervision (lead); Writing – original draft (supporting); Writing – review & editing (supporting).

## DATA AVAILABILITY

The data that support the findings of this study are available from the corresponding author upon reasonable request.

## REFERENCES

**21**, 337 (1966).