Prospects for memristors with hysteretic memristance as so-far missing core hardware element for transfer-less data computing and storage

A large part of the energy consumed by ICT systems in von-Neumann architecture is required for the continuous data transfer between separated memory and processor units.^1,2 The first ICT systems in von-Neumann architecture consisted of vacuum tubes as the processor unit and magnetic core memory as the memory unit [Fig. 1(a)]. Our current ICT systems in von-Neumann architecture consist of transistors as processor units and random access memory (RAM) as memory units [Fig. 1(b)]. The theoretically predicted ICT system in neuromorphic computer architecture merges the processor unit and the memory unit [Fig. 1(c)] and is expected to process and store data transfer-less. In this work, we discuss the perspectives for non-volatile memristors with hysteretic memristance as the core hardware element for neuromorphic computer architecture.

First, we will have a closer look at the transport characteristics, e.g., current–voltage curves, of processor units in von-Neumann computers, namely, of vacuum tubes [Fig. 1(a)] and transistors [Fig. 1(b)]. For a linear signal input, the signal output of such processor units is strongly distinguishable, and hence, they are used as basic building blocks in the arithmetic logic unit of von-Neumann computers. The I–V curves of such processor units are non-linear and pass through the origin, implying that they do not primarily store energy. However, the signal output is lost when the operation power of such processor units is switched off before storing the signal output in the memory unit. Therefore, requirements for the core hardware element for merged memory and processor units in neuromorphic computers are non-linear current–voltage curves and storage of the signal output as an internal state parameter in this core hardware element [Fig. 2(c)]. The material, BiFeO₃ (BFO), for such a core hardware elemen, was found in 2011.³ The storage of the signal output as the internal state parameter in a BFO-based core hardware element was reported in 2014⁴ and implementation of the activation function at the synapses level was reported in 2015.⁵ The BFO-based core hardware element belongs to the memristor class of passive hardware elements and reveals a hysteretic memristance.⁶ 

A memristor is a passive electronic component that has the ability to change its resistance in response to an applied voltage (voltage-driven) or in response to the current that flows through the component (current-driven).⁷ In this work, we focus on memristors that are commonly referred to as resistive random access memory (ReRAM) devices.

The purpose of this article is to discuss the transport properties of different memristors to better understand why memristors with linear I–V characteristic curves and non-hysteretic memristance can only be used as memory units, and why memristors with non-linear I–V characteristic curves and hysteretic memristance can be used both as a processor and a memory unit, without data transfer during computation. Typically, memristors are non-volatile, reconfigurable resistive switches that are composed of a poorly conducting dielectric thin film with a conducting metallic top and a bottom electrode attached. So far, available memristors only enable data storage. Using Ohm's law and Kirchhoff's law electronic circuits with arrays manufactured from memristors with linear I–V curves and non-hysteretic memristance,^8, in situ vector–matrix multiplication, e.g., for image processing, has been demonstrated.⁹ However, in comparison to the not-memory-bound vector–matrix multiplication, the memory-bound matrix–matrix multiplication, e.g., for many high-performance computing and machine learning applications, requires memristors that enable data processing and data storage in the same device to overcome the memory bottlenecks in traditional von-Neumann computer architectures, where processor and memory are separated. In this work, it is shown that only memristors with non-linear I–V curves³ and hysteretic memristance can process and store data in the same device⁴ and that only such memristors fulfill the requirements of the so-far missing core hardware element for resource-saving neuromorphic computers, not only for the not-memory-bound vector–matrix multiplication but also for the memory-bound matrix–matrix multiplication.

Memristors are classified according to the form of the state-dependent Ohm's law in extended, generic, and ideal memristors.¹⁰ For example, according to this classification, memristors with a linear I–V curve Figs. 2(a)–2(c)] or memristors with a non-linear I–V curve [Fig. 2(d)] may be classified in extended and generic or in ideal memristors, respectively.

From here on, we refer to memristors with a linear I–V curve at the origin of the coordinate system as linear memristors [Figs. 2(a)–2(c)] and memristors with a non-linear I–V curve at the origin of the coordinate system as non-linear memristors [Fig. 2(d)]. Strukov et al. discovered the TiO₂-based, linear memristor.¹¹ Since then, many other groups reported on different types of linear memristors.^12–24 Up to our knowledge, there were first reports on non-linear memristors in 2011 on the BFO-based memristor³ and in 2016 on the CoO_x-based memristor.²⁵ 

The BFO-based and the CoO_x-based memristors reveal a large endurance; however, retention requirements of nonvolatile electronic memory devices are only fulfilled by the BFO-based memristors.²⁶ The retention of CoOx-based memristors decays spontaneously on a timescale of 20 ms or under the disturbance of reading voltage pulses.²⁵ Only recently, the non-linear, two-dimensional MoS₂-based memristor with an infinitely large initialization time of the internal state parameters has been presented.²⁷ The initialization of the non-linear, BFO-based memristor³ can be ultrashort²⁸ and has been recently described by a physical model.²⁹ We discuss the effect of initialization on internal state parameters later [Fig. 3(d)]. Reported decay of retention²⁵ or infinitely large initialization time of the internal state parameter²⁷ limits the use of such memristors as a core hardware element in merged memory and processor units in neuromorphic computers. The central difference between extended and generic memristors with linear I–V curves at the origin of the coordinate system, with non-hysteretic memristance and of ideal memristors with non-linear I–V curves at the origin of the coordinate system, and with hysteretic memristance can be understood from the criteria derived by Professor Leon O. Chua^7,10,30 to describe the transport properties of memristors.

1. The electrical transport properties of the memristors are characterized using current–voltage measurements.

2. The distinctive memristor property is a frequency-dependent pinched-hysteresis loop in the current–voltage domain under zero-mean periodic input.

3. The memristance M and memductance G states of an extended memristor are described by a function M = M(q, x, I) with current momentum q, internal state variables x, current I, and by G = G(ϕ, x,V) with voltage momentum ϕ, internal state variables x, and voltage V, respectively.

4. The memristance M and memductance G states of a generic memristor are described by a function M = M(q, x) with current momentum q and internal state variables x and by G = G(ϕ, x) with voltage momentum ϕ and internal state variables x, respectively.

5. The memristance M and memductance G states of an ideal memristor are described by a single scalar function M = M(q) with the current momentum q and G = G(ϕ) with the voltage momentum ϕ, respectively. The single scalar function M = M(q) is related to hysteretic memristance.

The fact that a memristor cannot be realized by any simple combination of the three basic circuit elements (R, L, and C) proves that the memristor is actually a fundamental circuit element.³¹ As pointed out by Corinto et al.,³⁰ “it must be understood that the current momentum does coincide with a stored electric charge only in case of a capacitor, the voltage momentum with a magnetic flux only in case of an inductor. Since the memristor has nothing to do with such circuit elements, the use of current momentum and voltage momentum is suitable to avoid misunderstanding, although charge q and flux ϕ my be occassionally used for the sake of brevity.”

The central difference between extended and generic memristors with linear I–V curves at the origin of the coordinate system and ideal memristors with non-linear I–V curves at the origin of the coordinate system prelies in the function describing memristance M and memductance G.^10,30 The functions M and G of non-linear memristors only depend on current momentum q [M = M(q)] and voltage momentum ϕ [G = G(ϕ)], respectively.

In the following, two behavioral characteristics of memristors are discussed based on their IV characteristics with four branches.

A continuum-memory memristor can assume all resistance values between the high resistance state (HRS) and the low resistance state (LRS) in a non-volatile manner, regardless of whether the resistance value of the memristor is changed from the HRS to the LRS or from the LRS to the HRS. Non-linear memristors have a continuum of nonvolatile memory states and act as an analog nonvolatile memory. On the other hand, discrete-memory memristors can assume only a discrete number of resistance values in a non-volatile manner. Linear memristors have a discrete number of nonvolatile memory states, e.g., the HRS and the LRS or the HRS and the LRS, and many additional resistance values in between,^23,24 and act as digital or multilevel nonvolatile memory.

Nowadays, the continuum-memory behavior of biological synapses is emulated by memristors.⁵ If linear memristors are used as artificial synapses in neuromorphic chips, the discrete-memory behavior of linear memristors must be compensated as best as possible by additional software and even hardware. However, this is only partially successful. If, on the other hand, non-linear memristors with their continuum-memory characteristics are used as artificial synapses in neuromorphic chips, no additional software and hardware will be needed to compensate for the non-idealities of discrete memory.

Linear memristors have static internal state variables at the origin of the I–V coordinate system and more and more dynamic internal state variables away from the origin of the I–V coordinate system. On the other hand, non-linear memristors have static state variables x in two full branches and dynamic state variables x in the other two full branches.²⁹ The branches with static state variables x are the two read branches and the branches with dynamic state variables x are the two write branches. This uniquely allows to time separate read and write operations in non-linear memristors and to operate non-linear memristors as memory and processor units in the same cell without data transfer. In the following, we analyze the hysteretic I–V characteristics with a linearly ramped voltage of different memristors with a linear I–V curve at the origin of the coordinate system and the BFO-memristor with a non-linear I–V curve at the origin of the coordinate system with regard to their ability to store and process data in the same memristor cell.

Typically, memristors are reconfigured above a current or voltage threshold value and the state of the resistive switch is read out far below a current or voltage threshold value, e.g., at the red and blue semicircles shown in Fig. 2. Compared to linear memristors with (B) filamentary and (C) structural switching, the non-linear memristors do not have such a threshold, i.e., the state of the non-linear memristor can be read out at any current or voltage value on one of the two read branches and in the small current or bias range of the two write branches of the hysteretic current–voltage (I–V) curves.²⁹ 

We discuss linear, ferroelectric [Fig. 2(a)], filamentary [Fig. 2(b)], and phase-change [Fig. 2(c)] memristors. Typically, linear memristors are reconfigured above a current or voltage threshold value and the state of the linear memristor is read out below a current or voltage threshold value [Figs. 2(a)–2(c)]. Linear memristors are not suitable as core hardware components for merged memory and processor units in neuromorphic computers, since they can only store but not process data. Compared to linear memristors, non-linear memristors do not have such a reconfiguration threshold. As will be explained in the following, non-linear memristors have dynamic and static internal state variables in the two full write branches and the two full read branches, respectively. This uniquely allows the readout of the resistance state of the non-linear memristor in the two complete read branches of the current–voltage characteristics [branch 2 and branch 4 in Fig. 2(d)]. Understanding this allows to operate non-linear memristors as memory and processor units in the same cell without data transfer and—as a long-term goal—to implement such non-linear memristors as core hardware elements in resource-efficient neuromorphic computers. This might also open—as a short-term goal—new avenues for performance improvement of devices in edge computing, edge sensorics, and secure electronics. The switching behavior of reconfigurable resistive switches with a conducting metallic top bottom electrode is typically analyzed by current–voltage measurements. In the following, we analyze the possible operation of linear and non-linear memristors. The current–voltage curves can be recorded in both current-driven and voltage-driven modes. For example, in the voltage-driven mode, voltage can be applied to the top electrode and the bottom electrode can be grounded. Then, the voltage is changed successively. For convenience, we will number the branches on the current–voltage curve of memristors (Fig. 2), e.g., branch 1 from 0 V to +V_max, branch 2 from +V_max back to 0 V, branch 3 from 0 V to −V_max, and branch 4 from −V_max back to 0. The current–voltage curve of a memristor exhibits hysteresis in the positive voltage range, if the current in branch 1 and the current in branch 2, which are measured at the same positive voltage, are different. The current–voltage curve of the memristor exhibits hysteresis in the negative voltage range, if the current in branch 3 and the current in branch 4, which are measured at the same negative voltage, are different. If the current–voltage characteristic remains unchanged after repeated cycling, this is the first indication of the high endurance of memristive switches. Reliable endurance measurement methods³² with fast initialization of equilibrium resistance state will accelerate the integration of reconfigurable resistive switches in commercial products.

When storing data, memristors differ in their switching behavior [see Figs. 2(a)–2(c)]. If an appropriate write voltage is applied, then the internal state variables of ferroelectric [Fig. 2(a)], filamentary [Fig. 2(b)], structural [Fig. 2(c)], and linear memristors are constant, and current–voltage characteristics can be described either using branches 4 and 1 or branches 2 and 3. The resistance state of the linear memristors is read out by applying a read voltage. The read voltage and the corresponding read current in branches 4 and 1 as well as branches 2 and 3 are represented exemplarily by blue and red semicircles, respectively (Fig. 2). The read voltage must be selected so small that the internal state parameter is not changed when reading. The range of possible read voltages and corresponding read currents in branches 4 and 1 as well as branches 2 and 3 is indicated by blue and red lines, respectively. Interestingly, for a ferroelectric linear memristor [Fig. 2(a)] and for a barrier non-linear memristor [Fig. 2(d)], the read current depends on the polarity of the write and the read current. For the ferroelectric linear memristor [Fig. 2(a)], the read voltage must be chosen to be quite large, since no current flows with a small read voltage around 0 V. Therefore, every readout results in a small change of internal state variables of the ferroelectric linear memristor (so-called read disturbs) and a read disturb-aware write operation has to be applied. For the barrier non-linear memristor [Fig. 2(a)], the read voltage in branches 1 and 3 is chosen typically small; however, the read voltage in branches 2 and 4 can be chosen over the full voltage range without changing the internal state variables.

In a digital memory, it is sufficient to store two states, the high resistance state (HRS) and the low resistance state (LRS). The states of such digital memories are retained until a write voltage is applied again, thus changing the state of the memory. For example, if a positive and a negative read voltage are selected and if the linear memristor is in the HRS, then the read current is small [blue semicircle on branch 1 and blue semicircle on branch 4 in Figs. 2(b) and 2(c)]. If a positive and a negative read voltage are selected and if the linear memristor is in the LRS, then the read current is large [red semicircle on branch 2 and red semicircle on branch 3 in Figs. 2(b) and 2(c)]. On the other hand, if a positive and a negative read voltage are selected and if the non-linear memristor is in branch 4 or branch 1, then the read current is large [blue semicircle on branch 4 in Fig. 2(d)] or the read current is small [black semicircle on branch 1 in Fig. 2(d)]. If a positive and a negative read voltage are selected and if the non-linear memristor is in branch 2 or branch 3, then the read current is large (red semicircle on branch 2 in Fig. 2(d)] or the read current is small [black semicircle on branch 3 in Fig. 2(d)].

In the evaluation as a resistive random access memory (ReRAM) device, attention is first directed to how large is the difference between the read current, and, thus, the resistance ratio between resistance in the HRS and resistance in the LRS. Programming cycles ≥ 0.5 × 10⁶ can be used industrially at least in the temperature range between 0 and 80 °C. The retention describes how long the HRS and the LRS can be kept by the memristive switch. Values ≥10 years, at least in the temperature range between 0 and 80 °C, can be used industrially. Established retention and endurance measurements and a first analysis of the current–voltage curve of a resistive switch yield the benchmark parameters for comparison with commercially available resistive switches, e.g., of resistive random access memory (ReRAM) devices that store information by changing the electrical resistance of a poorly conductive dielectric between the top electrode and the bottom electrode. If the ReRAM has its maximal resistance R_OFF, it is in the high resistance state (HRS) and if the ReRAM has its minimal resistance R_ON, it is in the low resistance state (LRS). For classic ReRAM components, R_OFF/R_ON should be greater than 10, retention should be larger than 10 years, and endurance larger than 10⁶. The R_OFF/R_ON ratio of ferroelectric linear memristors (R_OFF/R_ON= 10⁰…10¹),^13,21–23 is smaller than the R_OFF/R_ON ratio of structural linear memristors (R_OFF/R_ON= 10²…10³)^16–19 and of filamentary linear memristors (R_OFF/R_ON= 10²…10⁵).^{12,14–15,24} The R_OFF/R_ON ratio of non-linear memristors (R_OFF/R_ON= 10¹…10³)^{5,26–27,33–39} is comparable to the R_OFF/R_ON ratio of filamentary and structural linear memristors. Only for the non-linear memristor does the read current depend on the polarity of the write voltage and the read voltage. On the other hand, the read current of a linear memristor (except ferroelectric linear memristors with read disturbs) depends only on the polarity of the write voltage and not on the polarity of the read voltage.

1. The first important feature of a non-linear memristor is certainly the programming with positive and negative write voltages, but, in particular, different read currents with positive and negative read voltages. This is also called barrier switching which enables the operation as one of the 16 Boolean logic gates, since two variables are available for implementation with positive and negative read voltages.⁴ 

2. Another important feature is the write voltage range in which the internal state variables of a memristor can be programmed to the maximum and the minimum read current. The larger the corresponding read current range, the more internal state variables can be stored.

3. Filamentary or structural linear memristors do not fulfill feature (1), which can be seen from the crossing hysteretic I–V curves [Figs. 2(b) and 2(c)] in comparison to tangential hysteretic I–V curves [Fig. 2(d)].

The memristance M of the [Fig. 3(c)] linear and [Fig. 3(d)] non-linear memristors is described by M = M(q, x, I) with current momentum q, internal state variables x, and current I, and by a single scalar function M = M(q) with current momentum q, respectively. For the [Fig. 3(c)] linear memristor, there exists no one-to-one relationship between current momentum q(t) and voltage momentum ϕ(t). For the [Fig. 3(d)] non-linear memristor, there exists a one-to-one relationship between current momentum q(t) and voltage momentum ϕ(t) = ϕ(q(t)). This can be seen from the hysteretic memristance [Fig. 3(d)].

The ϕ–q curve of the linear memristor is non-hysteretic [Fig. 3(c)]. Its slope is constant in the small bias range and its slope changes continuously in the large bias range. This means that the internal state variables of a linear memristor continuously change in the large bias range. For every time point on the time scale t = t₁ on branch 1 and memristance M(q(t₁), ϕ(q(t₁))), another time point t = t₂ on branch 2 and memristance M(q(t₂),ϕ(q(t₂))) can be found for which applies M(q(t₁),ϕ(q(t₁))) = M(q(t₂),ϕ(q(t₂))). Also, for every time point on the time scale t = t₃ on branch 3 and memristance M(q(t₃),ϕ(q(t₃))), another time point t = t₄ on branch 4 and memristance M(q(t₄),ϕ(q(t₄))) can be found for which applies M(q(t₁),ϕ(q(t₃))) = M(q(t₁),ϕ(q(t₄))). From this, it can be followed that for no time point, it is possible to distinguish between the internal state variables of the linear memristor with memristance from branch 1 and branch 2 or between the internal state variables of the linear memristor with memristance from branch 3 and branch 4 [Fig. 3(c)].

On the other hand, the ϕ–q curve of the non-linear memristor is hysteretic [Fig. 3(d)] and changes its slope continuously in the two write branches, namely, in branch 1 and in branch 3, and has a constant slope in the two read branches in the small and the large bias ranges.

Only for a single time point on the time scale t = t₁ on branch 1 and memristance M(q(t₁), ϕ(q(t₁))), another time point t = t₂ on branch 2 and memristance M(q(t₂),ϕ(q(t₂))) can be found for which applies M(q(t₁), ϕ(q(t₁))) = M(q(t₂), ϕ(q(t₂))). This is at V(t = t₁ = t₂) = +V_max [Fig. 3(d)]. Also, only for a single time point on the time scale t = t₃ on branch 3 and memristance M(q(t₃), ϕ(q(t₃))) another time point t = t₄ on branch 4 and memristance M(q(t₄), ϕ(q(t₄))) can be found for which applies M(q(t₃), ϕ(q(t₃))) = M(q(t₄), ϕ(q(t₄))). This is at V(t = t₃ = t₄) = −V_max [Fig. 3(d)]. From this, it can be followed that for every time point, except at the time point t = t₁= t₂ and at the time point t = t₃ = t₄, it is possible to distinguish between the internal state variables of the non-linear memristor [Fig. 3(d)]. Furthermore, because the memristance is constant in branch 2 and branch 4, we call branch 2 and branch 4 “read branches,” and because the memristance is continuously changing in branch 1 and branch 3, we call branch 1 and branch 3 “write branches.” We used this concept to extract internal state variables from the current–voltage curves of a non-linear memristor.²⁹ We assumed that the internal state variables are static and dynamic in the two full read branches and the two full write branches, respectively. Furthermore, extracted internal state variables are the same at the time point t = t₁ on the write branch 1 and at the time point t = t₂ on the read branch 2 with V(t = t₁= t₂) = +V_max where memristance is the same, i.e., M(q(t₁), ϕ(q(t₁))) = M(q(t₂), ϕ(q(t₂))), and extracted internal state variables are the same at the time point t = t₃ on the write branch 3 and at the time point t = t₄ on the read branch 4 with V(t = t₃ = t₄) = −V_max where memristance is the same, i.e., M(q(t₃), ϕ(q(t₃))) = M(q(t₄), ϕ(q(t₄))). The static and dynamic internal state variables of non-linear memristors can be used to implement operations on non-linear memristors representing linear, non-linear, and even transcendental, e.g., exponential or logarithmic, input–output functions.

The future implication of the presented findings is closely linked to the computability of a problem, i.e., to the existence of an algorithm to compute the input–output maps of computable functions in finite time. According to Boche et al.,^40,41 computing and processing paradigm needs to change so that more efficient but equally powerful computations can be carried out. In computational theory, the Turing machine is a computational model to describe calculations over a (finite) rational number of states with unlimited memory and time at its disposal and the Blum–Shub–Smale (BSS) machine is a computational model to describe calculations over an (uncountable) real number of states with registers that can store arbitrary real numbers and compute rational functions over reals in a single time step. So far, there exist no computational models to describe calculations over (uncountable) real numbers of states with registers that can store arbitrary real numbers and compute transcendental, e.g., exponential or logarithmic, functions over reals in a single time step. Because non-linear memristor devices are expected to perform computing of the input–output maps of transcendental functions in a single time step without intermediate data storage, it is proposed to incorporate non-linear memristor devices into the computing pipeline as registers. The memristance of the non-linear memristor-based registers can be written in the write branches 1 and 3 and read in the read branches 2 and 4.

To summarize, non-linear memristors are promising as the so-far missing core hardware for resource-saving neuromorphic computers. Their behavior is similar to that of a synapse in the brain, a component with memory value. Novel microelectronic circuits with non-linear memristors will allow for digital and analog data processing in real-time and in a certifiable manner in the same device without data transfer, whereby transparent, repeatable, and trustworthy data processing algorithms are performed in hardware. As an exemplary embodiment for non-linear memristors, we analyzed the hysteretic current–voltage (I–V) curves and hysteretic voltage momentum–current momentum (ϕ–q) curves of the BiFeO₃ (BFO)-based, non-linear memristors³ and compared it with the hysteretic current–voltage (I–V) curves and non-hysteretic voltage momentum–current momentum(ϕ–q) curves of the TiO₂-based, linear memristors.¹¹ The BFO-based, non-linear memristor has two write branches and two read branches with dynamic and static internal state variables, respectively. Only the non-linear memristor fulfills the requirements of the core hardware for resource-saving neuromorphic computers. Furthermore, because non-linear memristor devices are expected to perform computing of the input–output maps of transcendental functions in a single time step, it is proposed to incorporate non-linear memristor devices as registers in neuromorphic computers that can compute transcendental, e.g., exponential or logarithmic, functions over reals in a single time step.

I wish to thank my former and actual team members who continuously developed the BFO-based, non-linear memristors for edge computing, edge sensorics, and secure electronics. For this work, I mainly wish to thank Professor Bernd Ulmann from FOM Hochschule für Oekonomie and Management for motivating the development of nonlinear analog hardware for analog computers, Dr. Thomas Wille and Dr. Ruth Houbertz for discussing the unique specifics of the BFO-based, non-linear memristors compared to linear memristors, and Professor Holger Boche, Professor Gitta Kutyniok, and Adalbert Fono from TU München for pointing out the importance of developing analog hardware to realize computability of the input–output maps of transcendental functions. I wish to thank the Federal Agency for Disruptive Innovation (SPRIN-D) for promoting this work as part of a validation order.

The author has no conflicts to disclose.

Heidemarie Schmidt: Conceptualization (equal); Data curation (equal); Formal analysis (equal); Funding acquisition (equal); Investigation (equal); Methodology (equal); Validation (equal); Visualization (equal); Writing – original draft (equal); Writing – review & editing (equal).

The data that support the findings of this study are available from the corresponding author upon reasonable request.