Metal oxide transistors have garnered substantial attention for their potential in low-power electronics, yet challenges remain in achieving both high performance and low operating voltages through solution-based fabrication methods. Optimizing interfacial engineering at the dielectric/semiconductor interface is of utmost importance in the fabrication of high-performance thin film transistors (TFTs). In the present article, a bilayer Ti3C2Tx-MXene/SnO2–semiconductor (Tx stands for surface termination) configuration is used to fabricate a high-performance n-type thin film transistor by using an ion-conducting Li-Al2O3 gate dielectric on a p+-Si substrate, where electrical charges are formed and modulated at the Li-Al2O3/SnO2 interface, and Ti3C2Tx-MXene nanosheets serve as the primary electrical charge channel due to their long lateral size and high mobility. A comparative characterization of two distinct TFTs is conducted, one featuring Ti3C2Tx MXene and SnO2 semiconductor layer and the other with SnO2 only. Notably, the TFT with the Ti3C2Tx MXene layer has shown a significant boost in the carrier mobility (10.6 cm2/V s), leading to remarkable improvements in the on/off ratio (1.3 × 105) and subthreshold swing (194 mV/decade), whereas the SnO2 TFT without the Ti3C2Tx MXene layer shows a mobility of 1.17 cm2/V s with 8.1 × 102 on/off ratio and 387 mV/decade subthreshold swing. This investigation provides a possible way toward the development of high-performance, low-voltage TFT fabrication with the MXene/semiconductor combination.

Over the past few decades, advancements in semiconductor technology have significantly shaped our modern way of life, revolutionizing fields such as computing, telecommunications, and consumer electronics.1 Central to these innovations are transistors, the fundamental building blocks of electronic circuits, which control the flow of electrical signals and enable the amplification and switching of electronic signals.2 The relentless pursuit of enhancing electronic device performance and functionality has driven researchers to explore unique materials and innovative device architectures. As the demand for faster, more energy-efficient and miniaturized electronics continues to rise, conventional semiconductor technologies face challenges in meeting these ever-increasing requirements. In addition, advancements in metal oxide synthesis have enabled the fabrication of oxide TFTs on a large scale and using a roll-to-roll fabrication method. Metal-oxide TFTs utilizing conventional SiO2 required high operating voltages (≥20 V) owing to the relatively low dielectric constant (κ) exhibited by SiO2.3 This characteristic renders them unsuitable for most applications, such as lightweight portable electronics. This problem has been significantly alleviated with the development of various high-dielectric (high-κ) gate insulators. These insulators not only decrease the operating voltage of the device but also enhance the carrier mobility compared to the conventional SiO2 dielectric.4 Consequently, there is a pressing need to discover alternative materials and integrate them into advanced device designs to overcome these limitations.

In recent years, 2D materials have emerged as promising candidates for realizing next-generation electronic devices due to their unique and extraordinary properties.5 Among them, graphene has garnered significant interest due to its exceptional electronic properties, such as high electron mobility and high carrier saturation velocity.6 While graphene holds promise for various applications, there are several challenges and limitations that have hindered its widespread adoption and commercialization.7 Graphene is a zero-bandgap material, meaning it lacks an energy gap between the valence and conduction bands.8 This characteristic leads to a low on/off current ratio, making it challenging to completely turn off the transistor and achieve precise control over the flow of charge carriers.9 Without a bandgap, graphene transistors suffer from poor current saturation, limiting their application in digital logic circuits.10 The absence of a bandgap also limited switching performance and higher power consumption in digital applications.11 Recently, MXenes, a family of layered 2D transition metal carbides and nitrides, have gained remarkable attention for their exceptional electrical conductivity, mechanical strength, and chemical stability.12 The general formula of MXene is Mn+1XnTx (n = 1–3), where M denotes a transition metal, e.g., Ti, Cr, or Mo; X represents carbon or nitrogen; and Tx symbolizes a surface termination such as –F, –OH, or –Cl. Owing to their outstanding mechanical, biological, and electrical properties such as efficient electromagnetic interference (EMI) shielding, large surface-to volume ratio, extraordinary electrical conductivity, water dispersibility, high energy capacity, and excellent antibacterial activity, this newly discovered category of materials are important in a wide range of different areas of research.13–16 Among various MXenes, titanium carbide, Ti3C2Tx, stands out as one of the most extensively studied members due to its intriguing electronic properties and ease of synthesis.17 Introducing functional groups (–F, –Cl, –OH, etc.) on the surface of Ti3C2Tx MXene can lead to changes in its electronic structure, including bandgap engineering.18 The fascinating electrical behavior of Ti3C2Tx MXene, coupled with its ultrathin nature, opens up unprecedented opportunities for unique device architectures. The utilization of these properties of 2D materials were explored with other oxide materials to enhance the TFT properties along with different applications.19–22 Liu et al. reported the enhanced performance of ZnO/graphene TFT (Ion/Ioff = 1.68 × 107 and μ = 18.21 cm2/V s) in comparison to only ZnO as a channel (Ion/Ioff = 1.53 × 106 and μ = 7.35 cm2/V s) on the SiO2 substrate.19 Chen et al. reported strain-gated field effect transistors of a MoS2–ZnO hybrid structure. According to their report, at a 6.25 MPa applied stimulus on a device, the source–drain current can be tuned for ∼25%, equivalent to the results of applying an extra −5 V back gate voltage.20 Gottam et al. reported MoS2 nanosheet-coated ZnO thin films for hydrogen gas sensing applications, and the response rate for 100 ppm H2 gas was 7 s, and the recovery rate was 23 s at 250 °C with extremely high error-free repeatability.22To further elevate the performance and functionality of MXene-based transistors, integration with high-performance semiconducting materials is an imperative research direction. In this context, tin dioxide (SnO2), a well-established metal oxide semiconductor, has recently emerged as a strong contender due to its wide bandgap, high electron mobility, and excellent thermal stability.23 Researchers already explored the combination of SnO2 and MXene for boosting the charge transport in solar cell applications.24 Apart from this, this combination was also utilized to enhance the performance of gas sensors at room temperature.25 The synergistic combination of ultrathin Ti3C2Tx MXene and SnO2 as the semiconductor layer can be a highly promising avenue for realizing transistors with enhanced electronic characteristics.

Against this backdrop, the present research article offers a comprehensive investigation into the design, fabrication, and performance evaluation of an ultrathin Ti3C2Tx MXene-based metal oxide transistor utilizing SnO2 as the semiconductor layer and Li–Al2O3 as by using an ion-conducting gate dielectric. The Ti3C2Tx MXene nanosheets were used as primary electrical charge channels due to their large lateral size and high mobility, while the formation and modulation of electrical charge occurred at the Li–Al2O3/SnO2 interface. This device possessed significantly improved n-type TFT performance, including mobility, on-state current, on/off ratio, and subthreshold swing (SS). We systematically investigated the distribution of MXene nanosheets to fabricate a high-performance MXene/n-type semiconductor transistor. In summary, this research article endeavors to contribute significantly to the field of advanced electronic devices by presenting an innovative hybrid approach that capitalizes on the exceptional properties of Ti3C2Tx MXene and SnO2. By shedding light on the synergistic effects of their integration, this work aims to pave the way for the development of next-generation transistors with enhanced electronic performance, ushering in a new era of electronics and propelling technological progress across diverse domains.

The entire process of fabricating TFTs involves the preparation of different precursor solutions to synthesize the required materials. For the synthesis of the dielectric precursor solution, a mixture of aluminum nitrate nonahydrate and lithium acetate, with concentrations of 500 mM, is dissolved individually in 2-methoxyethanol (2-ME). The solutions are then combined in a 1:11 volume ratio of Li to Al and stirred for 6 h. The detailed synthesis of dielectric and its characterization can be found in our earlier literature.26 The synthesized dielectric shows the amorphous nature, which is already confirmed via GIXRD (Fig. S2 in the supplementary material). For the active layer, the semiconductor precursor solution is prepared using tin chloride (Sigma Aldrich) as the precursor salt with a concentration of 100 mM. It is vigorously dissolved in 2-methoxyethanol (2-ME) for 1 h. The final solution is aged for 48 h before being used for device fabrication.

The Ti3C2Tx MXene was chosen from among all of the potential MXenes for a number of reasons, including the fact that it is very stable in a wide variety of conditions and has a high electrical conductivity. Ti3C2Tx MXene was synthesized by the selective etching of aluminum (Al) from Ti3AlC2, which led to its formation. In order to accomplish the etching process, 0.8 g of LiF was mixed with 10 ml of 12 M HCl while being stirred with a Teflon magnetic stir bar. The solution received a measured quantity of 0.5 g of Ti3AlC2 that was mixed in it very gradually over the period of a few minutes. At room temperature, the solution was stirred continuously for a period of 24 h. After the allotted etching time had elapsed, the mixture was centrifuged and rinsed with de-ionized water until the pH level reached close to 6. A colloidal solution of delaminated Ti3C2Tx flakes was obtained by adding multilayered Ti3C2Tx to de-ionized water and then the mixture was sonicated for 2 h. After that, the solution was centrifuged at 3500 rpm for 1 h, and the collected supernatant was used in the process of film fabrication. The details about synthesis and material characterization can be found in our earlier literature.27 The structural analysis of the MAX phase and synthesized MXene is already discussed in Fig. S1 in the supplementary material.

To fabricate oxide TFT having low-cost and easily processable, the sol–gel technique has been used with a top contact bottom gate device architecture. At the outset, a highly doped silicon (p+-Si) substrate, 1.5 × 1.5 cm2 size, was subjected to a cleaning process using a soap solution to eliminate macroscopic dust and physical contaminants from its surface.28 Subsequently, the substrates underwent ultrasonic treatment with DI water, acetone, and isopropyl alcohol (IPA) for 20 min each, effectively removing any adhering particles from the surface. After that, the substrate was dried by passing dry air and passed through an O2 plasma cleaner for 10 min, which makes the surface of the substrate hydrophilic, free from pinholes as well as trap states.29 We fabricated one Metal–Insulator–Metal (MIM) structure as shown in Fig. 1(a) for electrical characterizations of materials and two types of TFTs depending on the position of the Li–Al2O3 dielectric, Ti3C2Tx MXene, and tin oxide (SnO2) semiconductor layer as shown in Fig. 1(b) (TFT-1) and Fig. 1(c) (TFT-2). TFT 1 was fabricated through the following process: A Li–Al2O3 dielectric solution (0.5 M) was deposited onto the p+-Si substrate using spin coating at 5000 rpm for 50 s. The coated substrate was then placed on a preheated hotplate at 80 °C for 2 min to dry the dielectric film. For final annealing, the substrate was left in a preheated furnace at 350 °C for 30 min in ambient atmospheric conditions. This step converted the precursor solution into their respective oxides, and the process was repeated multiple times to achieve the desired thickness (∼94 nm) of the Li–Al2O3 dielectric thin-film. After the third coating, the Li–Al2O3 coated sample was annealed at 500 °C for 1 h to achieve a dense, stable, and highly amorphous phase of Li–Al2O3. Following the dielectric Li–Al2O3 coating, a tin oxide (SnO2) semiconductor precursor solution was coated (∼30 nm) on top of the Li–Al2O3 dielectric layer using the same procedure, maintaining 4000 rpm for 40 s and annealed in a preheated furnace at 500 °C for 1 h to achieve its crystalline phase. Finally, an aluminum (Al) electrode was deposited on top of the SnO2 layer using a thermal evaporator under a high vacuum (10−6 mbar) using a shadow mask technique that functions as the source and drains for the TFT. To enhance the mobility and on–off ratio of the TFT, an interdigitated mask with a width-to-length ratio (W/L) of 118 [channel length and width of 23.6 and 0.2 mm, respectively] was used to remove the overestimation in the mobility.30 This device, termed TFT 1, was utilized to measure capacitance and leakage current in a metal–insulator–metal (p+-Si/Li-Al2O3/Al) device structure, which was prepared using the same process and conditions. To fabricate TFT 2, the supernatant of Ti3C2Tx MXene (∼15 nm) was coated on top of the Li–Al2O3 layers at 1500 rpm for 40 s. The sample was then placed on a preheated hotplate at 100 °C for 30 min to dry the film, resulting in a homogeneous and compact Ti3C2Tx MXene layer. Afterward, the same procedure for SnO2 and electrode deposition has been used that was followed for TFT-1. The schematic of all the fabricated devices is shown in Fig. 1.

FIG. 1.

Schematic diagram of the (a) metal–insulator–metal (p+-Si/Li–Al2O3/Al) structure (device geometry used for leakage current density and capacitance measurements of the dielectric), (b) TFT 1, and (c) TFT 2 (device geometry used for all electrical characterizations of TFT 1 and TFT 2).

FIG. 1.

Schematic diagram of the (a) metal–insulator–metal (p+-Si/Li–Al2O3/Al) structure (device geometry used for leakage current density and capacitance measurements of the dielectric), (b) TFT 1, and (c) TFT 2 (device geometry used for all electrical characterizations of TFT 1 and TFT 2).

Close modal

Roughness measurements of various thin film surfaces were performed using an Atomic Force Microscope (AFM) known as NTMDTNTEGRA-prima. Frequency vs capacitance measurements of the thin-film samples has been performed using an LCR meter, specifically the Keysight Technology Model E4990A. All electrical characterization, TFT characterization, and leakage current measurements of the dielectric material have been carried out using a semiconductor device analyzer (Keysight B1400A). All the device characterization has been conducted under ambient/open atmosphere conditions.

The surface morphological analysis of the Li–Al2O3 dielectric and Ti3C2Tx MXene thin film was accomplished using Atomic Force Microscopy (AFM). The resulting micrographs of Li–Al2O3 dielectric thin films are presented in Figs. 2(a) and 2(b). The thin film of the Li–Al2O3 has been fabricated on the cleaned silicon (p+-Si) substrate, and the extracted root mean square roughness (RRMS) of the Li–Al2O3 thin film is 0.19 nm. This study indicates the amorphous nature of the Li–Al2O3 dielectric thin film. The reduced roughness of Li–Al2O3 results in fewer trap states, leading to a significant reduction in the subthreshold swing (SS) of TFTs.31 Furthermore, a dielectric with reduced roughness leads to less scattering of carriers, which results in enhanced carrier mobility. As a result, the Li–Al2O3 dielectric film offers advantages in achieving improved TFT performance.32  Figures 2(c) and 2(d) represent the surface morphology of Ti3C2Tx MXene thin film fabricated on the silicon (p+-Si) substrate. The extracted root mean square roughness (RRMS) of the Ti3C2Tx MXene thin film is 7.4 nm. This low level roughness of the Ti3C2Tx MXene thin film indicates that the interface with SnO2 may be beneficial to enhance the device performance due to fewer defects and trap state density.

FIG. 2.

AFM micrograph. (a) 2D and (b) 3D images of the Li–Al2O3 dielectric thin film on a silicon substrate (p+-Si/Li–Al2O3); (c) 2D and (d) 3D images of the Ti3C2Tx MXene thin film on a silicon substrate (p+-Si/Ti3C2Tx).

FIG. 2.

AFM micrograph. (a) 2D and (b) 3D images of the Li–Al2O3 dielectric thin film on a silicon substrate (p+-Si/Li–Al2O3); (c) 2D and (d) 3D images of the Ti3C2Tx MXene thin film on a silicon substrate (p+-Si/Ti3C2Tx).

Close modal
The UV–Vis measurements have been performed to check the transparency of the Ti3C2Tx-MXene/SnO2 bilayer and the details have been discussed in the supplementary information (Fig. S3 in the supplementary material). To investigate the dielectric characteristics of the Li–Al2O3 thin film, capacitance vs frequency (C–f) measurements were performed using a metal–insulator–metal (MIM) device structure (p+-Si/Li–Al2O3/Al), covering the frequency range from 20 Hz to 1 MHz, as shown in Fig. 3(a). As a general trend, the areal capacitance of a dielectric material tends to decrease with increasing frequency, which is commonly referred to as the dispersion relation of dielectrics.33 Specifically, at a frequency of 50 Hz, the measured areal capacitance was found to be 230 nF/cm2, highlighting the reliability of the Li–Al2O3 dielectric in TFTs at this operating frequency. However, at higher frequencies, the areal capacitance of the Li–Al2O3 thin film exhibited a sharp decline, which can be attributed to the depletion of accumulated Li+-ions. Moreover, for TFT applications, a higher areal capacitance (>SiO2) of the gate dielectric is essential to enable low operating voltages.34 Considering this, the Li–Al2O3 dielectric demonstrate promising potential for use as a gate dielectric in thin-film transistors.32 However, the effective capacitance value of this film is lower than that of the actual Li–Al2O3 dielectric film, which is due to the native oxide formation in the p+-Si/Li–Al2O3 interface during the annealing process of the dielectric and semiconductor. The effective total capacitance Ctotal can be obtained from the following equation:
1 C total = 1 C Li - A l 2 O 3 + 1 C Si O 2 ,
(1)
where C Li - A l 2 O 3 and C Si O 2 are the contribution to the total capacitance from the Li–Al2O3 and SiO2 film, respectively. The overall capacitance can be reduced significantly by exploiting the low dielectric constant of SiO2.
FIG. 3.

(a) Capacitance vs frequency curve and (b) leakage current density vs applied field curve of the Li–Al2O3 dielectric with an MIM (p+-Si/Li–Al2O3/Al) structure.

FIG. 3.

(a) Capacitance vs frequency curve and (b) leakage current density vs applied field curve of the Li–Al2O3 dielectric with an MIM (p+-Si/Li–Al2O3/Al) structure.

Close modal

Apart from the C–f measurement, an assessment of the current–voltage (I–V) characteristics has been also conducted to understand the electrical properties of the solution-processed dielectric film. This investigation was performed using the same device architecture (p+-Si/Li–Al2O3/Al). As illustrated in Fig. 3(b), the leakage current density of the Li–Al2O3 dielectric layer annealed at 500 °C was found to be extremely low (∼10−9 A/cm2), allowing it to function effectively with the SnO2 active layer at an operating voltage of less than 2 V. Additionally, the device exhibited a breakdown voltage exceeding 15 V, which is significantly higher than the normal operating voltage of the device (∼2 V), and it is stable up to a field of 1.6 MV/cm. These remarkable properties can be attributed to the scarcity of trap states and the low pinhole density within the dielectric thin film. Based on these findings, it can be inferred that the solution-processed Li-Al2O3 ionic dielectric is a well-suited gate dielectric in Thin-Film Transistors (TFTs).

The TFT device characterization was carried out using an n-type SnO2 semiconductor as the active layer for two distinct types of TFTs (named as TFT 1 and TFT 2), as illustrated in Fig. 4. In TFT 1, SnO2 served as the active layer with the gate dielectric being Li–Al2O3. To conduct a comparative study, TFT 2 has been fabricated with Ti3C2Tx MXene incorporated on top of the Li–Al2O3 and followed by a SnO2 layer. The output (ID–VD) and transfer (ID–VG) characteristics of TFT 1 are depicted in Figs. 4(a) and 4(b), respectively. For each constant gate voltage ranging from −0.5 to 2 V, the drain voltage was varied from 0 to 2 V. The saturation in the output characteristics of TFT 1 was achieved at a drain voltage of 1.5 V. On the other hand, the transfer characteristics of TFT 1 involved varying the gate voltage from −0.5 to 2 V at a fixed 2 V drain voltage. The on/off ratio of the device, calculated from the transfer characteristics, was found to be 8.1 × 102.

FIG. 4.

(a) Output and (b) transfer characteristics of the TFT 1 and (c) output and (d) transfer characteristics of TFT 2 under a low operating drain (VD) and gate voltage (VG).

FIG. 4.

(a) Output and (b) transfer characteristics of the TFT 1 and (c) output and (d) transfer characteristics of TFT 2 under a low operating drain (VD) and gate voltage (VG).

Close modal
The effective carrier mobility (μ), sub-threshold swing (SS) and interface trap state density ( N s s M a x ) of these TFTs are calculated from following equations, respectively:
I D = μ C W 2 L ( V G V T ) 2 ,
(2)
SS = [ d ( log I D ) d V G ] 1 ,
(3)
N SS Max = [ SS X log e kT q 1 ] C q ,
(4)
where ID, C, VG, VT, SS, k, and q are saturation drain current, capacitance per unit area, gate voltage, threshold voltage, subthreshold swing, Boltzman’s constant, and electronic charge, respectively.

The subthreshold swing (SS) and saturation mobility (μsat) of the device were determined by obtaining the slope from the linear fit of log (ID) vs VG and (ID)1/2 vs VG curves in the transfer characteristics.35 The effective mobility in the saturation region of TFT 1, determined from Eq. (2), amounted to 1.17 cm2/V s, with an on voltage (VON) of the device being 0.9 V. Furthermore, Figs. 4(c) and 4(d) show the output and transfer characteristics of TFT 2. The TFT 2 exhibited clear saturation even below 1.5 V under the same operating drain voltage (VD) range and the same gate voltage (VG) value. The extracted values of the on/off ratio, saturation mobility, and threshold voltage for TFT 2 were 1.3 × 105, 10.6 cm2/V s, and 0.1 V, respectively. Moreover, the on current of TFT 2 was enhanced by 15 times compared to TFT 1 as shown in Table I. We have also checked the stability of the device through a bias stress stability test, which is already discussed in detail in Fig. S4 in the supplementary material. The statistical data of single batch devices of TFT 2 are presented (Fig. S5 in the supplementary material), which closely aligns with the data presented in the study. The actual optical image of the device can be found in Fig. S6 in the supplementary material.

TABLE I.

Summary of device parameters of TFT 1 and TFT 2.

DeviceThreshold voltage (Vth) (V)On–off ratioCarrier mobility (cm2 V−1 s−1)Subthreshold swing (mV Decade−1)Interface trap state density (cm−2)
TFT 1 0.9 8.1 × 102 1.17 387 7.9 × 1012 
TFT 2 0.1 1.3 × 105 10.6 194 3.2 × 1012 
DeviceThreshold voltage (Vth) (V)On–off ratioCarrier mobility (cm2 V−1 s−1)Subthreshold swing (mV Decade−1)Interface trap state density (cm−2)
TFT 1 0.9 8.1 × 102 1.17 387 7.9 × 1012 
TFT 2 0.1 1.3 × 105 10.6 194 3.2 × 1012 

Additionally, the mechanism for high-performance n-type FETs with a bilayer Ti3C2Tx MXene/SnO2 configuration was further explored. The schematic band diagrams of the bilayer Ti3C2Tx-MXene/SnO2 transistor upon different gate biases are shown in Figs. 5(a) and 5(b). The heterojunction formed between SnO2 and Ti3C2Tx played a crucial role in the enhancement of the TFT performance. As shown in Fig. 5(a), the SnO2/Ti3C2Tx interface, SnO2 (4.9 eV), and Ti3C2Tx (4.79 eV) have different work functions.36 As compared to no gate bias (VG = 0 V) at the SnO2/Ti3C2Tx interface, abundant electrons are induced at the Li–Al2O3/MXene interface by the positive gate voltage (VG > 0 V) and the electrons could flow from the conduction band of Ti3C2Tx into that of SnO2 until reaching the Fermi-level equilibrium. The electrons are transferred from MXene to the SnO2 channel because of the unique properties of MXene with the high mobility. The MXene nanosheets are partially interconnected for constituting charge transport pathways with long lateral sizes, which can be intrinsically used as electronic channels due to their high mobility. Furthermore, the SnO2/Ti3C2Tx interfaces are very smooth (very low surface roughness) due to which the possibility of the trapping of electron in the SnO2 film is minimal. Additionally, the MXene channel as a 2D nanomaterial with high crystallinity shows fewer defects and trap states density, leading to fewer trapped electrons, which facilitates the electronic charge transport, and significantly increases mobile electron transport from SnO2 to the drain electrode, resulting in the enhanced on-state current, reduced threshold voltage, and improved electron mobility.

FIG. 5.

Schematic diagram of the proposed charge transfer mechanics, (a) before contact (VG = 0 V) and (b) after contact (VG > 0 V).

FIG. 5.

Schematic diagram of the proposed charge transfer mechanics, (a) before contact (VG = 0 V) and (b) after contact (VG > 0 V).

Close modal

The summary of the device parameters for both TFTs, i.e., TFT 1 and TFT 2, can be found in Table I.

The performance benchmark chart of both single oxide and hybrid channel-based transistor can be found in Table S1 in the supplementary material.

In summary, we successfully fabricated two solution-processed SnO2 Thin Film Transistors (TFTs), one without MXene and the other one with MXene in the channel. In both devices, an ion-conducting Li-Al2O3 thin film has been used as the gate dielectric. The incorporation of the Li-Al2O3 thin film in TFTs led to a higher areal capacitance, enabling it to operate at a voltage within 2.0 V. From this comparative study, it has been observed that the additional thin layer of MXene on top of the SnO2 layer can enhance device performance like carrier mobility, on/off ratio, and sub-threshold swing significantly. The TFT 2 demonstrated an on/off ratio approximately 104 times higher than TFT 1, which may have originated due to the enhanced effective sheet resistance of the channel. Moreover, TFT 2 exhibited a significantly reduced subthreshold swing and an improved adequate carrier mobility, approximately 10 times higher than that of TFT 1, which may have originated due to highly reduced dielectric/semiconductor interface trap states. The suggested bilayer Ti3C2Tx-MXene/SnO2 semiconductor configuration demonstrates both broad applicability and superior performance. This research article not only underscores the profound influence of the Ti3C2Tx MXene interface on solution-processed metal oxide transistors but also advances our understanding of how tailored interfaces can propel the development of high-performance low-voltage electronics. The findings pave the way for the realization of energy-efficient electronic devices that can operate reliably at significantly reduced power supply voltages, facilitating the progression toward sustainable and power-efficient electronics.

See the supplementary material for additional experimental data on structural analysis of MAX phase and Ti3C2Tx MXene, GIXRD data of Li-Al2O3 dielectric thin film, transmittance spectra of Ti3C2Tx MXene/SnO2 bilayer thin film, statistical analysis of TFT 2, bias stress stability test of TFT 2, optical image of the as prepared TFT and the performance benchmark chart of both single oxide and hybrid channel-based transistor.

This work was supported by “Science and Engineering Research Board,” India. Nitesh K. Chourasia acknowledges the “Science and Engineering Research Board” for National Post-Doctoral Fellowship (No. PDF/2021/001490). One of the authors, Ankita Rawat, is thankful to CSIR for awarding Junior Research Fellowship with Reference No. 09/263(1233)/2020-EMR-I.

The authors have no conflicts to disclose.

Ankita Rawat: Data curation (lead); Formal analysis (equal); Methodology (lead); Visualization (lead); Writing – review & editing (lead). Utkarsh Pandey: Data curation (equal); Validation (equal); Writing – review & editing (equal). Ritesh Kumar Chourasia: Formal analysis (equal); Software (equal); Writing – review & editing (equal). Gaurav Rajput: Formal analysis (supporting); Methodology (lead); Validation (supporting). Bhola Nath Pal: Methodology (equal); Resources (lead); Writing – review & editing (lead). Nitesh K. Chourasia: Conceptualization (lead); Data curation (lead); Formal analysis (lead); Funding acquisition (lead); Investigation (lead); Supervision (lead); Writing – original draft (lead). Pawan Kumar Kulriya: Conceptualization (lead); Resources (lead); Supervision (lead); Writing – review & editing (lead).

The data that support the finding of this study are available within the article and its supplementary material.

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