Nonvolatile memory operations using intersubband transitions in GaN/AlN resonant tunneling diodes grown on Si(111) substrates

Nonvolatile memory has attracted much attention because data can be written and erased at low electric power and the data can be stored for a long time without the need for an electric power supply. These unique characteristics have led to the development of various types of nonvolatile memory, such as resistive random-access memory (RAM), phase change RAM, ferroelectric RAM, magnetic RAM, and spin-transfer torque magnetoresistive RAM.^1–10 If these types of nonvolatile memory can be used in the main memory, caches, registers, and logic circuits in computer systems, which presently rely on volatile memory such as static random-access memory (SRAM) and dynamic RAM (DRAM), then the energy consumption of computer systems would be greatly reduced by the removal of unnecessary electric power supply at the waiting or temporary storage time in computer processing.^10,11 Such systems are referred to as normally-off computing systems. In addition, nonvolatile field-programmable gate arrays (FPGAs) that include nonvolatile memory are expected to provide higher-performance and lower-power processing systems for artificial intelligence and machine learning.^12–14 Recent progress in heterogeneous integration or three-dimensional (3D) integration, such as chip-on-wafer and wafer-on-wafer, is expected to accelerate hybrid integration with Si devices and various types of nonvolatile memory to enable their use in computing systems and nonvolatile FPGAs.^15–19 

However, the operation speeds of nonvolatile memory are relatively slow, compared with those of volatile memory such as SRAM and DRAM.^10,11 In particular, it is difficult to realize high-speed nonvolatile memory that operates at the picosecond timescale or the processing speed of SRAM. Therefore, new types of nonvolatile memory based on voltage-driven dynamic magnetization, spin–orbit torque magnetoresistivity, and non-thermal phase transformation has been studied to realize high-speed nonvolatile memory that operates at the picosecond timescale.^20–22 We are investigating a nonvolatile memory that uses intersubband transitions and quantum-well electron accumulation in GaN/AlN resonant tunneling diodes (RTDs).^23–29 Although this nonvolatile memory is a kind of resistive switching memory or ReRAM, the mechanism of operation is quite different from that of the conventional ReRAM based on oxidation or atom/ion movement.^{1–3,12–14} The unique operating mechanism, which is based on Poisson's equation and band profile changes in GaN/AlN RTDs, can potentially allow high-speed and nondestructive nonvolatile memory operation.

The study of this nonvolatile memory was unexpectedly started when an unclarified bistability of current–voltage (I–V) characteristics of GaN/AlN RTDs could be explained by intersubband transitions and electron accumulation in the quantum well.²³ In addition, this finding enabled the use of GaN/AlN RTDs in both nonvolatile memory and terahertz oscillators.^30–39 We have confirmed to date that a long retention time of >30h and error-free operation of >10⁵ cycles can be achieved using GaN/AlN RTDs grown on sapphire(0001) substrates via metal-organic vapor phase epitaxy (MOVPE).^25,26 In addition, a large reduction in the density of pit-shaped crystal defects and dislocations in the quantum well was determined to realize a high ON/OFF ratio of >10³, which is 20 times higher than that for quantum wells with high densities of such defects.²⁹ Furthermore, it was confirmed that nonvolatile memory operation could be performed by inputting sequential pulse voltages with a speed of the nanosecond timescale, which is faster than the speed of electron release from crystal defects. These results strongly indicate that nonvolatile memory operation with the GaN/AlN RTDs is attributed to intersubband transitions and electron accumulation in the quantum-well and not to electron trapping by crystal defects.

In this work, GaN/AlN RTDs are fabricated on a Si(111) substrate using MOVPE with an aim of realizing hybrid integration between GaN/AlN RTDs and Si devices or other types of nonvolatile memory. A strain-compensation technique based on the insertion of a low-temperature-grown AlGaN layer and a thin AlN layer is utilized to suppress the strain caused by the differences in the thermal expansion coefficients and lattice constants between the Si(111) substrates and GaN/AlN RTDs. The crystal quality of the GaN/AlN RTDs grown on Si(111) substrates is characterized using atomic force microscopy (AFM) and transmission electron microscopy (TEM) observations. The nonvolatile memory characteristics of the GaN/AlN RTDs, such as ON/OFF switching and endurance characteristics, are evaluated at room temperature.

Figure 1(a) shows the device structure of a GaN/AlN RTD fabricated on a Si(111) substrate using MOVPE. First, a 100 nm thick AlN nucleation layer was grown on a Si(111) substrate at 900 °C. AlN/AlGaN heterointerface layers with a total thickness of 100 nm were then grown at 1130 °C to create a high-quality thin AlN layer for strain compensation. Low-temperature-grown AlGaN (LT-AlGaN), thin AlN and LT-AlGaN layers were then grown at 900, 1130, and 900 °C, respectively, to suppress the strain caused by the difference in the thermal expansion coefficients and lattice constants between Si and the nitride materials.

Figure 1(b) shows the concept of the strain-compensation technique using LT-AlGaN and thin AlN layers. The red arrows in the upper GaN layer show a tensile strain (Δα) caused by changing the temperature in the MOVPE chamber from the nitride growth temperature (between 950 and 1125 °C) to room temperature (or a Δα caused by the large difference in the thermal expansion coefficients between the Si and GaN materials). However, the insertion of thin AlN and LT-AlGaN layers with small lattice constants between 3.11 and 3.19 Å can induce compressive strain (Δd) in the upper GaN layer, as indicated by the blue dotted line arrows. Therefore, the total strain in the upper GaN layer can be reduced by the addition of compressive strain (Δd) to the tensile strain (Δα). Namely, the LT-AlGaN and thin AlN layers inserted between the upper GaN layers and Si(111) substrate function as sacrificial layers.

These compensation techniques have typically been performed with the GaN/AlN superlattices (SLs) or AlGaN/AlN SLs, which are composed of thin GaN and AlN layers or AlGaN and AlN layers with a thickness of a few nanometers and many periods of SLs greater than 40 or 60, and fine GaN/AlGaN high electron mobility transistors have been fabricated on Si(111) substrates with diameters between 2 and 6 in.^40–45 However, the proposed technique can realize strain compensation using a small number of periods of AlN and LT-AlGaN layers because thick LT-AlGaN layers can be coherently grown on thin AlN layers.⁴⁶ The growth temperatures and thicknesses of the LT-AlGaN and AlN layers in Fig. 1 were determined based on the results of previous experiments.⁴⁶ 

After the growth of the strain-compensation layers, a 1 μm thick undoped (u)-GaN buffer layer was grown at 1125 °C to further reduce the density of dislocations.^47,48 The GaN/AlN RTD layer, which is composed of an n⁺-GaN contact layer (500 nm), n-GaN emitter layer (50 nm), u-GaN/AlN quantum-well structure (17 nm), n-GaN collector layer (50 nm), and n⁺-GaN contact layer (30 nm), was then grown at temperatures between 950 and 1125 °C. For the growth of the u-GaN/AlN quantum-well structure including u-GaN spacer layers (17 nm), pure N₂ carrier gas and a trimethylindium (TMIn) surfactant were used to suppress the formation of pit-shaped crystal defects.^29,49,50 On the other hand, for the growth of other epitaxial layers excluding the quantum-well structure, a N₂/H₂ mixture carrier gas was used to suppress dislocations in all of the device layers. The advantages of the use of pure N₂ carrier gas and TMIn surfactant for growth of the quantum-well structure and the use of a N₂/H₂ mixture carrier gas for growth of the other layers have been previously described.²⁹ 

Finally, Cr/Au ohmic electrodes were formed on the top and bottom n⁺-GaN contact layers using photolithography and inductively coupled plasma (ICP) dry-etching techniques. The top electrode was placed apart from the etched region for forming the bottom electrode. In addition, relatively shallow etching (depth: ≈ 250 nm) was conducted to make a wide current path in the n⁺-GaN bottom contact layer. Therefore, even if the etched surface including sidewall surface is damaged by ICP dry etching, the current path in the RTD and n⁺-GaN bottom contact layers and nonvolatile memory operation would not be significantly affected.

Figures 1(c) and 1(d) show the mechanism for nonvolatile memory operation using intersubband transitions and quantum-well electron accumulation in GaN/AlN RTDs. The GaN/AlN RTDs have a high band offset (ΔE_c) of 1.8 eV and can make two resonance levels in the quantum well. The bold red arrow in Fig. 1(c) shows that resonant tunneling of electrons through the upper resonance level (E_R2) occurs when a forward bias voltage is applied to the device. However, as shown by the red broken arrow in Fig. 1(c) and the black bold arrows in Fig. 1(d), intersubband can relax the electrons from E_R2 to the lower resonance level (E_R1), and the electrons accumulate in E_R1 via longitudinal optical (LO) scattering. The electrons that accumulate in E_R1 change the band profile according to Poisson's equation and shift E_R2 (and E_R1) to higher energy. The shift of E_R2 stops resonant tunneling of electrons through E_R2 and the state changes from a low resistivity state to a high resistivity state. Therefore, a write operation for the nonvolatile memory is realized by the application of a forward bias voltage. On the other hand, the electrons accumulated in E_R1 can be released by the application of a reverse bias voltage, as described in Ref. 29. E_R1 shifted by the quantum-well electron accumulation becomes much higher than the Fermi level in the collector (E′_f) at a zero-bias voltage.²⁸ Therefore, the electrons accumulated in E_R1 can be forced out by the application of a reverse bias voltage and the reverse tunneling current through E_R1, according to the Tsu–Esaki formula. This recovers E_R2 from the high energy position to the original low energy position, and then changes the state from a high resistivity state to a low resistivity state. Therefore, write and erase operations for nonvolatile memory are realized by the application of forward and reverse bias voltages, respectively. This simple operation (two terminal operation) would be effective for decreasing the cell size of RAM in computing systems and switching circuits in nonvolatile FPGAs, because it is difficult to decrease the cell size and leakage current in SRAM, which is composed of CMOS circuits with complex wiring patterns.^10,11

The electron transition from E_R2 to E_R1 and resonant tunneling through E_R2 and E_R1 occur at femtosecond or sub-picosecond timescales.^51–53 Therefore, high-speed nonvolatile memory operation can be realized using intersubband transitions and quantum-well electron accumulation in GaN/AlN RTDs. In addition, nondestructive write and erase memory operations based on Poisson's equation can potentially realize high-endurance nonvolatile memory operations. However, imperfect accumulation and release of electrons in the quantum well due to dislocations can cause errors in the write and erase memory operations, as discussed later.

Figure 2(a) shows an optical microscopy image of a GaN/AlN RTD grown on a Si(111) substrate using MOVPE. Although shallow and short cracks were unintentionally formed on the substrate, sufficiently large areas to fabricate the device structure and obtain AFM images were obtained, as shown in Figs. 2(b) and 2(c). The density of dislocations and the root mean square value for the sample surface roughness, which are estimated using Fig. 2(c), were 1.2 × 10⁹ cm⁻² and 0.298 nm, respectively. The density of dislocations was equivalent to or slightly higher than those of GaN/AlN RTDs grown on sapphire(0001) substrates, which are shown in Fig. 2(d) and Refs. 28 and 29. However, the size and depth of dislocations in the GaN/AlN RTD layers grown on the Si(111) substrate were greater than those of GaN/AlN RTDs grown on sapphire(0001) substrates, as shown in Figs. 2(e) and 2(f).

Then, bright-field TEM, high-resolution TEM (HR-TEM), and high-angle annular dark field scanning TEM (HAADF-STEM) observations were performed to investigate the crystal quality within the GaN/AlN RTDs grown on Si(111) substrates. Figure 3(a) shows that the strain-compensation layers composed of LT-AlGaN layers, thin AlN layer and AlN/AlGaN layer were clearly evident. It was also confirmed that some dislocations were annihilated in the middle of the 1 μm thick (u-)GaN buffer layer, because of the bonding of the adjacent dislocations with different Burgers vectors.^47,48 Furthermore, as shown in Figs. 3(b) and 3(c), formation of a fine GaN/AlN quantum-well structure was confirmed. However, as shown in Figs. 3(d) and 3(e), residual dislocations were found to locally distort the GaN/AlN quantum-well structure. In addition, it was confirmed that the density of dislocations that penetrated the GaN/AlN quantum-well structure was equivalent to that estimated from AFM observations because of a short distance between the sample surface and the quantum-well structure.

Figure 4(a) shows the typical nonvolatile memory characteristics of GaN/AlN RTDs fabricated on a Si(111) substrate measured by the repeated application of positive and negative bias voltages. The write and erase voltages and ON/OFF ratio were approximately +1 V, −2 V, and 220, respectively, which were equivalent to those obtained for GaN/AlN RTDs fabricated on a sapphire(0001) substrate, as shown in Fig. 4(b). However, shoulder-like structures were observed between +1 and +3 V in the I–V characteristics of GaN/AlN RTDs fabricated on a Si(111) substrate at the write operations. In addition, the erase voltages changed significantly by repeating the measurements. Furthermore, the ON and OFF currents (I_ON and I_OFF) for GaN/AlN RTDs fabricated on a Si(111) substrate were approximately 10 times larger than those for GaN/AlN RTDs fabricated on a sapphire(0001) substrate. Note that the maximum values of vertical axes of Figs. 4(a) and 4(b) are different. The growth rate of AlN barrier layers on a Si(111) substrate appears to be slower than that on sapphire(0001) substrates, because of the small difference in the growth temperature due to the thermal conductivity or size of the Si(111) and sapphire(0001) substrates, which have a diameter of 4 and 2 in., respectively. In addition, it has been reported that a decrease in the AlN barrier thickness by approximately 1 nm can increase I_ON and I_OFF by approximately 10 times.^32,37,54

Nonvolatile memory operations were further investigated by measurement of the current responses to the pulse voltages using a semiconductor parameter analyzer (Keysight Technology, B1500A/1530A). Figure 4(c) shows that clear current changes due to intersubband transitions and quantum-well electron accumulation were observed by inputting a pulse voltage of +3 V, and current changes due to electron release were observed by inputting a pulse voltage of −3 V. In addition, as shown in Fig. 4(d), the ON/OFF switching characteristics and I_ON could be well fitted using previously reported exponential curves and time constants of τ_sw and τ_f.^27,29 However, as shown in Fig. 4(e), the switching time for write operations (τ_sw) fluctuated during repeated ON/OFF switching measurements of 20 cycles, while the fall time for I_ON (τ_f) did not fluctuate and was equivalent to the measurement limit of the apparatus (5–10 ns). To clarify this, the ON/OFF switching characteristics of GaN/AlN RTDs fabricated on a sapphire(0001) substrate with a relative low density of dislocations on the order of ≈10⁸ cm⁻² were evaluated. In addition, the samples with thin barrier thicknesses of 2 nm and well thickness of 3 nm and a high I_ON of >10⁻⁴ A were used to evaluate τ_sw and τ_f with high accuracy.²⁹ As a result, it was found that τ_sw for the GaN/AlN RTDs fabricated on sapphire(0001) substrates was more stable than that for the GaN/AlN RTDs fabricated on Si(111) substrates. Therefore, the large instability of nonvolatile memory operations using GaN/AlN RTDs grown on a Si(111) substrate appears to be due to the enhanced electron leakage through the deep levels in AlN barriers, as discussed below.

Figure 5(a) shows the band profile of a GaN/AlN RTD, when write operation or electron accumulation was started by the application of a forward bias voltage. The broken lines in the AlN barrier layers indicate the deep levels (E_DL and E′_DL) that are created by dislocations and that provide the ability to leak electrons by trap-assisted-tunneling.^55,56 From reported calculation results,^28,29 it is considered that E_DL becomes close to the Fermi level in the emitter (E_f) by the application of a high forward bias voltage, as shown in Fig. 5(a). Therefore, electron leakage from the emitter to the quantum well would occur during write operations, as shown in the red bold arrow in Fig. 5(a). The electron leakage from the emitter to the quantum well also increases the density of electrons that accumulate in the quantum well (n_well), as illustrated by the red bold arrow in Fig. 5(b). In addition, the erase voltage is dependent on n_well.^28,29 Therefore, the erase voltage for GaN/AlN RTDs grown on a Si(111) substrate, which have a large size and density of dislocations (or a large density of deep levels), changed significantly by the irregular electron leakage through E_DL during repeated measurements of the I–V characteristics [see Fig. 4(a)].

In addition, electron leakage from the quantum well to the collector through E′_DL appears to occur during or after the write operation, as shown in Fig. 5(c). When many electrons are accumulated in the quantum well, E_R2 and E_R1 are shifted to higher energy, according to the change in the band profile based on Poisson's equation, as explained in Sec. II. In addition, the electric field in the AlN barrier in the collector side becomes stronger. As a result, E_R1 (energy level for electron accumulation) would approach E′_DL, and electron leakage through E′_DL and a decrease in n_well would occur, as illustrated in Figs. 5(c) and 5(d). Such a leakage results in the inefficient or slow accumulation of electrons in the quantum well during the write operation. Therefore, a large fluctuation of τ_sw would be observed, as shown in Fig. 4(e). In addition, the shoulder-like structures in the I–V characteristics in Fig. 4(a) would be explained by the electron leakage through E′_DL.

The large shift of erase voltage and the shoulder-like structures in the I–V characteristics in Fig. 4(a) are caused by the complicated electron leakage through E_DL and E′_DL. In addition, the number of electrons leaked through E_DL and E′_DL increases by decreasing the energy difference between E_f and E_DL and the energy difference between E_R1 and E′_DL, respectively. These energy differences depend on the quantum-well structure and n_well and decrease by applying a forward bias voltage, as reported in Refs. 24 and 28. Therefore, the retention time obtained by the GaN/AlN RTDs fabricated on a Si(111) substrate was equivalent to that on sapphire(0001) substrates, because the energy differences between E_f and E_DL and between E_R1 and E′_DL were relatively large at a zero-bias voltage. The energy differences between E_f and E_DL and between E_R1 and E′_DL at a zero-bias voltage and n_well= 1.5 × 10¹⁸ cm⁻³ were estimated to be approximately 0.4 and 0.6 eV, respectively, from reported calculation results.^28,29 This result also supports an explanation that the instability of nonvolatile memory operations is mainly caused by the electron leakage through E_DL and E′_DL at the application of high forward bias voltage.

Finally, the endurance characteristics of the GaN/AlN RTDs fabricated on a Si(111) substrate were investigated by inputting a pulse voltage sequence with a pulse width of 500 μs and repeat cycles for write-read-erase-read operations, which can be generated by the semiconductor parameter analyzer (Keysight Technology, B2912A).²⁶ For a forward correction of the large fluctuation of write and erase voltages, the write and erase pulse voltages were set to +3 and −3 V, respectively. In addition, read pulse voltages (V_read) for ON and OFF currents (I_ON and I_OFF) were set to +0.5 and +2 V, respectively. The reason that uses different V_read for I_ON and I_OFF is as follows.

As shown in Fig. 4(a), when the I–V characteristics are measured by the direct current mode or high-resolution mode, the minimum current that can be measured precisely is on the order of 10⁻⁹ or 10⁻¹⁰ A. However, the current resolution for the sequential pulse voltages or the minimum current that can respond to the sequential pulse voltages in the apparatus (B2912A) is about 10⁻⁵ or 10⁻⁶ A. Therefore, we had to apply a relatively high V_read of +2 V to measure I_OFF. From the above reasons, the ON/OFF ratio (=I_ON/I_OFF) for the endurance characteristics, which is approximately 50, is four times lower than the maximum ON/OFF ratio (≈220) determined from the I–V characteristics in Fig. 4(a).

Figure 6 shows the typical endurance characteristics measured at room temperature for the GaN/AlN RTDs fabricated on a Si(111) substrate. To investigate the influence of continuous pulse voltages on I_ON and I_OFF, the measurements were conducted by inputting pulse voltage sequences with a relatively small cycle of 10³. As a results, as shown in Figs. 6(a) and 6(b), error-free operation with a high I_ON/I_OFF of >50 was successfully achieved for 2000 (=1000 + 1000) cycles. However, as shown in Figs. 6(c) and 6(d), errors in the erase operations and small increases in I_OFF were observed with additional measurements. Errors in the erase memory operations are due to the large shift of the erase voltage, as observed in the I–V characteristics in Fig. 4(a) and the increase in n_well illustrated in Fig. 5(b). In addition, the small increases in I_OFF can be explained by the irregular release of electrons accumulated in the quantum well through E′_DL, as illustrated in Figs. 5(c) and 5(d). Therefore, suppression of electron leakage through E_DL and E′_DL in the barrier layers is indispensable to realize high-endurance and high-speed nonvolatile memory using intersuband transitions and quantum-well electron accumulation in GaN/AlN RTDs.

Table I shows the endurance characteristics obtained in this work and previous studies.^25,26,29 As shown in the first row of Table I, error-free operation of >10⁵ cycles have been achieved to date with the GaN/AlN RTDs fabricated on sapphire (0001)substrates. The reason for the high endurance characteristics of >10⁵ cycles in previous work and the low endurance characteristics of >2000 cycles in this work is under investigation. However, there appears to be a trade-off between the ON/OFF ratio and the endurance characteristics for nonvolatile memory operation. A high ON/OFF ratio or high density of electrons accumulated in the quantum well (n_well) appears to promote electron leakage from the quantum well through E′_DL in the AlN barrier, because the increase in n_well directly increases the Fermi level of electrons in E_R1. In addition, an increase in n_well can change the band profile and shift E_R1 to higher energy. This would increase the number of electrons leaked through E′_DL in the AlN barrier layers. Furthermore, electron leakage through E_DL and E′_DL, which are formed by dislocations (or imperfect crystalline areas) has a possibility to cause a mechanical fracture of the barrier layers in the GaN/AlN RTDs. Therefore, it seems that degradation of nonvolatile memory operation occurred when the GaN/AlN RTDs with a high density of dislocations of ≈10¹⁰ cm⁻² were used for evaluation of the endurance characteristics.²⁶ 

A possible method to suppress the electron leakage through E_DL and E′_DL and realize high endurance characteristics would be a homoepitaxial growth method using a GaN substrate. It has been revealed that the dislocation density in the devices fabricated by homoepitaxial growth using GaN(0001) substrates is approximately two orders of magnitude below those by heteroepitaxial growth using Si(111) and sapphire(0001) substrates, and fine p-n junction GaN diodes have been successfully fabricated.^57,58 However, further progress in the 3D integration technique between the GaN chip (or wafer) and Si chip (or wafer) will be necessary for the use of this nonvolatile memory in attractive applications such as normally-off computing and nonvolatile FPGAs.^10–14 Another possible method to suppress electron leakage through E_DL and E′_DL might be to utilize barrier layers made from different materials, such as AlGaN and AlInGaN.^36,37 The energy difference between E_f and E_DL or E_R1 and E′_DL could possibly be increased with the use of AlGaN or AlInGaN barriers instead of the AlN barriers employed in the present study, because (GaN,) AlGaN, AlN, and AlInGaN have different bandgaps and different deep levels.^56,59–62 In addition, the composite barrier with AlGaN/AlN or InAlN/AlN heterointerface might be effective for suppressing electron leakage in and out of the quantum well, because an uncontentious deep level can be formed at the AlGaN/AlN or InAlN/AlN heterointerface. Furthermore, if growth techniques based on patterned Si substrates (PSS) and epitaxial lateral overgrowth of AlN (ELO-AlN) templates, which can realize a low dislocation density between 10⁷ and 10⁸ cm⁻² and enhance the characteristics of GaN-based light-emitting diodes, are used for the fabrication of GaN/AlGaN or GaN/AlInGaN RTDs, electron leakage through E_DL and E′_DL might be significantly suppressed.^63–65 Therefore, it is expected that endurance characteristics of this nonvolatile memory will be improved using the above growth and fabrication techniques or designing the quantum-well structure appropriately.

In this study, nonvolatile memory based on intersubband transitions and quantum-well electron accumulation in GaN/AlN RTDs was fabricated on Si(111) substrates using MOVPE. The strain caused by the large differences in the thermal expansion coefficients and lattice constants between Si and the nitride materials was suppressed by the insertion of low-temperature-grown AlGaN layers and thin AlN layers. As a result, clear GaN/AlN heterointerfaces and nonvolatile memory characteristics with a high ON/OFF ratio of >220, which were equivalent to that for devices fabricated on sapphire(0001) substrates, were successfully realized. However, the endurance characteristics of GaN/AlN RTDs fabricated on Si(111) substrates were lower than those of devices fabricated on sapphire(0001) substrates. This was explained by enhanced electron leakage through the deep levels (E_DL and E′_DL) in the AlN barrier layers, via AFM and TEM observations and the operation mechanism for nonvolatile memory with GaN/AlN RTDs. In addition, it was shown that there was a trade-off between ON/OFF ratio and endurance characteristics. The unique operation mechanism based on Poisson's equation and the band profile change in the GaN/AlN RTDs has the potential to realize high-speed nondestructive memory operation on a picosecond timescale. However, electron leakage through E_DL and E′_DL appears to prevent this. As methods to suppress electron leakage through E_DL and E′_DL in GaN/AlN RTDs, (1) the use of homoepitaxial growth with a GaN substrate and wafer or chip bonding techniques, (2) the use of different materials in the barrier layers, such as AlGaN or AlInGaN barriers, and (3) the use of PSS and ELO-AlN templates, and a combination of (2) and (3) were discussed. Crystal growth and fabrication techniques for GaN-based devices are progressing due to the development of GaN-based power devices, light-emitting diodes, and laser diodes. Therefore, it is expected that endurance characteristics of this nonvolatile memory will be improved using the advanced growth and fabrication techniques for nitride materials or designing the quantum-well structure of GaN-based RTDs appropriately.

This work was supported by a Kakenhi Grant-in-Aid (No. JP20H02214) from the Japan Society for the Promotion of Science (JSPS). Part of this work was conducted at the National Institute of Advanced Industrial Science and Technology (AIST) Nano-Processing Facility, supported by the “Nanotechnology Platform Program” of the Ministry of Education, Culture, Sports, Science and Technology (MEXT), Japan.

The authors declare that they have no conflict of interest.

Masanori Nagase: Conceptualization (lead); Data curation (equal); Formal analysis (lead); Funding acquisition (equal); Investigation (equal); Project administration (lead); Resources (equal); Validation (lead); Visualization (lead); Writing – original draft (lead); Writing – review & editing (equal). Tokio Takahashi: Data curation (equal); Funding acquisition (equal); Investigation (equal); Resources (equal); Writing – review & editing (equal). Mitsuaki Shimizu: Data curation (equal); Funding acquisition (equal); Resources (equal); Writing – review & editing (equal).

The data that support the findings of this study are available from the corresponding author upon reasonable request.