The recent progress in quantum computing and space exploration led to a surge in interest in cryogenic electronics. Superconducting devices such as Josephson junction, Josephson field effect transistor, cryotron, and superconducting quantum interference device (SQUID) are traditionally used to build cryogenic logic gates. However, due to the superconducting nature, gate-voltage-based control of these devices is extremely difficult. Even more challenging is to cascade the logic gates because most of these devices require current bias for their operation. Therefore, these devices are not as convenient as the semiconducting transistors to design logic gates. Here, to overcome these challenges, we propose a ferroelectric SQUID (FeSQUID) based voltage-controlled logic gates. FeSQUID exhibits two different critical current levels for two different voltage-switchable polarization states of the ferroelectric. We utilize the polarization-dependent (hence, voltage-controllable) superconducting to resistive switching of FeSQUID to design Boolean logic gates such as Copy, NOT, AND, and OR gates. The operations of these gates are verified using a Verilog-A-based compact model of FeSQUID. Finally, to demonstrate the fanning out capability of FeSQUID-based logic family, we simulate a two-input XOR gate using FeSQUID-based NOT, AND, and OR gates. Together with the ongoing progress on FeSQUID-based non-volatile memory, our designed FeSQUID-based logic family will enable all FeSQUID-based cryogenic computer, ensuring minimum mismatch between logic and memory blocks in terms of speed, power consumption, and fabrication process.
INTRODUCTION
The idea of superconducting electronics (SCEs) was first put forward in 1950s with the effort of building magnetic field-modulated superconducting wires.1,2 The requirement of extremely low temperature was one of the major roadblocks for the superconducting devices to be used in practical applications which now becomes an advantage, thanks to the recent interests in superconducting qubit-based quantum computers and space electronics.3–6 Superconducting logic circuits can significantly improve the performance of the control processor in the quantum computers and the aircrafts for space exploration.3 Even in the classical computing, SCE shows immense potential. Although CMOS technology can now allow us to put more than trillion transistors on a single chip, the power dissipation reaches the physical limit and makes further scaling difficult.6,7 To solve this issue, several beyond-CMOS alternatives are being explored. SCE is considered as one of the most promising alternatives to CMOS technology, thanks to their high speed and low power operation.2,8 SCE has also been used in radio frequency receivers, high-end computing, and so on.9,10
Over the last few decades, several superconducting logic devices1,11–20 have been introduced. All of these except Josephson junction (JJ) have been limited within the basic characterization. JJ has been successfully utilized in a wide variety of applications due to their high speed (hundreds of gigahertz) and low power consumption (sub-aJ/bit). However, JJ-based circuits suffer from challenges: (i) the manipulation of single flux quanta causes issues while driving large impedances or fanning out digital signals and (ii) difficulty in the fabrication of uniform JJs over a wafer and the effects of magnetic field limit the distance between two JJs and, hence, the integration density.21 Another disadvantage (particular to logic circuits) of two-terminal JJ and superconducting quantum interference device (SQUID) is that the absence of resistance in superconductors hinders the voltage biasing and hence, superconducting devices cannot offer convenient gating mechanism like the semiconducting transistors. Therefore, there has been a significant amount of effort to implement a gate-tunable superconducting device.1,12–14,17
SQUID is one of the basic building blocks for superconducting circuits and systems. Researchers have tried continuously to introduce gate-tunability to SQUIDs. The efforts include utilizing ionic liquid,22,23 integrating ferromagnetic components,24–26 and so on. Although the integration of ferromagnetic components allows non-volatile tunability, magnetic tunability limits the scalability of the circuits and systems. Recently, a new technique has been demonstrated that uses a ferroelectric material to tune the superconductivity of the SQUID.27 Ferroelectric materials show voltage-controlled non-volatile switching of the polarization. Therefore, the incorporation of the ferroelectric material introduces voltage-controlled non-volatile switching of the critical current of the SQUID which opens a lot of possibility of utilizing this device in circuit/system level. This ferroelectric SQUID (FeSQUID) has already been used to design a cryogenic memory system, which promises voltage-controllability, non-volatility, scalability, separate read write paths, and energy efficient operation.28 Therefore, FeSQUID-based cryogenic memory might be able to solve the issues of existing cryogenic memories and pave the way of large-scale development of quantum computers and SCE.3,6,29–32 In this work, we present a voltage-controllable cryogenic Boolean logic family based on FeSQUIDs, which will allow the close integration of logic and memory blocks since both logic and memory can be designed using the same device. Therefore, there will be no mismatch between the logic and memory blocks in terms of speed, power consumption, and fabrication process which will also reduce the “memory wall” bottleneck.33–37 The major contributions of this work are outlined below.
Designing the first voltage-controlled superconducting logic circuits.
Solving the issues of single fan-out and the need for extra current splitter circuits in current-controlled superconducting logic designs.
Utilizing the interaction between FeSQUIDs and heater cryotrons (hTron) to ensure that both input and output values match, allowing one logic gate’s output to drive the next input.
Developing a compact Verilog-A model for FeSQUID to verify the functionality of the designed logic gates in simulations, which can be valuable for future exploration of FeSQUID-based circuits and systems.
DEVICE CHARACTERISTICS AND MODELING APPROACH OF FeSQUID
(a) Device structure and circuit symbol of FeSQUID. (b) Polarization–voltage characteristics for the PZT ferroelectric along with the validation of the developed compact model with the experimental results obtained from Ref. 27. (c) Current–voltage characteristics of FeSQUID. Two polarization states of the ferroelectric lead to two levels of IC. (d) Table shows the definition of logic states and corresponding device states used in the design of Boolean logic gates.
(a) Device structure and circuit symbol of FeSQUID. (b) Polarization–voltage characteristics for the PZT ferroelectric along with the validation of the developed compact model with the experimental results obtained from Ref. 27. (c) Current–voltage characteristics of FeSQUID. Two polarization states of the ferroelectric lead to two levels of IC. (d) Table shows the definition of logic states and corresponding device states used in the design of Boolean logic gates.
In our FeSQUID-based logic circuits, we leverage the DC mode of SQUIDs which make them susceptible to issues like high frequency power loss and the effects of kinetic inductance faced by the existing superconducting rapid single flux quantum (RSFQ) logic circuits.
DESIGN METHODOLOGY AND RESULTS
For any logic gate, a crucial requirement is the capability of handling fan-out. For a cascadable logic system, the outputs of the logic gates should be able to drive the inputs of the next stage. Now, for FeSQUID, to drive one gate by the output of another gate, the output voltage needs to be sufficiently large to set the intended polarization in the ferroelectric of the FeSQUID. Figure 2(a) shows the schematic of a FeSQUID-based copy gate. As seen in Fig. 1(c), the IC values of the FeSQUID device are 2.6 and 4 μA, and the values of RN are 0.95 and 1.75 kΩ for and , respectively. or proper operation of the copy gate shown in Fig. 2(a), the value of the external resistance (R) needs to be chosen in a way so that when the FeSQUID becomes resistive, almost all the bias currents flow through R. Also, we have to choose a bias current so that it satisfies . Here, we choose 3.2 A and 10 Ω for I and R, respectively. For these chosen values, we get ∼31 μV (0 V) for logic “1” (“0”) at the output of the copy gate shown in Fig. 2(a) which are not sufficient to drive the FeSQUID of the next stage. To circumvent this issue, we utilize heater cryotron (hTron)21,32,44 at the output of each logic gates to develop a cascadable logic system based on FeSQUIDs. Figure 2(c) displays the I–V characteristics of hTron. hTron is a three terminal gate current-controlled superconducting switch, consisting of a superconducting channel and a resistive gate. The hTron channel initially remains superconducting but a high enough (larger than the switching current) gate current can switch the superconducting channel to the resistive state. In our simulation, we utilize a phenomenological compact model for hTron, developed in one of our previous works.32 After using hTron (working principle of the designed logic gates are discussed later), the output voltage of the copy gate becomes and for logic “0” and “1,” respectively, as required to drive the FeSQUID of the next stage [Fig. 2(b)].
(a) Schematic of a Copy gate using a FeSQUID. The output of this configuration is not sufficiently large to drive the input of the next gate and hence, this configuration is not cascadable. (b) Modified version of the Copy gate of (a) where a hTron is used to convert the output voltage to the same level of the input so that two or more logic gates can be cascaded. (c) I–V characteristics of hTron showing the gate current-controlled superconducting to resistive switching.
(a) Schematic of a Copy gate using a FeSQUID. The output of this configuration is not sufficiently large to drive the input of the next gate and hence, this configuration is not cascadable. (b) Modified version of the Copy gate of (a) where a hTron is used to convert the output voltage to the same level of the input so that two or more logic gates can be cascaded. (c) I–V characteristics of hTron showing the gate current-controlled superconducting to resistive switching.
It is worthwhile to discuss the design methodology, working principle, and simulated results of FeSQUID-based logic family. First, we design one-input Copy gate utilizing one FeSQUID where the input is applied as voltage across the ferroelectric. Figure 3(a) shows the schematic of the Copy gate. In the case of logic “0” (−6 V) applied to the input and suitable bias current (I) is applied, the FeSQUID shows IC,high (>I) and becomes superconducting [Fig. 3(b)]. Therefore, almost all the bias current flows through FeSQUID and the hTron gate does not get enough current to switch the channel to its resistive state [Fig. 4(b)]. Due to the proper biasing of hTron, we get logic “0” (−6 V) at the output. Now, for logic “1” (+6 V) at the input, FeSQUID becomes resistive, driving most of the bias current to the gate of hTron which switches the channel to resistive state [Fig. 3(c)], and hence, we obtain logic “1” (+6 V) at the output.
(a) Schematic of FeSQUID-based Copy gate. Working principle of the Copy gate for (b) logic “0” and (c) logic “1” at the input. (d) Schematic of FeSQUID-based NOT gate. Working principle of the NOT gate for (e) logic “0” and (f) logic “1” at the input. Green and red colors correspond to the superconducting and resistive states, respectively. (g) Simulated results for the 1-input Copy and NOT gates.
(a) Schematic of FeSQUID-based Copy gate. Working principle of the Copy gate for (b) logic “0” and (c) logic “1” at the input. (d) Schematic of FeSQUID-based NOT gate. Working principle of the NOT gate for (e) logic “0” and (f) logic “1” at the input. Green and red colors correspond to the superconducting and resistive states, respectively. (g) Simulated results for the 1-input Copy and NOT gates.
Working principle of FeSQUID-based AND gate for inputs (a) “00,” (b) “01”/“10,” and (c) “11.” Operation of FeSQUID-based OR gate for (d) “00,” (e) “01”/“10,” and (f) “11” at the input terminals. (g) Schematic of XOR gate built cascading FeSQUID-based NOT, AND, and OR gates. (h) Simulated results for the two-input AND, OR, and XOR gates.
Working principle of FeSQUID-based AND gate for inputs (a) “00,” (b) “01”/“10,” and (c) “11.” Operation of FeSQUID-based OR gate for (d) “00,” (e) “01”/“10,” and (f) “11” at the input terminals. (g) Schematic of XOR gate built cascading FeSQUID-based NOT, AND, and OR gates. (h) Simulated results for the two-input AND, OR, and XOR gates.
Next, we design the NOT gate whose schematic is presented in Fig. 3(d). In the NOT gate, the gate of the hTron is connected in series with the FeSQUID. Therefore, for logic “0” (−6 V), FeSQUID becomes superconducting and passes enough current to the gate of hTron which consequently switches the channel to its resistive state and we get logic “1” (+6 V) at the output [Fig. 3(e)]. For logic “1” (+6 V) at the input, the exact opposite scenario occurs for the FeSQUID and hTron, and we get logic “0” (−6 V) [Fig. 3(f)]. Figure 3(g) presents the simulation results for the one-input Copy and NOT gates.
Having designed the one-input gates, next we design the two-input AND and OR gates where we use two FeSQUIDs and apply the inputs as voltages across the ferroelectric materials of the FeSQUIDs. Figure 4(a) captures the schematic of the AND gate where we connect two FeSQUIDs in parallel, and hence, if any of the FeSQUIDs become superconducting (“00,” “01,” and “10” cases), most of the bias current flows through that and deprives the hTron gate to get enough current to switch the channel to resistive [Figs. 4(a) and 4(b)]. Consequently, we get logic “0” (−6 V) at the output. However, for the “11” case at the input, both the FeSQUIDs switch to the resistive state driving the bias current through the hTron gate which creates logic “1” (+6 V) at the output [Fig. 4(c)]. On the contrary, in the OR gate, two FeSQUIDs are connected in series [Fig. 4(d)]. Therefore, only when both the FeSQUIDs remain superconducting (“00” case), the hTron gate does not experience enough current to switch the superconducting channel and creates an output of logic “0” (−6 V) [Fig. 4(d)]. For other cases (“01,” “10,” and “11”), at least one FeSQUID becomes resistive, and hence, the hTron channel switches to the resistive state and we get logic “1” (+6 V) at the output [Figs. 4(e) and 4(f)]. Lastly, to demonstrate the capability of FeSQUID-based logic family to handle fan-out, we simulate a two-input XOR gate using the FeSQUID-based NOT, AND, and OR gates. Schematic of the XOR gate is shown in Fig. 4(g). Figure 4(h) shows the simulation results for the two-input AND, OR, and XOR gates.
CONCLUSION
In summary, using voltage-controlled superconductivity in FeSQUIDs, we developed CMOS-like voltage-controlled superconducting logic family (one-input Copy and NOT gates and two-input AND and OR gates), which can potentially revolutionize the implementation of (i) classical control architecture of quantum computers, (ii) exascale high performance computing systems, and (iii) space electronics. Moreover, our designed logic circuits are transferrable to FeSQUIDs with different ferroelectric and superconducting materials as well as other voltage-controlled superconducting devices such as Josephson junction FET,45 Dayem bridge transistors,17,46 etc.
ACKNOWLEDGMENTS
The authors thank Michael L. Schneider and Matthew R. Pufall of NIST for the helpful scholarly discussions.
AUTHOR DECLARATIONS
Conflict of Interest
The authors have no conflicts to disclose.
Author Contributions
Shamiul Alam: Conceptualization (equal); Data curation (equal); Formal analysis (equal); Investigation (equal); Methodology (equal); Validation (equal); Visualization (equal); Writing – original draft (equal); Writing – review & editing (equal). Md Shafayat Hossain: Investigation (equal); Validation (equal); Writing – review & editing (equal). Kai Ni: Writing – review & editing (equal). Vijaykrishnan Narayanan: Writing – review & editing (equal). Ahmedullah Aziz: Funding acquisition (lead); Project administration (lead); Supervision (lead); Writing – review & editing (equal).
DATA AVAILABILITY
The data that support the plots within this paper and other finding of this study are available from the corresponding author upon reasonable request.