GaN-based power devices: Physics, reliability, and perspectives

Over the past decade, gallium nitride (GaN) has emerged as an excellent material for the fabrication of power semiconductor devices. Thanks to the unique properties of GaN, diodes and transistors based on this material have excellent performance, compared to their Si counterparts,¹ and are expected to find wide applications in the next-generation power converters. Owing to the flexibility and the energy efficiency of GaN-based power converters, interest toward this technology is rapidly growing: the aim of this Tutorial is to review the most relevant physical properties, the operating principles, the fabrication parameters, and the stability/reliability issues of GaN-based power transistors. For introductory purposes, we start summarizing the physical reasons why GaN transistors achieve a much better performance than the corresponding Si devices to help the reader understanding the unique advantages of this technology.

The properties of GaN devices allow for the fabrication of high-efficiency (near or above 99%),^2–6 kW-range power converters. Such converters can have switching frequencies above 1 MHz,^7,8 and—through proper design, integration and/or hybrid GaN/CMOS manufacturing—frequencies as high as 40–75 MHz can be reached.^9,10 High-frequency operation permits us to substantially reduce the size and weight of inductors and capacitors, thus resulting in a compact converter design. Further innovation will come from the design of monolithically integrated all-GaN integrated circuits (ICs): specific platforms, such as GaN on silicon-on-insulator (SOI) can be used for the fabrication of fully integrated power converters, containing smart control, pulse width modulation (PWM) circuitry, dead time control, and half bridge.^11,12 Such solutions, which can be tailored for switching in the 1–10 MHz range, can reach very short turn ON/OFF times, which are considerably smaller than in discrete gate drivers.¹² The availability of fast, small, efficient, and lightweight power converters can be particularly beneficial in the fields of portable/consumer electronics, automotive, and avionics.

GaN is a wide-bandgap (WBG) semiconductor and has an energy gap of 3.4 eV.¹³ This allows GaN devices to be operated at extremely high temperatures, thus substantially increasing the maximum power density that can be dissipated on a device, or permitting the use of light and small heat sinks. Over the last few decades, several reports on the high temperature and stable operation of GaN high-electron mobility transistors (HEMTs) have been published. Temperatures above 400–500 °C^14–16 have been reached and, for selected InAlN/GaN devices, up to 900 °C.¹⁶ Operation at high temperature is a first, substantial, advantage of GaN devices, compared to Si-based metal–oxide–semiconductor field-effect transistors (MOSFETs), that are typically rated for maximum operating temperature of 125–150 °C.

A second advantage of GaN arises from its high breakdown field (3.3 MV/cm¹³), which is 11 times higher than that of Si (0.3 MV/cm). The direct consequence of such a high critical field is that for withstanding a given voltage, a layer of GaN can be 11 times thinner than its Si counterpart, with consequent beneficial impact on resistivity. As a consequence, the use of GaN switches can substantially reduce the resistive losses in switching mode power supplies (SMPSs).

A third aspect to be considered is the high mobility of the channel: as will be discussed in Secs. III–V, GaN transistors are typically heterostructure devices. A high mobility (up to 2000 cm²/V s¹³) channel can be obtained through the formation of a two-dimensional electron gas (2DEG) at the heterointerface between the AlGaN barrier and the GaN channel layer. Such high mobility, along with the large saturation velocity (2.5 × 10⁷ cm/s), further contributes to reduce the resistivity of the devices. FETs based on AlGaN/GaN heterostructures are usually referred to as high-electron mobility transistors (HEMTs), or heterojunction field-effect transistors (HFETs).

At present, GaN devices are commercially available, and several products have been proposed, in three main voltage ranges: (a) low/mid-voltage (V_DS,max < 200 V) devices find applications in dc–dc power converters, motor drives, wireless power transfer, LiDAR and pulsed power applications, solar micro-inverters, class D audio amplifiers, robotics, and synchronous rectification. Such devices can have ON-resistances below 2 mΩ (for drain currents up to 90 A),¹⁷ or up to 100–200 mΩ (for operating currents in the range 0.5–5 A), depending on the final application.^18,19 (b) High voltage (V_DS,max up to 650 V) finds applications in telecommunication servers, industrial converters, photovoltaic inverters, servo motor control,²⁰ lighting applications, power adapters, converters for consumer electronics,²¹ class D amplifiers,²² and datacenter SMPS.^23,24 (c) Devices with ultrahigh voltage (V_DS,max above 1 kV). At present, no kV-range transistor based on GaN is commercially available. Commercial transistors with highest voltage rating have a maximum voltage of 900 V (see, for example, Ref. 25) and are expected to find application in data communication systems, industrial application, motor control, and photovoltaic inverters. As will be discussed in the article, several research papers demonstrated the feasibility of GaN transistors with breakdown voltages (BVs) above 1 kV^26–28 and proposed possible fabrication processes to target this voltage range. kV-range GaN transistors will compete with SiC-based devices in the industrial, automotive, and photovoltaic application environments.

As will be described in detail in the paper, current GaN devices have typically a lateral layout. Several key aspects related to device design, fabrication, and performance must be discussed in detail to understand how the performance of the transistors can be optimized through careful device design: this will be done extensively in Secs. III–VI of this paper. For introductory purposes, we remind here that in a HEMT, current flows between drain and source through a two-dimensional electron gas (2DEG), which is formed at the heterojunction between an AlGaN barrier and a GaN layer. Figure 1(a) reports the schematic structure of a GaN-based HEMT, showing the main layers that constitute the structure. Power GaN devices are typically grown on a Si substrate to minimize cost and maximize yield. Growing GaN on a Si substrate is particularly complicated, due to (a) the large mismatch of the in-plane thermal expansion coefficient (2.6 × 10⁻⁶ K⁻¹ for Si and 5.59 × 10⁻⁶ K⁻¹ for GaN²⁹), that may lead to cracking of the GaN layer during the cooling-phase after the epitaxial growth; (b) the large lattice mismatch [around 16% for Si(111)]^30,31 that may result in the propagation of dislocations through the GaN epitaxial layers, with consequent defect generation. A careful optimization of the buffer is needed in order to limit the propagation of such defects toward the 2DEG region; Fig. 1(b) reports a cross-sectional SEM image of the epitaxial layers of a GaN-based transistor. As can be noticed, the use of a step-graded buffer in combination with an AlN nucleation layer is used to release the strain and prevent the formation/propagation of dislocations.

The lateral structure described in Fig. 1 may have some limitations, when extremely high breakdown voltages and/or power densities are targeted. First, in a lateral transistor, the breakdown voltage scales with the gate–drain (G–D) spacing. Thus, devices with a high breakdown voltage can be fabricated but will be more resistive and will use a wider semiconductor area, thus resulting in a higher device cost. Second, the density of electrons in the 2DEG can be strongly influenced by surface charges: for this reason, the performance of the final devices is strongly dependent on the process and backend. To solve the limitation of GaN lateral devices, vertical device structures are currently being explored and investigated, in line with what has been done with Si and SiC components. In a vertical device [see a schematic structure in Fig. 1(c)], current flows through the bulk of the material, thus allowing high current and power densities. The density of electrons in the channel is modulated through a metal–oxide–semiconductor (MOS) stack, and a p-type body is usually employed to shift the threshold voltage toward more positive values. The breakdown voltage of a vertical GaN transistor depends on the thickness of the lightly doped drift region and not on the size and area of the device as in a lateral transistor. Vertical GaN devices represent the latest development in GaN technology, and the reader will find interest in the related concepts and applications, described in this paper.

As for every technology, there are some physical processes that may limit the performance and the reliability of GaN devices. The ON-resistance of a GaN transistors (and thus the density of electrons in the 2DEG) strongly depends on the intrinsic (spontaneous and piezoelectric) polarization charges of GaN, as well as on the presence of charges trapped at surface states (e.g., in the passivation layer or at the interface between the passivation layer and the AlGaN barrier) or in buffer states. For this reason, it is of fundamental importance to know and manage the surface- and buffer-related trapping phenomena that may limit the dynamic performance of GaN transistors, leading to a recoverable increase in ON-resistance (dynamic R_ON problem). Trapping in the epitaxial layers and/or at the gate stack may result in positive- or negative-bias threshold instability (PBTI or NBTI), and the related processes must be investigated and understood to be able to fabricate fast and reliable devices.

Finally, GaN-based transistors are operated at field, temperature, and frequency levels, which are unimaginable for conventional Si devices. Electric fields can be in excess of 3 MV/cm, and channel temperatures can be above 300 °C during operation, if lightweight heat dissipators are used. Such conditions may favor sudden or time-dependent breakdown phenomena, leading to the failure of the devices. Furthermore, operation at high frequencies may exacerbate the degradation processes related to hard-switching events. For this reason, it is of utmost importance to understand the degradation processes of GaN power devices and to identify ways and strategies for improving the robustness of the components.

This Tutorial presents a detailed overview on the physics, performance, and reliability of GaN-based power devices. In Secs. II–IV, the properties and physical parameters of GaN are discussed to help the reader understand the unique advantages offered by GaN compared to other semiconductors. The main figures of merit (FOMs) for high speed (Johnson FOM) and high power (Baliga FOM) devices are also introduced. Finally, the properties of AlGaN/GaN heterostructures and the related band diagrams are described in detail, and first-order formulas for the calculation of sheet electron charge and threshold voltage are introduced. In Sec. V, the properties, structure, and characteristics of lateral GaN devices are discussed. Specific details are given to the various approaches for normally off operations, to the main device parameters, and to the optimization of the buffer. A perspective on AlN-based devices and on possible strategies to increase the breakdown voltage is given, also by discussing devices with local substrate removal (LSR). Section VI deals with GaN vertical devices. First, the advantages of vertical GaN transistors are described. Attention is then given to the choice of the substrate (GaN-on-GaN vs GaN-on-Si) for vertical device manufacturing. Then, the various vertical device architectures are discussed and compared, in terms of performance and structural parameters. In Sec. VII, the stability of GaN devices is analyzed in detail. Specific focus is given to the role of surface traps, barrier traps, and buffer traps in modifying the main device parameters to present a clear overview of the topic. A complete overview of the dominant defects and deep levels in GaN is given in Sec. VII A to provide an exhaustive view of the problem. Finally, Sec. VIII describes the most relevant degradation processes that can limit the lifetime of GaN-based transistors. Specific attention will be given toward the degradation mechanisms induced by exposure to OFF-state stress, SEMI-ON-state regime, and ON-state degradation (with focus on gate reliability for p-GaN and insulated-gate devices).

Through a pedagogical approach, this paper helps the reader to understand the advantages of GaN technology and get familiar with the main performance, design, and reliability aspects.

GaN, along with its InGaN and AlGaN alloys, represents an excellent material for both optoelectronics and electronics. In the early GaN era, the research efforts on GaN have been driven by the need of fabricating high-efficiency short-wavelength (blue/violet) LEDs. GaN has a direct bandgap of 3.4 eV, thus being ideal for manufacturing ultraviolet optoelectronic devices. In addition, the energy gap of III-N alloys can be tuned between the 0.7 eV of InN and the 6.2 eV of AlN, thus, in principle, allowing fabrication of LEDs with ultraviolet (UVA, UVB, UVC), visible, and infrared emission.

Contrary to other semiconductors, like InP or GaAs, III-N semiconductors typically have a wurtzite crystal, with its characteristic hexagonal shape (see Fig. 2). It can be easily understood that this lattice arrangement does not have an inversion plane perpendicular to the c axis (0001) and, for this reason, the surfaces have either atoms from group III (In, Ga, Al) or nitrogen atoms.³³ The nature of the surfaces has a fundamental importance, since it determines the polarity of the polarization charges, as will be discussed in the following.

Table I reports the main parameters of GaN, as compared with other semiconductor materials, including Si, GaAs, SiC, AlN, diamond, and Ga₂O₃. The materials are ordered with increasing energy gap E_G, from left to right. Excluding the three semiconductors for which commercial devices are not available (gallium oxide, diamond, and aluminum nitride), GaN is the semiconductor with the largest energy gap, the largest critical field, and the highest saturation velocity. As a consequence, it is an ideal candidate for the fabrication of power semiconductor devices, capable of operating at high temperature and voltage levels.

Figure 3(a) reports the relation between breakdown field and energy gap for the semiconductor materials in Table I. As can be noticed, breakdown field has a power-law dependence on the energy gap, in the form $E c r i t∝ E G 2.3$⁠. This dependence is consistent with previous reports in the literature³⁵ and demonstrates the great advantage of using wide-bandgap semiconductors for fabricating electron devices with high breakdown voltage.

The Johnson figure of merit indicates that, in general, devices with high breakdown voltage are typically slower than devices with lower voltage rating.

Figure 3(b) reports the values of the Johnson figure of merit for the semiconductors listed in Table I; all values are normalized to that of GaN to allow for an easy comparison. As can be noticed, the Johnson FOM of GaN is slightly higher than that of SiC (0.556), comparable to β-Ga₂O₃ (0.978), and is much larger than that of Si (0.0379) and GaAs (0.0455). AlN and diamond are better than GaN, but their Johnson FOMs are between 2.5 and 3, thus having the same order of magnitude of GaN. While there is a substantial advantage by moving from Si/GaAs to GaN, the improvement obtained by changing to AlN and diamond is only incremental, in terms of the Johnson FOM.³⁶ 

The denominator of the last term is linked to the Baliga FOM^38,39 (that was initially defined as $μϵ E G 3$⁠) and identifies the material parameters that help minimizing the conduction losses in power transistors. This FOM is defined based on the assumption that power losses only originate from the ON-resistance of the FET. For this reason, it applies at relatively moderate frequencies, where conduction losses are dominant.³⁸ For higher frequency devices, one would have to consider also the contribution of switching losses. Figure 4(c) reports the Baliga figure of merit (calculated as $μϵ E c r i t 3$⁠) for the same set of semiconductors in Table I. All values are normalized to GaN: the plot indicates that the Baliga FOM of GaN is substantially larger than those of Si and GaAs, higher than SiC, similar to the one of gallium oxide. Diamond and AlN (ultra-wide-bandgap semiconductors) have a much higher Baliga FOM and can be considered interesting alternatives to further push the limits.

For GaN, AlN, and InN the related parameters are summarized in Table II. As can be noticed, by using alloys of GaN, AlN, and InN, it is possible to vary the bandgap of the alloy in a wide range, from 0.7 to 6.2 eV. In most cases, GaN transistors are based on AlGaN/GaN heterostructures, and AlN and AlGaN layers are used as nucleation and buffer layers, respectively. InAlN devices have also been investigated: lattice matched InAlN/GaN HEMTs allow an efficient down-scaling of the transistor dimensions, thus allowing to reach high cutoff frequencies.⁴⁰ 

Other band structure parameters of interest for GaN are the effective density of states in the conduction and valence bands (⁠ $N C=2.24⋅ 10 18 c m − 3$ and $N V=4.56⋅ 10 19 c m − 3$ at room temperature, RT), and the effective masses of electrons and holes (⁠ $m e=0.20$ and $m h=1.49$⁠).³⁶ 

Controlled doping of wide-bandgap semiconductors is not always straightforward: typically, mobile carriers in FET are induced through impurity doping, i.e., by introducing foreign atoms in a semiconductor lattice. The energy distance between the dopant level and the related band (⁠ $E C− E D$ for a donor level at energy $E D$⁠, or $E A− E V$ for an acceptor level at energy $E A$⁠) represents the dopant binding (or ionization) energy. The best dopants are relatively shallow, with binding energies in the range 0.01–0.05 eV. For GaN, only shallow donors are available (Si, $E C− E D=0.015 eV$⁠), while the conventional acceptor is magnesium that creates a level 0.16 eV above the valence band energy. As a consequence, it is relatively easy to achieve high-electron concentrations, whereas for reaching high hole densities, dopant levels in excess of $10 19 c m − 3$ are required. It is worth noticing that even high-quality GaN has a residual n-type (unintentional) conductivity, resulting in carrier densities in the range f $10 15– 10 17 c m − 3$⁠, depending on material properties. Such residual conductivity has been ascribed to native defects of the semiconductor (e.g., point defects, vacancies, antisites) and impurities (like carbon, oxygen, and hydrogen).⁴² The suppression of such defect-induced free carriers is very important for the fabrication of a highly insulating GaN layer to be used in devices with extremely high blocking voltages.

Contrary to conventional semiconductors, GaN has a unique advantage that helps obtain high carrier densities even in the absence of intrinsic doping: GaN, in fact, is a polar material and exhibits strong polarization effects.

As already mentioned, the wurtzite crystal of III-N semiconductors, which are typically grown epitaxially along the (0001) orientation, leads to the existence of polarization fields that are both spontaneous and piezoelectric. With zero external field, the total polarization P is equal to the sum of the spontaneous polarization $P s p$ and of the piezoelectric (or strain-induced) polarization $P p z$⁠. Bernardini et al.⁴⁶ investigated the polarization in GaN layers along the (0001) axis. Nitrogen has a higher electronegativity, compared to gallium. As a consequence, Ga and N atoms have anionic (+) and cationic (−) characteristics, generating a spontaneous polarization $P s p$ along the (0001) axis.³⁷ Wurtzite is the crystal arrangement with highest symmetry compatible with the presence of spontaneous polarization.^46–48 The arrangement of the cation and anion sublattices can lead to a relative movement from the ideal wurtzite position, favoring spontaneous polarization.⁴⁹ The orientation of spontaneous polarization is defined assuming that the positive direction goes from the metal (Ga) to the nearest nitrogen atom, along the c axis.⁵⁰  Figure 5 depicts the crystal structure of GaN and the sign and direction of the spontaneous polarization.

The strain in the crystal, and the displacement of the anion sublattice with respect to the cation sublattice, can lead to a piezoelectric polarization of the III-N semiconductors. A (simplified) representation of the polarization is given in Fig. 6, which reports a ball and stick diagram of the bond (tetrahedral) between gallium and nitrogen. In this figure, the Ga-polar configuration is represented. The electron cloud is closer to the nitrogen atoms, and this generates the polarization vectors. If the tetrahedron is ideal, the in-plane and vertical polarization components cancel each other.⁵⁴ When an in-plane tensile strain is applied [as shown in Fig. 6(a)], the polarization generated by the triple bonds decreases, and this generates a net polarization along the $( 000 1 ¯)$ direction. On the contrary, when an in-plane compressive strain is applied [as shown in Fig. 6(b)], the polarization generated by the triple bonds increases, and this generates a net polarization along the $(0001)$ direction.

To calculate the piezoelectric polarization, one needs to refer to the piezoelectric constants of the materials under analysis. Details on the main parameters were given in Refs. 46,50, and 55, and a comprehensive summary was presented in Ref. 51; here, in Table IV, we report the values of piezoelectric constants $e i j$ and lattice parameters $a 0$ and $c 0$ for GaN, InN, and AlN.

Here, $ϵ z=( c − c 0)/ c 0$ represents the strain along the c axis, while the in-plane strain $ϵ x= ϵ y=( a − a 0)/ a 0$ is assumed to be isotropic. a and c are the lattice constants of the strained layers, and differ from $a 0 and c 0$⁠.

In a GaN layer, polarization charges are present on each unit cell. As schematically depicted in Fig. 7, the internal polarization charges cancel each other. Only the $Q π$ and $− Q π$ at the N- and Ga-faces remain and form a charge dipole [Fig. 7(c)]. Based on the numbers given in Table III, the spontaneous polarization charge in GaN has values in the range of $1.8−2.1⋅ 10 13 e − / c m 2$⁠. In the absence of other charges, the polarization charge would lead to the presence of a dipole, resulting in a fairly high electric field, in the range of MV/cm. Such a dipole is screened through the formation of a screening dipole $( Q s c r)$⁠. In the absence of the screening dipole, a non-physical situation would form. As discussed in Ref. 49, a first hypothesis would be that the screening dipole originates from ions from the atmosphere $( H +, O H −)$⁠; however, the dipole is present also in material grown in atmosphere free of counterions, like during molecular beam epitaxy (MBE) growth.

A different interpretation can be given by considering the presence of donor states at the surface of the GaN layer,^57,58 as schematically represented in Fig. 8(a). In the absence of compensating charge, due to the presence of the polarization dipole $± Q π$⁠, an electric field is present in the GaN layer, and the band diagram shows a linear slope [Fig. 8(b)]. If the GaN layer is sufficiently thick, the donor states pin the Fermi level at the surface (at the donor level $E D D$⁠), and the screening charge $N D D +$ at the surface is formed. The presence of a surface level $E D D$ has been proved also experimentally.⁴⁹ Realistic GaN layers typically have an n-type conductivity, as mentioned above. The ionized (bulk) donors also contribute to the overall charge balance. For a thick GaN layer [see Fig. 8(d)], the bands are nearly flat (corresponding to a negligible field), apart from the surface region. The polarization charge $− Q π$ at the surface is compensated by the positive charge of the ionized surface defects $N D D +$ and by the total density of charges in the depleted n-type GaN.⁴⁹ 

The core of a GaN-based HEMT is the AlGaN/GaN heterostructure. Both the GaN and the AlGaN layers are typically left undoped to minimize electron scattering at impurities. Based on the considerations above, undoped GaN has a weak n-type conductivity, with electron densities that depend on the quality of the epitaxy, and that—even in the best case—are higher than 10¹⁵ cm⁻³⁴⁹ (early GaN films were showing a high n-type conductivity, in the range of 10¹⁷–10¹⁸ cm^−3.59,60). Optimizing the background electron density in lateral and vertical HEMTs requires a tuning of the growth process and the control of the residual impurities (such as carbon, see for instance Ref. 61).

Figure 9 shows the charge distribution, the electric field profile, and a schematic band diagram for an AlGaN/GaN heterostructure used in HEMT technology. In the figure, t is the thickness of the AlGaN layer, while the 2DEG is supposed to be located at a position d, a few nanometers far from the heterojunction, on the GaN side.

At the surface of the AlGaN layer, the total charge is determined by the sum of the charge of the surface donors and of the polarization charge of the AlGaN layer, $q N D D +− Q π ( AlGaN )$⁠. At the AlGaN/GaN heterojunction, the total charge is given by the difference between the polarization charges of AlGaN and GaN, i.e., $Q π ( AlGaN )− Q π ( GaN )$⁠. For gallium polar material, this is a positive number, since AlGaN has a higher polarization, compared to GaN. In the triangular potential well formed near the heterojunction, on the GaN side, a two-dimensional electron gas is formed. For simplicity, we consider this sheet of charge to be located in $x=d$ (position of the centroid of the electron distribution).

By simple calculations (see details in Ref.49), one can calculate the position d of the 2DEG, with respect to the heterointerface. Here, the 2DEG is considered an ideal 2D sheet of electrons located at a distance d from the interface, on the GaN side. For an AlGaN/GaN heterostructure, a typical value of d is 2 nm.⁴⁹ 

At the bottom of the GaN layer, at the interface with the substrate, a screening charge compensates the (positive) component $Q π ( GaN )$⁠. The reader should note that in more realistic structures, other layers [e.g., a C-doped layer, a step-graded or a superlattice (SL)-based buffer, and an AlN nucleation layer] are placed between the GaN channel layer and the substrate; these layers are not shown here for simplicity.

When a potential $V G$ is applied to the gate (through a suitable metal deposited on the AlGaN barrier), the charge in the 2DEG can be modulated: a more positive voltage will fill the channel, whereas moving to negative values of $V G$ will lead to the depletion of the 2DEG.

A typical range of interest for the mole fraction is between 0.2 and 0.4; such values are sufficiently high to give a reasonable polarization charge (which is necessary for generating electrons in the 2DEG), and enough conduction band discontinuity at the AlGaN/GaN heterointerface (which is necessary to ensure a good confinement of the 2DEG electrons). At the same time, the use of molar fractions higher than 0.4 may be critical, since the thermal and lattice mismatch between AlGaN and GaN may lead to high defect density and rough interfaces that may limit the overall device performance.

As can be noticed, when the mole fraction x is around 0.2–0.3, the sheet charge density is around $10 13 c m − 3$⁠. With increasing thickness of the AlGaN layer, the density of electrons in the 2DEG increases, since the conduction band at the channel edge drops further below the Fermi level at the AlGaN/GaN interface (see also the band diagram in Fig. 9). As can be understood, AlGaN/GaN HEMTs are intrinsically normally ON. At zero gate bias, the channel is formed, with a high-electron density. A first possible approach to change the threshold voltage (by keeping the same Al content in the barrier) is to reduce the thickness of the AlGaN barrier. For sufficiently thin AlGaN barriers, the electron density falls to zero, and the 2DEG vanishes. This effect has also been observed experimentally, see for instance Ref. 57. This is just one of the possible approaches to achieve normally off operations in HEMTs; an excessive thinning of the barrier, along with the related etching process, may result in a significant increase in the leakage, and countermeasures are required to guarantee a good device performance.

In high-voltage devices, the gate–drain spacing is typically longer than the gate length. Figure 12(b) reports the variation of the ON-resistance (multiplied by the gate width $W g$⁠) as a function of the target breakdown voltage for devices having different gate lengths (0.25 and 1 μm). For mobility and sheet charge density values of 1400 cm²/V s and 10¹³ cm⁻² were used. As can be understood, for low-breakdown voltage devices (corresponding to devices with a short gate–drain distance), the ON-resistance is strongly determined by the gate length. Decreasing the gate length from 1 to 0.25 μm can lead to a substantial reduction in the resistive losses. On the contrary, for high breakdown voltage devices, the resistive contribution of the gate–drain access region becomes relevant, and $R o n$ scales with the breakdown voltage. Figure 6(b) also shows that the use of GaN devices with nearly ideal breakdown field (3.3 MV/cm, see Table I) can lead to a substantial improvement in ON-resistance, compared to the more conservative case of 1 MV/cm reported in previous publications.³⁷ Optimizing the breakdown field of the material is a key step for minimizing the resistive losses in power semiconductor devices.

Besides resistive losses, switching losses can also play a relevant role in limiting the efficiency of a switching mode power converter. One of the parameters used to quantify the switching losses related to a specific transistor is the gate charge $Q G$⁠. For understanding the meaning of this parameter, we consider the simple circuit in Fig. 13(a). Here, the FET is supposed to be ideal, and three capacitances $C G S, C G D, and C D S$ are added to model the parasitic capacitive components. A fixed current is forced into the gate, and the measured gate voltage is plotted as a function of the charge flowing toward the gate. Figure 13(b) shows the schematic gate-charging curve, during a turn-on event, i.e., when the device switches from the OFF-state (high drain voltage, zero current) to the ON-state (low-drain voltage, high current). At device turn-on, the gate–source voltage $V G S$increases; when $V G S$ reaches the threshold voltage $V t h$⁠, current starts flowing through the device. At the same time, the gate–source capacitance $C G S$ is charged, until the $V M i l l e r$ voltage (and the corresponding plateau) is reached. At this point, $C G S$ is completely charged, and the drain current reaches the value fixed by the circuit. At the same time, $V G S$ becomes almost constant, and the drive current starts charging the Miller capacitance $C G D$⁠. This process goes on until the capacitance $C G D$ is fully charged. When both $C G S$and $C G D$are fully charged, the gate voltage starts increasing again. Through this experimental procedure, the charges $Q G S$ and $Q G D$ can be calculated. The gate charge $Q G S+ Q G D$ is the minimum charge required to turn on the transistor⁶⁶ and is thus representative of the switching losses.

A low value of $Q G S+ Q G D$results in the device's ability to achieve high commutation speed (dV/dt) and in a substantial reduction in switching losses.⁶⁷ A low gate charge also results in a reduced gate drive power for GaN devices, compared to Si components.⁶⁸ Since, as stated above, the dc losses depend on the $R o n W G$ product, and the ac losses are proportional to $Q G/ W G$⁠;³⁷ the $R o n⋅ Q G$ product is an important parameter describing the switching efficiency of a given device. In a recent paper,¹ Chen et al. compared devices based on Si, SiC, and GaN in terms of figures of merit. They showed that, for devices with comparable ON-resistance, the $R o n⋅ Q G$ product can be around $3800m Ω nC$ for a Si superjunction MOSFET, in the range of $1950–3480m Ω nC$ for SiC-based FETs, and around $290–300m Ω nC$ for an E-mode GaN transistor. This result indicates that GaN E-mode HEMTs can contribute to a substantial reduction in switching losses, compared to conventional semiconductor transistors.

A further advantage of GaN-based transistors is the absence of reverse recovery charge. Si -based power transistors have an intrinsic body diode, whose presence results in a large reverse recovery charge during commutation. For a Si superjunction (SJ) MOSFET, the product of ON-resistance (R_DS,ON) and reverse recovery charge (Q_rr) can be in excess of 300 mΩμC.¹ On the other hand, lateral GaN devices are based on the high-electron mobility transistor (HEMT) concept and do not have any body diode. HEMTs are majority carrier devices, and the lack of minority carriers leads to a near-zero Q_rr (R_DS,ON × Q_rr down to 2.2 mΩ μC¹), with beneficial impact on the switching losses.

The rapid evolution of wide-bandgap semiconductors in the recent years has positioned lateral GaN transistors as key enablers in the power device market. The interest in power applications has undergone a remarkable shift due to the technological advantages of GaN HEMTs, which allow for simultaneous high voltage, high current, and low ON-state resistance, resulting in high power and high-efficiency operation. In addition, the wide bandwidth provides a robust and reliable technology capable of operating at high frequency and high temperature. This is why GaN-based lateral power electronic devices are emerging as switching components for next-generation high-efficiency power converters. Furthermore, the GaN-on-Si technology platform offers the best cost figures for commercialization of these products, although technologically very challenging. For instance, a complex GaN buffer for stress management and insulation purpose is required. This paves the way for a growing number of applications in various fields, including consumer electronics, transportation, and energy, as well as several industrial, automotive, and aerospace applications, such as rectifiers and high-voltage converters. As can be seen in Fig. 14, each application uses a specific voltage range. In terms of the device market, currently, the majority of GaN components are designed for 600/650 V applications and below (see Fig. 15). 900 V devices are also available.

GaN-on-Si typical HEMT structures (Fig. 16) consist of several epilayers. These layers include materials with a wider bandgap and a lower bandgap, and an AlGaN/GaN heterostructure. At the interface between AlGaN and GaN, a two-dimensional electron gas (2DEG) is created with an electron channel accumulation without extrinsic doping. The 2DEG formation results from both the spontaneous and piezoelectric effects.^50,56,69 The thickness and Al content of the AlGaN barrier layer defines the resulting polarization. It can be pointed out that a high-electron mobility above 2000 cm²/V s can be combined with a high carrier density within the 2DEG, thus resulting in excellent electrical performance.

One of the main issues for GaN-based heteroepitaxy is the lattice mismatch and difference in thermal expansion coefficients with the substrate. This generally leads to a high dislocation density, which may be a source of leakage current under high electric field and subsequent device degradation. Residual stress may be created, inducing eventually cracks. The most common materials used as substrates are Si, sapphire, SiC, and, more recently, bulk GaN. In all cases, the epitaxial layers have rather high dislocation density (10³–10¹⁰ cm^−270,71). Some properties of the substrates typically used for GaN-based epitaxy are shown in Table V. For power applications, the Si substrate is preferred because of its low cost and availability in large diameter (up to 12 in.), despite a 17% lattice mismatch and a strong difference in thermal expansion coefficient between GaN and Si, which makes the growth challenging. Although sapphire substrates combine a high resistivity and low cost, the low thermal conductivity leads to a significant self-heating, which is not suitable for power applications. Finally, the high cost of SiC is prohibitive for large volume applications despite its outstanding properties.

Emerging GaN substrates, perfectly lattice matched, are of interest for vertical GaN architectures, see also Sec. VI.

In order to grow crack-free and high-quality GaN films by reducing the defect density, especially when using Si substrates, the tensile stress during the growth and cooling process needs to be limited. An AlN nucleation layer (NL) is typically used as an initiating layer for GaN growth. By using an AlN NL, the melt-back etching of Ga into Si can be avoided.⁷² Moreover, the AlN NL provides a GaN layer with a compressive strain due to the 2.5% lattice mismatch between AlN and GaN. This is necessary for compensating the tensile stress generated during the cooling process. Figure 17 shows a TEM image of the interface between the Si substrate and the AlN nucleation layer. Dislocations are reduced but still present across the buffer layers.

Whatever the choice of substrate, the buffer layers are critical. The high 2DEG sheet charge density in GaN-based HEMTs enables significant drain current densities. Inadequate carrier confinement within the channel leads to soft pinch-off characteristics and high subthreshold leakage. The presence of a high defect or impurity density in the buffer produces high leakage currents and poor device reliability. Consequently, on top of a high-quality AlN NL, proper buffer configuration and material quality is mandatory.

A well-known approach is the use of a step-graded AlGaN buffer, as shown in Fig. 18. Several micrometers thick Al_xGa_1−xN buffer layers with various Al contents enable us to further mitigate lattice and thermal-mismatch detrimental effects. The interest of this approach is also to improve the 2DEG electron confinement under high electric field, by limiting the carrier injection into the buffer layers, i.e., to the so-called punch-through effect. Another practical route to significantly increase the buffer layers' resistivity is the introduction of intentional compensating centers. Iron or carbon doping can be used to produce highly resistive buffers (carbon being the choice for GaN-on-Si GaN devices). Finally, superlattice (SL) buffers consisting in many periods of thin AlN/GaN pairs have been proved to be one of the most effective techniques both to control the stress and enhance the blocking voltage.⁷⁵ With thick SL buffers, high crystal quality and smooth surface of the top-GaN layer can be obtained resulting in superior performance as described further in this paper.

The epitaxial heterostructure is completed with a cap layer, which is generally composed of GaN or SiN to reduce the oxidation of the underlying AlGaN film. It is important to note that surface states⁵⁷ on top of the AlGaN constitute the origin of the 2DEG, as discussed in Sec. IV. However, surface defects may also be detrimental to the device performance. Under operating conditions, trapping at surface defects can create a virtual gate between gate and drain terminals, depleting unintentionally the 2DEG and thus severely degrading the device performances and/or reliability. Negatively charged surface states may compensate the donor atoms, thus depleting the channel between the gate and the drain. A surface passivation layer, typically SiN, allows us to mitigate the 2DEG depletion as can be seen in Fig. 19.

Lateral heterostructure devices are inherently normally ON, i.e., they conduct current when no gate voltage is applied. This raises safety concerns because in case of a malfunctioning gate driver, the GaN transistor is not automatically switched off and an uncontrolled current flow can damage the entire system. Furthermore, normally ON transistors make circuit designs more complex because a negative-voltage supply is required. Thus, a substantial research effort was focused on creating normally off devices in recent years.

Thicker AlGaN barriers and higher polarization differences between AlGaN and GaN lead to more negative V_TH as they increase n_s at zero bias. From this equation, it is clear that several degrees of freedom exist to tune the V_TH, such as changing the Schottky barrier height or the 2DEG carrier density related to the AlGaN barrier layer, which is dependent on the Al content and its thickness.

Different topologies have been proposed in order to achieve normally off GaN HEMTs: a cascode configuration^78–80 combining a Si normally off MOSFET and a normally ON GaN HEMT, the use of a HEMT with fluorine implantation under the gate,^81–83 a gate recessed MIS-HEMT (metal–insulator–semiconductor) with partial^84,85 or complete⁸⁶ AlGaN barrier removal, and a p-GaN-gated^26,87,88 HEMT.

The cascode configuration uses a high-voltage normally ON GaN HEMT connected in series with a low-voltage Si MOSFET in the switching circuit, as can be seen in Fig. 20. The Si MOSFET controls the ON and OFF-state switching of the GaN HEMT. When a positive gate voltage above the threshold voltage is applied to the MOSFET, the GaN HEMT gate voltage is close to zero and the device is turned on. As the two devices are connected in series, when a voltage is applied to the drain of the HEMT, the current will also flow through the MOSFET. On the other hand, when no gate voltage is applied to the MOSFET to turn it off, no current can flow through the channel of the HEMT. In addition, any increase of the drain voltage will be handled by the HEMT, thus resulting in a high reliability.

Therefore, the cascode configuration enables us to take advantage of the positive threshold voltage of the MOSFET as well as the low ON-resistance of the 2DEG, together with the high breakdown field of the GaN HEMT in OFF-state conditions. However, it can be noticed that this approach limits the high-temperature operation by the presence of the Si device. In addition, the packaging complexity and size are increased and parasitic inductances are introduced, and this may have an impact on the switching performance of the circuit.

Another approach consists of etching the AlGaN barrier layer under the gate area followed by a deposition of a gate dielectric insulating layer. The AlGaN barrier layer is fully etched by plasma in the gate region (Fig. 21). This allows for high threshold voltages, while the thick gate dielectric enables a large maximum forward gate bias (>+10 V).

The choice of the dielectric is extremely important, as it will directly impact the channel mobility within the 2DEG⁸⁹ and the stability of the threshold voltage.⁹⁰ Also, the dielectric quality and surface roughness of the etched area are critical parameters, and the interface charge density needs to be well controlled. Several mechanisms, involving the surface states and related trapping, have been proposed to explain the possible origin of the device degradation phenomena (see Secs. VII B and VII C).

Fluorine ions implanted into the AlGaN layer self-aligned to the gate (see Fig. 22) can also create a normally off behavior.^91,92 The negative ions into the barrier change the surface potential, thus depleting the 2DEG. However, the V_TH stability after annealing at high temperature and/or under high electric field is a source of concern for this approach.^93,94 Moreover, previous studies have shown the relation between fluorine and current collapse,^95,96 which may be an issue for power switching applications.^95,97 Other reports focused on fluorine-treated MIS/MOS-HEMTs, see for instance Refs. 83 and 98.

An attractive method to achieve normally off GaN transistors is the use of a p-doped GaN layer⁹⁹ under the gate area (Fig. 23). The presence of the p-GaN layer lifts the band diagram to higher energies (Fig. 24), so that the 2DEG depletion occurs even in the absence of an applied external bias. In order to maximize the 2DEG depletion induced by the p-GaN cap layer, the Al mole fraction in the barrier and the thickness of the barrier must be carefully optimized. It has been demonstrated that to achieve a good depletion of the 2DEG, the Al content and thickness of the barrier should be kept relatively low.¹⁰⁰ Greco et al. determined the energy band diagram by Schrödinger–Poisson (Fig. 25) of two structures with an identical barrier thicknesses (25 nm) but different Al content (12% and 26%) by using a p-GaN layer thickness of 50 nm with an acceptor concentration of 3 × 10¹⁹ cm⁻³. Figure 25 clearly shows that despite the presence of the p-GaN layer, the high Al content structure still exhibits a normally ON behavior with the conduction band below the Fermi level at the AlGaN/GaN interface; on the contrary, the structure with reduced Al content can reach normally off operations. Similarly, the conduction band diagram of p-GaN/AlGaN/GaN heterojunctions with two different barrier thicknesses (10 and 25 nm, with a fixed Al content of 26%) has been simulated. As can be noticed, the structure with a thickness of 25 nm reveals a normally ON behavior, whereas the thinner barrier results in normally off devices. Based on a series of tests, a summary graph can be produced showing the normally ON and normally off area with respect to the thickness and Al content of the AlGaN barrier layer (Fig. 26).

Also, a high Mg concentration in the p-GaN layer is required, which should be balanced with the deterioration of the crystal quality for too high Mg doping concentration. The p-GaN layer has shown a wide process window in terms of thickness and doping, which eases process control requirements. However, the low selectivity of the etching process between the p-GaN and the barrier layer needs to be carefully optimized in order to achieve a stable high threshold voltage.⁹⁵ 

The presence of a p-GaN layer above the AlGaN barrier and the GaN channel creates a p–i–n diode. When the device is in the ON-state (i.e., with positive gate bias, PGB), this diode may gradually turn-on, resulting in an increase in gate current. The amount of current is strongly dependent on the properties of the metal/p-GaN interface. In general, most single-metal contacts to p-GaN have a Schottky-like nature: this is due to the wide bandgap of GaN (3.4 eV) and its large electron affinity (4.1 eV^101,102). From these numbers, it appears evident that a ohmic contact on p-GaN would need a work function in excess of 7 eV, and this is not the case for common single-metal contacts based on Pt (work function = 5.65 eV¹⁰³), Pd (work function = 5.12 eV¹⁰³), and Ni (work function = 5.15 eV¹⁰³). As a consequence, the metal/p-GaN contacts are not ohmic in strict sense; their conductivity depends on the properties of the materials formed at the metal/semiconductor interface during deposition and annealing.¹⁰⁴ 

Depending on the choice of the metal, on the doping of p-GaN and on the process parameters, the metal/p-GaN contact can have a higher (referred to as ohmic) or lower (Schottky) leakage current. Ohmic contacts have been reported, see, for example, Refs. 88,104, and 105. Recent reports indicated that by using a titanium nitride (TiN) contact,¹⁰⁶ it is possible to significantly reduce the gate leakage for transistors. The use of a Schottky-like contact can significantly reduce the gate leakage; however, degradation phenomena related to the depletion and high electric field across p-GaN must be avoided, as discussed in Sec. VII B. On the other hand, a forward-biased gate diode may require a specific driving strategy,¹⁰⁷ e.g., based on the use of a RC network. A ohmic contact can also favor hole injection and, in some cases,¹⁰⁵ promote conductivity modulation.

Compared to conventional planar AlGaN/GaN HEMTs, tri-gate transistors feature fins patterned in the gate region, which are conformably covered by a 3D gate electrode [Figs. 27(a) and 27(b)]. While such architecture was first introduced for Si ultra-scale MOSFET in 2002¹⁰⁸ to address the short channel effects, it was soon adopted for power devices. The first tri-gate GaN demonstration appeared in 2008,¹⁰⁹ followed by several other works that showed the several benefits of such architecture, such as the improved current stability, the lower subthreshold slope, and the reduced OFF-state leakage.^110–113 

The most interesting feature of the tri-gate is, however, its ability to modulate the device threshold voltage (V_TH) by simply tuning the fin width (w_fin) [Fig. 27(c)]. Such an effect has been attributed to the partial AlGaN strain relaxation when patterned into fins and by the fin sidewalls depletion due the side gate electrode.^115–117 

The dependence of the device V_TH on the fin width can be used to achieve a normally off operation by simply designing the proper w_fin by lithography, without the need for any critical etching as for gate recess or p-GaN gates. However, early demonstrations based on this approach typically presented still negative V_TH (at 1 μA/mm) and degraded ON-resistance due to the very small fin width required to achieve a normally off operation.^{110,118–120} Recently, a tri-gate device with 20 nm-wide fins in combination with a large work function gate metal stack (Pt/Au) successfully showed a full normally off operation with a V_TH of 0.64 V (at 1 μA/mm) and a competitive R_ON of 7.4 Ω⋅mm.¹²¹ To achieve such performance, however, very high-resolution lithographic processes are required both to define the fin width (which sets V_TH) and to reduce the gap in-between fins (which degrades R_ON). Since, at the moment, the lithographic resolution in power devices foundries is still in the order of several hundreds of nm, it is interesting to find solutions to increase the minimum required w_fin.

A promising approach consists of combining the tri-gate architecture with conventional methods to achieve a normally off operation such as recessed gate and p-GaN cap. This allows us to achieve large positive V_TH values while keeping the benefits of the tri-gate architecture and relaxing the lithographic requirements. The first demonstration of such an approach appeared in 2012¹²² with the integration of the tri-gate architecture with AlGaN barrier recess, followed by a more recent work¹²³ in 2019 that showed promising V_TH of 1.4 V (at 1 μA/mm) and R_ON of 7.3 Ω mm. Moreover, the tri-gate architecture can also be integrated with the p-GaN cap approach, allowing us to further increase V_TH with respect to the planar case and relax the trade-off between V_TH and the heterostructure sheet resistance.¹²⁴ Finally, the tri-gate architecture can also be combined with promising p-type oxides, such as NiO, which can be conformably deposited around the fin and help us to further shift the device V_TH without the need of complex p-GaN regrowth.¹²⁵ 

At the moment, commercial GaN normally OFF devices are based either on the cascode or the p-GaN technology. Cascode devices have demonstrated high reliability, obtaining several automotive certifications, and present large gate swing and robustness, which is highly appreciated by circuit designers used to work with Si devices. On the other hand, the introduction of the Si low-voltage device may lead to more complex and costly packaging. In parallel, normally OFF GaN devices with a p-GaN cap structure allow us to achieve a normally OFF operation with a good reliability and quite simple fabrication. However, the p-GaN technology may present some limitations in terms of gate swing. While fluorine implantation seems to have lost steam due to long-term and high-temperature reliability concerns, gate recess could leverage on the trade-off found for p-GaN devices and result in good performance. Thanks to current and future research efforts, it is expected that the technology will improve and that the current issues regarding the GaN etched interface and the high-quality gate dielectric layer will be solved. Such research could strongly benefit also the tri-gate technology, which faces similar issues regarding the sidewalls interface quality and the gate dielectric. Moreover, the development of GaN logic [both direct-coupled FET logic (DCLF)^126–129 and CMOS^130–132] will require the adoption of higher-resolution lithographic lines, which would allow for a reduction of the minimum fin width, making the tri-gate and its combination with gate recess a viable future technology.

Converters based on MOSFETs have the ability to survive a limited exposure to voltages above the device rating, according to the specified avalanche energy rating. However, lateral GaN HFETs do not have the potential for avalanche breakdown¹³³ because they do not rely on a p-n junction for blocking voltage and may experience catastrophic dielectric breakdown when exposed to sufficient overvoltage.¹³⁴ This breakdown is destructive and non-recoverable.

The main sources of leakage current and related breakdown voltage (V_BR) for an AlGaN/GaN HEMT power transistor on an Si substrate are the following (see Fig. 28):

• Punch-through effect reflecting a parasitic electron injection into the buffer.

• Leakage current through the passivation layer and/or due to a surface related conduction.

• Vertical breakdown, through the total buffer thickness, that can be due to a poor doping compensation of the buffer.

Different approaches have been developed in order to mitigate these leakage paths and associated premature breakdown while avoiding trapping effects.

• - The use of a high-quality dielectric for surface passivation reduces leakage at the surface and at the interface with the barrier.¹³⁵ 

• - Proper doping compensation into the buffer layers, generally carbon or iron doping,^136–138 enables us to significantly enhance the buffer resistivity and consequently avoid carrier injection. Furthermore, back barrier^139,140 based on graded AlGaN or AlN material has been developed in order to reduce this phenomenon, increasing the blocking voltage. In both cases, the thickness of the GaN channel region must be carefully optimized with the aim of achieving a high-electron density in the 2DEG, a good electron confinement in the channel, and low trapping effects, especially in the case of doping compensation.^141,142

It can be pointed out that the AlGaN/GaN transistor breakdown voltage scales linearly for small gate–drain distances (typically below 15 μm), while larger gate–drain distances result in a saturation of V_BR due to the conduction into the substrate triggered by the vertical electric field. Extensive research is carried out to overcome the breakdown mechanisms and further push the limits of GaN-on-Si HEMTs.

In addition, the crystal quality is an important factor. Considering the high material defect density in GaN/Si epilayers, recent studies^143,144 showed that the presence of defects may impact on the breakdown voltage.

AlGaN/GaN devices are based on a lateral design and a high-concentration two-dimensional electron gas. These features lead to an inhomogeneous electric field distribution in the OFF-state with a large peak at the gate electrode edge. If not treated properly, this results in the early breakdown of the device and in very limited voltage blocking capabilities.^145–150 To address the inhomogeneous electric field distribution, field plate (FP) structures are typically employed. As shown in Figs. 29(a)–29(d), the FP helps us to extend the depletion region from the gate to the drain electrode, alleviating the electric field peak at the gate edge. Various designs of field plates have been developed^148,149,151 (Figs. 29 and 30), including the single FP, multiple FPs, and the slant field plate, which is the most effective but also very challenging to realize in a planar process. These structures are based on the precise control of the dielectric thickness, which sets the field plate threshold voltage and should be carefully designed. For high-voltage GaN devices (typically 650 V), several FP structures with increasing dielectric thickness are combined to smoothen the electric field profile.¹⁵² Under this point of view, the tri-gate architecture provides an interesting solution for the design of the lower voltage section of the FPs since the fin width can be easily designed in a slanted shape by lithography to gradually increase its threshold voltage. This results in an optimal electric field distribution, which leads to significant breakdown voltage improvement.^112,153 Moreover, the ability to precisely tune the field plate threshold voltage is of great importance for AlGaN/GaN Schottky barrier diodes (SBDs) as it enables us to reduce the voltage drop on the Schottky contact and thus greatly improve the diode blocking performance.^153–157 

Unintentionally doped (UID) GaN buffer layers deliver insufficient resistivity for high-voltage operation due to the residual n-type conductivity of GaN, which can induce parasitic leakage paths, thus increasing the OFF-state leakage current. As previously mentioned, high resistivity can be achieved by doping with deep acceptor impurities (such as C atoms) to compensate the background donors. However, this approach can generate severe current collapse, if the buffer is not carefully optimized.^161–163 

To further improve the carrier confinement while suppressing undesirable trapping effects, the doping compensation can be combined with the use of an AlGaN back barrier⁷⁵ or superlattices^164,165 consisting in AlN/GaN pairs (see Fig. 31). By alternating thin layers of high crystalline quality wide-bandgap semiconductors (e.g., AlGaN, AlN, or GaN), the accumulation of internal stress can be minimized, thus creating a highly insulating buffer with low buffer trapping effects.

Tajalli et al. showed that the insertion of superlattices (SL) into the buffer layers allows pushing the vertical breakdown voltage above 1200 V without generating additional trapping effects as compared to a more standard optimized step-graded AlGaN-based epi-structure using a similar total buffer thickness (see Fig. 32). Characterization of fabricated transistors by means of back-gating transient measurements reflects the much lower trapping effects and the advantages of the SL (Fig. 33).

A limiting factor for the breakdown voltage of GaN-on-Si transistors is the poor critical electrical field strength of the Si substrate, together with a parasitic conduction at the buffer/substrate interface. In order to suppress the parasitic conduction phenomenon, local Si substrate removal (LSR)¹⁶⁶ has been shown to be very effective leading to significantly improved blocking voltage up to 3 kV.^27,167

Dogmus et al. used the following device processing, which consists in ohmic contacts formed directly on top of the AlGaN barrier by rapid thermal annealing. After device isolation, a metal–insulator–semiconductor gate structure was employed by depositing an Ni/Au metal stack on top of the in situ SiN cap layer. Once the front-side processing was completed, the Si substrate is locally etched up to the AlN nucleation layer around the entire device (see Fig. 34). Devices with and without LSR have been fabricated on the same samples, eliminating any processing or epi variations during the device characterization. Electrical characterization showed a slight decrease of the maximum current density after LSR as can be seen in Fig. 35 due to self-heating effects.³⁵ Further improvement of the heat dissipation would be required to avoid the decrease of the current density. On the other hand, a drastic enhancement of the blocking voltage is achieved by locally replacing the substrate with a wider bandgap material (Fig. 36).

Furthermore, the effects of Si removal were investigated by Raman thermometry,^167,168 which revealed a worsening of the thermal performance. A significant improvement of the thermal dissipation is obtained after the AlN and copper deposition.

As the AlGaN/GaN power technology is reaching its maturity and increasing its market share, research on this topic is likely to follow two parallel paths. On the one hand, there will be growing interest on the aspects directly related to the realization of a successful commercial product such as trapping, reliability, stability, packaging, and circuit operation. On the other hand, researchers will continue to come up with novel device structures and designs to improve performance and take full advantage of the GaN material properties for future generations of high-efficiency devices. Under this point of view, a few recent promising directions are presented below, which are rapidly growing and offer a significant advance in device performance.

Ultra-wide-bandgap materials such as AlN (6.2 eV) and related Al-rich AlGaN channel could allow for further improvement, especially in terms of voltage and temperature operations. This is primarily due to their much higher critical electric field resulting from a wider bandgap (see Fig. 3). In addition, the use of an AlN back barrier would enable us to both increase the electron confinement in the transistor channel and enhance the thermal dissipation. It has already been demonstrated that for extremely high-temperature electronics, the properties of Al-rich transistors^169–171 show favorable comparisons to conventional wide-bandgap materials. Despite the difficulty to achieve very high-voltage operations due to the material quality and the ability to implement high Al content above 50%, some recent attempts showed the premise of voltage enhancement with AlGaN channels together with superior thermal stability.

Abid et al. used an AlN barrier on top of an Al₅₀Ga₅₀N channel grown on an AlN/sapphire template (Fig. 37). The heterostructure provides a high carrier concentration close to 1.9 × 10¹³ cm⁻² with a rather limited electron mobility of 145 cm²/V s. Low leakage current is obtained without the use of any field plates, confirming that tunneling mechanisms are not present in Al-rich transistors. In general, Al-rich transistors are less prone to gate leakage than AlGaN/GaN HEMTs. Despite the rather high defect density, a blocking voltage above of 4000 V with an OFF-state leakage current below 0.1 μA/mm is achieved for AlGaN-based channel HEMTs (Fig. 38). It can be noticed that low gate–drain distance of 5 μm yields a breakdown field of 3.5 MV/cm, which is well beyond that of SiC and GaN devices. Furthermore, these transistors show a very stable behavior as a function of temperature, with no threshold voltage variation and low OFF-state leakage increase up to 200 °C.

One of the major challenges limiting the research progress of Al-rich AlGaN transistors is the optimization of ohmic contacts. High resistance of the source and drain electrodes and the possible Schottky-like behavior lead to a reduced current density. Low resistance ohmic contacts are fundamental performance enablers in wide-bandgap HEMTs. Several approaches^174–177 are under development to mitigate this issue, namely, based on tuning the heterostructure and/or the subsequent annealing. For instance, regrown ohmic contacts using a SiO₂ mask can be applied. The reduction of the contact resistances has been verified at the transistor level. Output characteristics of transistors with regrown non-alloyed contacts showed a significant current density increase above 100 mA/mm as compared to identical devices with partially etched barrier and annealed contacts (see Fig. 39). This is clearly resulting from the drastic drop of the contact resistances. In spite of these obstacles, preliminary results show that contact resistivity will improve over time and that advanced approaches such as the etch and regrowth processes will ensure successful achievement at even higher Al-composition.

Despite the recent progress, the performance of AlGaN/GaN devices is still far from the theoretical limit predicted for the GaN materials.¹⁷⁹ A direct way to improve the device's performance is represented by increasing its carrier concentration, which directly leads to a reduced ON-resistance. Yet, achieving a large n_s leads to major challenges for the heterostructure and device design. First, a large n_s severely impacts the mobility (μ) due to the increased electron-to-electron scattering, limiting the reduction of the heterostructure R_sh. Second, a large n_s leads to a difficult control of the channel, which results in negative V_TH and degrades the device voltage blocking capability.

A promising approach to address these challenges is represented by the use of a multi-channel heterostructure, in which several barrier/channel layers are stacked to achieve multiple 2DEGs^180–183 [Fig. 40(a)]. This allows us to distribute a large n_s in several parallel channels, thus overcoming the trade-off between n_s and μ and considerably increasing the heterostructure conductivity. However, the multi-channel heterostructure can be combined with a tri-gate architecture, which allows us to gain excellent control over all of the embedded channels and manage the large OFF-state electric field (Fig. 40).