Silicon carbide (4H) based metal–oxide–semiconductor field-effect transistors provide capabilities in high power and high temperature inaccessible to silicon. However, the performance of thermally grown oxide-based devices remains limited by oxide/semiconductor interface defects. This research employs deposited dielectrics, Al2O3, rather than thermal oxidation. Investigation of various pre-deposition processes reveals different degrees of improvements in the electronic properties. An optimum structure employs the preparation of a nitrided surface via NO annealing, a process known to passivate surface defects, a hydrogen exposure, followed by Al2O3 deposition. Inversion layer field-effect mobilities as high as 52 cm2/V s are reported in the optimum structures. Capacitance–voltage measurements and field-effect mobility characteristics indicate a trapping limited conductivity in Al2O3/4H-SiC inversion channels similar to SiO2/4H-SiC. Leakage currents and interface breakdown are also reported for various Al2O3/4H-SiC MOS structures.
I. INTRODUCTION
The wide bandgap semiconductor 4H-SiC demonstrates unique material properties that enable metal–oxide–semiconductor field-effect transistor (MOSFET) operation for high power and fast switching applications,1,2 with levels of performance unreachable using silicon. Despite significant progress in the last 20 years, SiC device performance employing such thermal oxidation remains limited by interfacial defects. Similar to that of silicon, high temperature oxidation of SiC is employed to produce a MOS structure. During thermal oxidation, the top layers of SiC convert into silicon dioxide as carbon is released primarily as CO or CO2, creating a variety of defects.3 Interface trap densities (Dit) in such thermally grown 4H-SiC/SiO2 structures are at least an order of magnitude higher than those of Si/SiO2, posing a serious limitation on device performance. Post-oxidation annealing in nitrogen ambient4–6 has proven to yield acceptable performances and has been widely adopted in SiC technology. Other approaches involving boron7,8 or phosphorus9,10 have also been shown to reduce the interfacial trap densities inherent to the oxidation process at the cost of greater threshold voltage instability. Nevertheless, the structure, defect density, and device performance leave significant room for improvement.
Deposited dielectrics stand as an alternative approach to the formation of MOS interfaces, where the initial semiconductor surface bonds to the dielectric and becomes the final dielectric/semiconductor interface. Not only does this approach involve minimal amounts of structural modification but also opens the possibility of dielectric layer with critical properties that differ from SiO2. For example, the employment of high dielectric constant (high-k) insulators in 4H-SiC MOS devices could, in principle, allow for a lower electric field in the oxide during operation, potentially improving reliability.11 In addition, deposited dielectrics may offer higher channel mobilities, as a result of lower Dit compared to thermally grown SiO2 and/or reduced surface scattering. Among high-k dielectrics for SiC, Al2O3 (k = 7–10) is an appropriate candidate in this regard due to its good thermal stability, relatively large bandgap (∼ 9 eV), high critical electric field (∼10 MV/cm), and high conduction band offset (∼1.7 eV) with 4H-SiC.12–15 Promising works have reported higher channel mobilities for SiC MOSFETs using Al2O3 than nitrided SiO2.16–19 Nonetheless, further systematic studies on the impact of surface treatments prior to high-k dielectric deposition are required to fully unlock the potential of this approach to 4H-SiC MOSFETs.
In this work, different surface terminations of 4H-SiC involving O, H, and N prior to atomic layer deposition (ALD) of Al2O3 are compared. It is demonstrated that the surface treatments prior to ALD are key to improving the electrical quality of the interface and obtaining high channel mobility. Nitridation of the SiC surface followed by H2 annealing prior to ALD was found to be the best 4H-SiC surface treatment resulting in MOSFETs with peak field-effect mobility of ∼52 cm2 V–1 s−1 along with improvements in charge trapping and device stability. Results demonstrated here may overcome the channel mobility limitations in SiC MOS devices and provide new insights into the basic scattering and trapping mechanisms in this and other wide bandgap materials.
II. EXPERIMENTAL DETAILS
The effects of different 4H-SiC surface treatment processes prior to ALD were investigated by fabrication and electrical characterization of Al2O3/4H-SiC MOSFETs and MOS capacitors. For long channel lateral MOSFETs (150 μm length × 290 μm width), 10 × 5 mm2 size 4° off-axis (0001) Si-face 4H-SiC pieces with 4.4 × 1015 cm−3 epitaxial p-type doping were used. The source/drain regions were doped with high concentrations (∼1019 cm−3) of nitrogen implanted at 700 °C. Dopant activation annealing was performed at 1650 °C using a graphitic carbon cap. Parallel MOS capacitors were fabricated on 5 × 5 mm2 samples diced from 4° off-axis (0001) Si-face n-type 4H-SiC wafers with 10 μm epitaxial layers doped at ∼2 × 1016 cm−3 with nitrogen. At the outset, all samples were cleaned using organic and standard RCA (Radio Corporation of America) cleaning with buffered oxide etch (BOE) between each step. Then, different surface treatment processes were carried out on all the measured samples as described below.
Sacrificial oxidation in O2 (Process O): After the initial cleaning, a dry thermal oxide ∼15 nm thick was grown at 1150 °C for 2 h in pure O2 and completely etched with 6:1 BOE prior to ALD. This process results in a hydrophilic surface and about half a monolayer (∼1015 cm−2) of oxygen atoms, incorporated from the oxidation, remaining on the surface of SiC.20
Sacrificial oxidation in NO (Process N): Here, a sacrificial oxide layer was grown at 1175 °C for 2 h in pure NO, instead of O2 and subsequently completely etched with 6:1 BOE prior to ALD. The etching produces a sub-nm SiON film on the SiC surface that is composed of ∼5 × 1014 cm−2 of N atoms and ∼1015 cm−2 O atoms.21 N atoms are mainly bonded to three Si atoms, but some Si–O–N bonds cannot be excluded.
Sacrificial oxidation in O2 + H2 annealing (Process O + H): Process O was followed by annealing in 100% H2 at 1000 °C under atmospheric pressure for 15 min. Sample loading and unloading were carried out at room temperature. Such hydrogen annealing processes result in H-terminated 4H-SiC surfaces, which are clean, stoichiometric, unreconstructed, and chemically inert.14,22–25 In addition, H2 annealing removes hydrocarbon contaminations and results in the SiC surface, which is largely H-terminated and electronically passivated.
Sacrificial oxidation in NO + H2 annealing (Process N + H): Process N was followed by H2 annealing as described above.
After the different surface treatments, thermal ALD was carried out at 200 °C at a chamber pressure of 10−2 Torr, using trimethylaluminum [TMA, Al(CH3)3] as the precursor and H2O as the oxidizer to deposit ∼33 nm of Al2O3. Nitrogen was the carrier gas and pulse times of 0.06 s and 0.1 s were used for the precursor and the oxidizer, respectively. The growth rate of Al2O3 was 1.08 Å/cycle as measured by spectroscopic ellipsometry. X-ray photoemission spectroscopy analysis of test samples after the etching of deposited Al2O3 demonstrated that the underlying nitrogen containing layer was intact and not significantly affected by the ALD process.
Using photolithography and e-beam deposition a ∼100 nm thick Al gate and Ni source/drain (S/D) metals were patterned. For etching Al2O3 from the S/D areas, 1 min of 6:1 BOE was employed. No further annealing of the contacts was performed to avoid high temperature induced crystallization of Al2O3.26,27 For MOS capacitors, circular Al gates with ∼100 nm thickness and 300 μm diameter were formed by e-beam deposition, and a colloidal silver paste was used as back contact. For comparison, SiO2/4H-SiC MOSFETs were also fabricated in parallel with the same lateral MOSFET structure and process flow. These devices had ∼54 nm thermal SiO2 grown at 1150 °C in pure O2 and subsequently annealed in flowing NO at 1175 °C for 2 h.
III. RESULTS AND DISCUSSION
Simultaneous 100 kHz and quasi-static (high–low frequency) capacitance–voltage (CV) measurements were carried out on at least ten MOS capacitors per process. Samples that underwent sacrificial oxidation in O2 or NO had significantly reduced leakage currents compared to as-deposited Al2O3 films (i.e., deposited on surfaces that only received RCA cleaning and BOE dip). Therefore, as-deposited films are not discussed any further here. Typical room temperature CV measurements for all other samples are shown in Fig. 1. The effective charge densities (Neff) at the interfaces corresponding to the shift between experimental and ideal flatband voltages at 298 K were determined from 100 kHz CV as listed in Table I. In the case of a wide bandgap material like 4H-SiC, Neff includes charged interface traps under the flatband condition as well as any fixed charges in the oxide. While bulk negative fixed charge is widely reported in ALD Al2O3 films deposited on silicon, the measurements were not attempted here to isolate the effect of such fixed charges as in SiC, the interface trapped charge is a large negative charge that dominates the device characteristics. For samples that underwent H2 annealing (O + H, N + H), CV curves shift toward ideal characteristics, indicating the reduction of negative interface charges. Moreover, samples subjected to process N + H yielded a positive Neff in contrast to the other samples, as indicated in Table I. It is possible that aside from the removal of negative charge as a result of Dit reduction, incorporation of N results in the creation of positive charges at the interface in the form of a fixed charge or via N surface doping. Capacitors without hydrogen treatment (process O or N) prior to ALD barely held the accumulation voltage due to higher dielectric leakage currents. Therefore, Dit was not quantified on these samples. Based on the large dispersion of the high frequency and the quasistatic CV curves, a lower Dit for process N is qualitatively apparent compared to process O. More significantly, when H2 annealing was used (O + H, N + H), a large Dit reduction was obtained. The lowest Dit near the conduction band edge (∼6 × 1011 cm−2 eV−1 at the energy level of ∼0.2 eV, Dit profile not shown) was observed for process N + H. The effect of H2 annealing is consistent with previous studies on 6H-SiC and 4H-SiC capacitors,14,28 which suggests that clean Si–H terminated surfaces formed by H2 annealing results in uniform nucleation of the ALD film.
Process . | Neff (1011 cm−2) . | ΔNit (1011 cm−2) . |
---|---|---|
O | (−)54.9 ± 2.7 | … |
N | (−)52.3 ± 4.3 | … |
O + H | (−)3.9 ± 1.2 | (−)10.2 ± 0.25 |
N + H | (+)9.0 ± 1.2 | (−)1.14 ± 0.01 |
Process . | Neff (1011 cm−2) . | ΔNit (1011 cm−2) . |
---|---|---|
O | (−)54.9 ± 2.7 | … |
N | (−)52.3 ± 4.3 | … |
O + H | (−)3.9 ± 1.2 | (−)10.2 ± 0.25 |
N + H | (+)9.0 ± 1.2 | (−)1.14 ± 0.01 |
It is recognized that simultaneous high–low frequency CV underestimates Dit at shallow energies in nitrided SiO2 due to the presence of traps with extremely fast response times.29 Compared to the high–low CV analysis, the Gray–Brown (GB) method30 gives a more accurate estimate of the total amount of near-interface states near the conduction band edge. This method was used to estimate near-interface trap densities located energetically between ∼0.05 eV and ∼0.2 eV below the conduction band.31 In this analysis, the difference ΔNit, in the amount of occupied near-interface trapped charge at room temperature (298 K) and low temperature (77 K), is calculated by considering the temperature-dependent shifts of the flatband voltages. The results, summarized in Table I, follow the same trends as high–low CV, i.e., both H2 annealing and sacrificial oxidation in NO prior to deposition lead to a reduction of shallow Dit. The lowest ΔNit is found in process N + H and is significantly smaller than NO annealed SiO2 capacitors where typical values of ΔNit measured using this method are of the order of 5 × 1011 cm−2. This indeed suggests that hydrogen annealing of SiON surface layers is an attractive way to form electronic-defect free interfaces.
The field-effect mobilities (μFE) at 298 K were extracted using Al2O3/4H-SiC lateral MOSFETs, as a function of average oxide electric field (Eox) from transconductance measurements on the fabricated Al2O3/4H-SiC MOSFETs. The results, shown in Fig. 2, are the first measurements on FETs that demonstrate that Al2O3/4H-SiC channel mobilities are highly dependent on surface treatments. When H2 annealing is employed (either process O + H or N + H), higher μFE values are obtained compared to sacrificial oxidation only (process O or N). The effect of H2 annealing is more significant for N + H, which had the highest peak mobility of ∼52 cm2 V−1 s−1. This surpassed the control NO annealed thermal SiO2/4H-SiC device with the same p-substrate doping, labeled “ref” in the figure, which is on par with the process O + H. The MOSFET threshold voltages Vth, extracted by linear extrapolation of the μFE − VG characteristics, also showed a reduction consistent with the decrease of negative Neff as observed in the capacitors (Table I) for the different processes. We note that the lack of source–drain contact annealing results in high contact resistances. While this extrinsic factor does not affect the main conclusions of the paper, the μFE values reported here represent a lower limit of the actual values.
Next, the impact of trapping and Coulomb scattering from the shallow near-interface states was evaluated from electrical characteristics at 77 K. At this temperature, the reduction of the peak mobility μFE and the increase of the threshold voltage Vth was observed for all FETs, regardless of pre-deposition surface treatments as reported in Table II. This is a consequence of increased charge trapping near the band edges at 77 K and associated Coulomb scattering from shallow near-interface states.
Process . | Peak μFE (cm2 V−1 s−1) . | Vth (V) . | ΔNitFET (1012 cm−2) . | ||
---|---|---|---|---|---|
300 K . | 77 K . | 300 K . | 77 K . | ||
O | 1.5 | 0.2 | 4.4 ± 0.2 | 8.3 ± 0.3 | 5.6 ± 0.7 |
N | 12 | 6 | 2.6 ± 0.6 | 4.4 ± 0.2 | 2.2 ± 0.9 |
O + H | 26 | 10 | 3.0 ± 0.1 | 5.7 ± 1.2 | 3.9 ± 1.7 |
N + H | 52 | 20 | 0.5 ± 0.1 | 1.6 ± 0.5 | 1.3 ± 0.5 |
Process . | Peak μFE (cm2 V−1 s−1) . | Vth (V) . | ΔNitFET (1012 cm−2) . | ||
---|---|---|---|---|---|
300 K . | 77 K . | 300 K . | 77 K . | ||
O | 1.5 | 0.2 | 4.4 ± 0.2 | 8.3 ± 0.3 | 5.6 ± 0.7 |
N | 12 | 6 | 2.6 ± 0.6 | 4.4 ± 0.2 | 2.2 ± 0.9 |
O + H | 26 | 10 | 3.0 ± 0.1 | 5.7 ± 1.2 | 3.9 ± 1.7 |
N + H | 52 | 20 | 0.5 ± 0.1 | 1.6 ± 0.5 | 1.3 ± 0.5 |
The shallow interface state density for the FETs was also estimated by the GB method using the Vth difference between 77 K and 298 K as denoted by ΔNitFET in Table II. For the same process, the Vth shift of the MOSFETs is greater than the Vfb shift of capacitors (Table I). This is likely due to the different band-bending conditions in the two cases. Based on these results, it can be concluded that, similar to thermally grown SiO2/4H-SiC, channel conductivity in deposited Al2O3/4H-SiC is also limited by trapping in shallow states even though the composition and formation method of oxide are different. Specifically, this may indicate that Al2O3 devices are limited by a sub-nm Si sub-oxide, which contributes to these states. Further detailed chemical and electronic structure analysis are desirable to shed more light on these findings.
As mentioned earlier, when thermally grown SiO2 on SiC is etched with HF (BOE), approximately one monolayer of oxygen from SiO2 remains bonded to the SiC surface. In addition, adventitious surface carbon, Si–O sub-oxides and Si–O–C oxycarbides on the as-received wafers can also be removed from the SiC surface by such sacrificial oxidation in O2.32 However, the results obtained here suggest that the sole use of process O is not sufficient to attain low Dit in Al2O3/4H-SiC interfaces.
It is well known that nitridation of the SiO2/SiC interface results in an improved MOS interface. Suggested mechanisms include the passivation of C-dangling bonds33 and Si–Si sub-oxide bonds34 in the near-interfacial oxide, the passivation of Si-vacancies on the SiC side of the interface,35 and doping via the direct substitution of C with N in the first SiC bilayer.36 Nitrogen is commonly introduced by post-oxidation annealing in NO at moderate temperatures or in N2 at relatively higher temperatures. Both processes form an ultra-thin (<1 nm) interfacial layer containing N which, upon etching of the oxide, remains intact as a SiON surface layer on 4H-SiC,21,37 suitable for SiO2 deposition.38,39
The results here clearly evince the advantage of introducing N for the deposition of dielectrics. The stable SiON layer passivates the surface and enables the formation of a high-quality interface between SiC and deposited dielectric. Results obtained here suggest that surface nitridation of SiC yields improved interfaces not only for deposited SiO2 but also for Al2O3. Furthermore, the effectiveness of the H2 annealing is greater when applied to Si–O–N surfaces on 4H-SiC. It is apparent that the surface nitridation and subsequent hydrogen annealing (process N + H) works in an additive manner resulting in the best surface treatment.
Recent reports suggest that the growth of a low-temperature thin oxide (SiOx < 1 nm) prior to ALD of Al2O3 results in a very low Dit and excellent channel mobility of >150 cm2 V−1 s−1.17–19 It was highlighted that a ∼0.7 nm thick SiOx layer with an extremely small thickness tolerance (<0.1 nm) was necessary to achieve the best properties.40 Herein, this process was also attempted for different SiOx thicknesses obtained by employing various oxidation temperatures and time durations. The measurements indicate very high Dit (not shown) in a wide range of SiOx interlayer thicknesses (0.3–0.8 nm, as measured by XPS), highlighting the difficulty in reproducing those results, possibly due to very stringent processing condition requirements.
In addition to channel conductivity, bias induced instability of the gate dielectric is a major practical concern. Phenomena such as voltage hysteresis with changing sweep directions as well as permanent shifts after initial measurements have been reported for deposited dielectric/4H-SiC devices prepared under various conditions.12,15,28,41 In this work, the bias instability was studied using the MOS capacitors. Compared to the first voltage sweep, subsequent sweeps were considerably right shifted for processes O and N. This implies that some energetically deep interface traps or “slow states” in the oxide10 become filled with electrons during the first sweep and do not emit during subsequent measurements. When H2 anneal is incorporated (O + H or N + H) this effect improves significantly. In addition, back and forth CV sweeps were performed in a time scale of seconds on the MOS capacitors to evaluate the room temperature bias stability. Compared to the other processes, the N + H process yielded almost hysteresis free CV curves as shown in Fig. 3 for measurements with oxide electric field less than 1.5 MV/cm, under accumulation. This suggests that near-interface or border traps are responsible for the hysteresis in these devices in this electric field range, rather than defects in the bulk Al2O3 film. However, bulk traps may play an important role at higher oxide fields as indicated by the increased leakage current discussed next.
Gate dielectric leakage was found to be a serious challenge for devices formed with Al2O3. Leakage current in MOS capacitors as a function of the oxide electric field is shown in Fig. 4. The electric field Eox was estimated considering the different flatband voltages of the various samples. Processes involving hydrogen annealing (O + H and N + H) show improved oxide leakage and breakdown characteristics compared to sacrificial oxidation (processes O or N), as in Fig. 4. This suggests that the dominant leakage currents are likely due to trap-assisted tunneling mediated by near-interface traps. Despite the hydrogen induced improvement, gate leakage of all Al2O3 samples was significantly poorer than SiO2 (ref) counterparts, as shown in Fig. 4. This is a significant shortcoming that needs to be overcome before deposited dielectrics can compete with nitrided thermally grown SiO2 for practical 4H-SiC devices.
IV. CONCLUSIONS
In conclusion, a selective SiC surface treatment prior to dielectric film deposition is critical to obtain high channel conductivity in 4H-SiC MOSFETs with deposited dielectrics as the gate. This work is the first demonstration on MOSFETs that hydrogen annealing of 4H-SiC surfaces prior to atomic layer deposition of Al2O3 results in a large reduction of the near-interface state density and enhancement of channel mobility. Furthermore, it is shown that the hydrogen annealing is most effective when performed on sub-nm SiON layers formed on 4H-SiC surfaces by nitric oxide annealing. Using this surface treatment, an impressive peak field-effect electron mobility of ∼52 cm2 V−1 s−1 at room temperature was achieved, about 2× higher than the conventional nitrided SiO2/4H-SiC MOSFETs. In addition, device stability was improved with the reduction of interface states. Gate leakage in Al2O3/4H-SiC MOS devices was found to be high and, hence, remains a large challenge to overcome when using Al2O3 as an alternative for SiO2.
ACKNOWLEDGMENTS
The authors acknowledge support from the U.S. Army Research Laboratory (Grant No. ARMY-W911NF-18-2-0160). The authors thank the support of Ms. Tamara Isaacs-Smith of Auburn University for help with sample fabrication and discussions and Mr. Hengfei Gu of Rutgers University for help with XPS measurements. The authors would also like to thank Dr. Koushik Ramadoss of the Birck Nanotechnology Centre, Purdue University for useful discussions and help with sample preparation.
DATA AVAILABILITY
The data that support the findings of this study are available from the corresponding author upon reasonable request.