Opportunities and challenges of 2D materials in back-end-of-line interconnect scaling

Copper (Cu) has been the material of choice for interconnects in today's IC chips for more than 20 years. Before the integration scheme for Cu interconnects was available, aluminum (Al) was used as metal interconnects. However, with increasing demands of lower resistivity and better electromigration endurance, Al was eventually replaced with Cu in the late 1990s, after many integration challenges had been solved. Overviews of the technology development can be found in Refs. 1 and 2. Although Cu offers the advantage of improving interconnect performance, its high diffusivity results in diffusion of Cu atoms/ions into the surrounding dielectric that isolates individual Cu interconnect wires, causing short-circuiting and chip failure.^3–6 To prevent this, TaN has been adopted as the “diffusion barrier” to block Cu diffusion.^7,8 While possessing a decent diffusion barrier property, the adhesion between TaN and Cu is not ideal. Therefore, Ta has been introduced as the “liner” between Cu and TaN to improve the adhesion.^7,8 The schematic of basic interconnect structures is shown in Fig. 1, with two levels of Cu interconnects being connected through a “via.” Although the TaN/Ta/Cu stack gives an optimal diffusion barrier and liner properties, both TaN and Ta are much more resistive than Cu. Since the TaN/Ta stack occupies a certain percentage of the interconnect volume, the effective portion for high current conduction is less than the actual dimension of the interconnect. As a result, thinning down of the TaN/Ta layer must be carried out every few generations to reach the targeted current driving capability. However, with the advent of 5-nm node and beyond, interconnect width can be as narrow as 20 nm or below. Meanwhile, the thickness of the TaN/Ta stack must be at least 3–4 nm⁹ in order to provide a reasonable barrier and liner functions. Taking an interconnect with 20 nm in width and 40 nm in trench depth as an example, at least 35% of the entire interconnect cross-sectional area is occupied by a 3-nm thick TaN/Ta layer. Further scaling will lead to an even less percentage of Cu occupancy, largely suppressing the current conduction, as illustrated in Fig. 2(a). Even though scaling below 3 nm has been demonstrated by introducing atomic-layer deposition (ALD) TaN,¹⁰ achieving a sub-nm barrier/liner will be necessary for advanced technology nodes, which is extremely challenging for these conventional materials due to their three-dimensional (3D) nature. On the other hand, two-dimensional (2D) materials, including graphene, hexagonal-boron-nitride (h-BN), and transition-metal-dichalcogenides (TMDs), can be atomically thin, e.g., ∼0.3 nm for a single layer graphene.¹¹ Consequently, research has been carried out to evaluate 2D materials for their potential as a diffusion barrier replacement in the past few years, with the main idea illustrated in Fig. 2(b). Preliminary results have suggested that 2D materials have promising diffusion barrier properties,^12–16 which encourages further studies especially on the perspective of integrating these novel materials to the state-of-the-art technologies. For example, early studies of graphene grown at 1000 °C^12–15 provided the initial evidence that a single layer of carbon atoms is sufficient to block ion diffusion. However, the very high growth temperature is not compatible with the back-end-of-line (BEOL) technologies.¹⁷ Besides, none of the early works discussed the liner properties of 2D materials, which could be an inherent weakness of these materials due to their van der Waals force interaction. Figure 1 summarizes the list of qualifying criteria for both barrier and liner as well as process-related issues to the surroundings materials/structures, all of which must be investigated before making decisions to integrate any of these new 2D materials to the technology. The framework of this article will be based on the reviews and discussions of each criterion. Some of them have already been successfully demonstrated in 2D materials, while the others still remain challenging. Possible solutions to address these remaining challenges and future routes in realizing a 2D-material-based barrier/liner will also be extensively discussed throughout this article to inspire future studies and development.

In this section, we will provide an overview on both theoretical and experimental studies of diffusion barrier properties of 2D materials. First-principles density functional theory (DFT) calculations have been employed to investigate barrier energies of various 2D materials for blocking Cu diffusion and provide insight into the electronic structures of the interface between Cu and various 2D materials.¹⁸ Details of the calculations are provided in Sec. VIII. Figures 3(a) and 3(b) show the lowest potential energy surfaces for Cu diffusing across various single-layer, perfect crystals of MX₂ TMDs with M = Mo, W, and Ta and X = S, Se, and Te. We show results for the two most stable phases 2H (space group P-6m2) and 1 T (space group P-3 m1). These calculations are performed on defect-free, perfect crystals that are hardly produced in real growth effort. In fact, most 2D materials in the literature and those available in the market show rather high defects and impurity densities as well as limited grain sizes. Grain boundaries have been established as the dominant diffusion paths in the case of TaN/Ta,^19–21 and they can certainly play important roles in the 2D materials of interest.²² Nevertheless, exploring performance in ideal materials by calculations is essential for comparing intrinsic properties among different materials and identifying diffusion mechanisms. Our DFT results show that sulfides impose the highest barriers to diffusion with a reduction as we move to selenides and tellurides [Fig. 3(a)]. In fact, quite surprisingly, Cu prefers interstitial sites over surface sites for 2H tellurides.²³ Due to the great interest in TaS₂ for reasons to be addressed below, the material will be discussed in further detail to fully evaluate its potential. Figures 3(a) and 3(b) show that 2H-TaS₂ is preferable over 1T-TaS₂ because of its higher energy barrier. In addition, 2H-TaS₂ is easier to be produced by low-temperature syntheses.²⁴ Zhao et al.²² have calculated a very high barrier energy of 30.6 eV in graphene [compared in the left panel of Fig. 3(c)], which promises a good diffusion barrier candidate that we will discuss in the paper. It is important to compare these new 2D materials with the conventional TaN barrier that has been thoroughly studied both theoretically and experimentally. Although the comparison of calculated energy barriers for 2D materials and experimentally extracted values for TaN is rather crude, it is helpful to gain some initial insights in order to quickly identify promising candidates. An experimental barrier energy extraction of 3.27 eV in single crystalline TaN by Wang et al.¹⁹ is included in the same figure. Based on these comparisons, we conclude that graphene, h-BN, and some sulfides can be as good as or even better than single crystalline TaN in terms of barrier energy and can be considered for Cu diffusion barrier applications. As mentioned earlier, materials used in practice are normally polycrystalline with grain boundaries. The right panel of Fig. 3(c) displays an experimental extraction of a reduced barrier energy range from 0.14 to 1.4 eV in TaN due to diffusion through grain boundaries.^20,25,26 The barrier energy for 1T-TaS₂ is calculated to be 1.5 eV,²⁷ higher than that of TaN. It would be interesting to have the same to be calculated for 2H-TaS₂ as well. Surprisingly, the value for graphene obtained from the same work by Zhao et al.²² reduced significantly.

To experimentally test diffusion barrier properties, various approaches have been utilized, including thermal^12–14 and electrical^{15,16,28–31} stress. This article will mainly focus on electrical tests, including three types, namely, capacitance–voltage (CV),^16,28 triangular voltage sweep (TVS),^16,29 and time-dependent dielectric breakdown (TDDB).^15,30–37 To study the intrinsic material properties, especially for novel materials, simple planar structures [Fig. 4(a)] are preferred since they exclude the extrinsic effects from an unoptimized process,^33,35,36 such as post-CMP (chemical–mechanical polishing, a process commonly used in BEOL) damage and contamination.³⁸ In contrast, inter-digitated damascene structures are more commonly adopted in the state-of-the-art technology to test the performance of the conventional TaN/Ta stack.³⁹ In general, for all of the electrical tests using either test structure, a constant electric field is applied across a capacitor like structure (Cu electrode/barrier/dielectric/electrode) for a certain duration to drive Cu ions into the dielectric. Note that the mass transport of Cu ions driven by the electric field is actually “Cu drift.” Nevertheless, we still denote it as “Cu diffusion” because of the conventional terminology used in the field. In CV and TVS measurements, the electric fields applied are generally small to just drive a small amount of Cu ions into the dielectric, while the electric fields applied in TDDB measurements are large enough to cause device breakdown. In the CV method, after the constant field stressing, the flatband voltage will shift with the presence of fixed charges contributed by Cu ions in the dielectric. If a barrier is superior in blocking Cu diffusion, the flatband shift will be less or even negligible, as illustrated in Fig. 4(b). In the TVS method, after the stressing, a voltage sweeping from positive to negative is performed. A “bump” with increased current flow in the negative voltage regime can be observed, as depicted in Fig. 4(c), which is attributed to the presence of Cu ions. A better diffusion barrier will result in a smaller “bump.” Details of the mechanism are described in early literature.²⁹ The examples of using CV and TVS methods to test barrier properties of graphene can be found in the work of Mehta et al.¹⁶ 

TDDB measurement is the most widely used method in the industry since statistical information with solid theoretical backup, namely, the percolation theory,^40–42 can be obtained. Unlike the CV and TVS methods, where the “monitoring” of device characteristics is conducted after the stressing, the stressing and monitoring processes are performed simultaneously in TDDB measurements. As depicted in Fig. 4(d), the current is being monitored while the stressing is being applied. After a certain amount of time, a current surge will occur, indicating the device breakdown. The breakdown is attributed to the Cu ions present in the dielectric, which facilitate trap-assisted conduction^34,37 or even short, the electrodes on both sides by forming copper silicide in some extreme cases,^12–14,30 as depicted in Fig. 4(e). If a barrier is superior, the time-to-breakdown (t_BD) of devices using that barrier will be longer. The values of t_BD of multiple devices can be obtained and plotted in a statistical fashion shown in Fig. 4(f). When the y axis is presented as the cumulative probability (F), smaller/larger values of t_BD are assigned to have smaller/larger cumulative probabilities. In this way, a clear comparison between different barriers can be obtained. Sometimes, the y axis is presented in the Weibull scale [W = ln(−ln(1 − F))]. A straight line in the Weibull plot normally indicates that the percolation theory can be applied, as is the case for a gate dielectric breakdown.^40,41 Even though some works claim that the percolation theory can also be applied to a Cu-induced breakdown,⁴² we suggest using cumulative probability for the comparison to avoid mis-interpreting the underlying mechanisms of Cu diffusion through these novel materials.

An example of comparing diffusion properties of TaS₂, Ta, and TaN is presented in Fig. 5. The time to breakdown tends indicate that 1.5-nm TaS₂ is as good as 3-nm Ta [Fig. 5(a)] and equivalent to 2-nm TaN¹⁵ [Fig. 5(b)]. Together with the superior liner properties, which will be discussed in Sec. III, it is possible to replace the 5-nm TaN/Ta bilayer with 3-nm TaS₂, based on experimentally already achieved TaS₂ performance. This barrier/liner scaling down can significantly increase the percentage of Cu occupancy and decrease the line resistance of ultra-scaled interconnects, as shown in Figs. 5(c) and 5(d). Further development in growth and improvement in material quality would make it possible to use high quality, single-layer (∼0.7 nm) TaS₂ as the barrier/liner layer. Note that the actual Ta to S ratio of this plasma-enhanced chemical vapor deposition (PECVD)-grown TaS_x is 1:2.5.²⁷ However, for simplicity, it is referred as TaS₂ throughout this article. TDDB results of other 2D materials, including graphene, h-BN, and MoS₂, can also be founded in other works.^15,30 Evaluations of diffusion barrier properties of 2D materials from experimental works in the literature are summarized in Table I.

In addition to the ability to block Cu diffusion, blocking oxygen diffusion is also an important function of the barrier layer. Since low-k dielectrics used in current BEOL technologies are porous, oxygen can easily diffuse through low-k and oxidize Cu, hence degrading its performance.³ Testing this property is more straightforward, and both theoretical^43,44 and experimental works^45,46 have shown that 2D materials are adept at preventing O₂ diffusion.

The liner properties include mainly three aspects, namely, wettability, adhesion, and impact on Cu resistivity. Wettability is important for the deposition of a thin Cu seeding layer before electroplating the actual Cu interconnects.³ The testing method is to deposit a thin layer of Cu on different surfaces to evaluate the wetting situation.²⁷ As shown in Fig. 6(a), when ∼10 nm Cu is deposited directly on a dielectric, a significant number of cracks are observed, indicating poor wettability. On the other hand, when a TaS₂ layer is inserted between Cu and the dielectric [Fig. 6(b)], the morphology is significantly improved. It is actually as good as a standard Ta liner shown in Fig. 6(c), suggesting that TaS₂ serves well as a liner in terms of wettability.

The adhesion property is the most critical factor to determine whether a 2D material can be adopted in the BEOL technology. The weak van der Waals layer-to-layer interaction in 2D materials make them unique in the way that individual layers can be exfoliated from the crystal even by a scotch tape, which was discovered and applied to the first graphene work. However, this weak interaction is not desired between 2D materials and other materials that they need to interface with, such as Cu. Much stronger adhesion is needed at interfaces of different materials to ensure the BEOL reliability. In the interconnect damascene process, a very harsh chemical–mechanical polishing (CMP) step is performed to remove excess Cu after the electro-plating deposition;³ therefore, the liner needs to provide strong-enough adhesion to avoid the desired part of Cu being removed.³ In addition, it has been demonstrated that the inferior adhesion can lead to worse electromigration lifetime.⁴⁷ To give a quick assessment of adhesion properties of 2D materials, a simple tape test can be used.^27,48,49 The procedure is described in Fig. 7. The 2D-material-under-test was first deposited to cover half of a substrate. A Cu layer (∼80 nm in this example) was then deposited on the entire sample. A 3M Scotch^® tape was attached on the sample and then detached. A qualified liner needs to prevent Cu from being peeled off by the tape during the detaching process. As summarized in Table I, among the 2D materials that are tested, only TaS₂ passes the tape test and proceeds to be compared with Ta (standard liner) using an industrial-standard method,⁵⁰ i.e., a 4-point bending test.^51–53 The measurement setup is roughly illustrated in Fig. 8(a), and details can be found in other works.^51,52 Load-displacement curves obtained from measurements are shown in Fig. 8(b). At the early stage, the load increases linearly with the increasing displacement due to bending of the sample. Beyond a certain point, the load will drop abruptly, indicating the occurrence of delamination. By using the values of load and displacement at the delamination point, the adhesion energy or the strain energy release rate (G) can be obtained. Details of the theory and more examples can be found in the literature.^52,53 It is calculated that the G values of Ta and TaS₂ are similar, as shown in Fig. 8(c), confirming the strong adhesion of TaS₂ with the Cu and SiO₂ substrate.

In addition to the wetting and adhesion properties, researchers have found that 2D materials can reduce Cu resistivity in ultra-scaled dimensions and attributed that to reduced inelastic surface/interface scattering at 2D/Cu interfaces.^54,55 It is well known that Cu resistivity increases as its dimensions are reduced, mainly due to increased grain boundary scattering and inelastic surface/interface scattering.^56,57 Especially in an ultra-scaled interconnect, much more pronounced inelastic surface/interface scattering is the main factor responsible for the deteriorated Cu resistivity. It has been discovered that the perturbing localized interfacial states at the Ta/Cu interface cause more inelastic scattering of electrons in Cu.^58,59 On the other hand, experimental observation of improved Cu resistivity when its surface is passivated by graphene⁵⁴ leads to follow-up experimental and theoretical studies on other 2D materials,^55,60 which all conclude that the weak interaction between Cu and 2D materials can result in reduced interface scattering. In Ref. 55, the experimental test structure consists of a Cu thin film deposited on a 2D liner-under-test, as illustrated in Fig. 9(a). The reason of using thin Cu (∼15 nm) is to enhance the scattering contribution from the interface. The Cu thin film is patterned into the so-called Kelvin structure to obtain an accurate resistance measurement. After carefully measuring the dimensions, including length, width, and thickness of the patterned Cu thin film, Cu resistivity can be calculated. The results are shown in Fig. 9(b), where each point represents the value obtained from a single test structure. As observed, when MoS₂ and WSe₂ are used as the liner, Cu resistivity is obviously reduced, suggesting 2D liners are able to reduce inelastic interface scattering. Note that even though the values from Ta/Cu are not shown here, it is known that Cu resistivity is even higher in the case of Cu on Ta, as compared to Cu on oxides.⁵⁹ More details can be found in the work of Shen et al.⁵⁵ Other 2D materials including TaS₂²⁷ have also shown a similar benefit. Comparison of diffusion barrier and liner properties of various 2D materials is summarized in Table I. It is important to note that all evaluations and comparisons here are based on the materials synthesized in respective references. Further research and effort on materials to improve the quality of materials can certainly change the outcome.

In the state-of-the-art BEOL processes, barrier and liner are deposited on low-k dielectrics before the deposition of Cu. The differences between conventional TaN/Ta deposition and current 2D material synthesis will require major design and process modifications. Physical vapor deposition (PVD), more specifically, sputtering has been used to deposit TaN and Ta.^64,65 On the other hand, large area 2D materials are typically synthesized by chemical vapor deposition (CVD).⁶⁶ The key differences between PVD and CVD are the substrate preference and process temperature. First, successful film deposition by PVD is less dependent on the targeted substrate. Although different substrates can result in different crystallinity, surface morphology, and so on, formation of a certain type of film is guaranteed.⁷ However, in the case of CVD for 2D materials, choice of substrates is crucial since the film might not be grown at all on certain substrates. For example, it is well known that graphene prefers to grow on Cu rather than on dielectrics.⁶⁷ Using the same growth conditions, replacing Cu by dielectric as the substrate may result in a complete absence of film formation.⁶⁷ Therefore, it is important to identify synthesis approaches that can successfully deposit uniform 2D materials directly on dielectric substrates. In early works where graphene was investigated as a diffusion barrier,^12–15 graphene was first grown on Cu foils at 1000 °C, followed by a wet process to be transferred onto dielectrics for diffusion barrier property testing, as depicted in the top-left part of Fig. 10. Although this method is suitable for preliminary evaluations of unexplored materials, transferring these atomically thin films at the wafer scale appears to be a major challenge for BEOL applications. Therefore, efforts have been made to directly grow graphene on dielectric substrates to avoid the transfer process.^12–15 On the other hand, transition-metal dichalcogenides (TMDs) favor to be grown on dielectrics (the bottom-left part of Fig. 10), as shown by many early TMD works.⁶⁶ Nevertheless, the growth temperature for 2D material synthesis remains to be a concern, as discussed below.

In BEOL, the process temperature must be close or below 400 °C. Otherwise, both the low-k dielectric and previously deposited Cu at lower levels can be damaged.¹⁷ However, the temperature for conventional CVD growth of 2D materials is normally above 700 °C due to the requirement of thermal energy to dissociate the precursors. These types of CVD are also known as the “thermal CVD.” To reduce the growth temperature, plasma-enhanced CVD (PECVD) has been adopted since plasma can assist in dissociating the bonds of precursors, hence reduce the demand of high thermal energy. Graphene directly grown on dielectrics at 550 °C has been demonstrated by Mehta et al. using PECVD,¹⁶ as illustrated in the top-middle part of Fig. 10. However, to further bring down the temperature to be BEOL-compatible, a sacrificial layer (SL) needs to be employed for graphene growth on dielectrics.^61,68,69 In this approach, a metal sacrificial layer with high solubility of carbon (normally Ni or Co) is first deposited on dielectric. Since graphene prefers to grow on metals, a layer is formed on the top of the metal surface. In the meantime, carbon atoms can diffuse into the metal due to the high solubility and arrive at the interface between the sacrificial metal and the dielectric. Finally, carbon atoms accumulated at the interface form graphene layers underneath the metal. The SL and the top graphene layer are then removed, leaving the bottom graphene film directly on the dielectric. The procedure is briefly illustrated in the top-right part of Fig. 10. Detailed mechanisms are nicely described in the work of Kwak et al.⁶⁸ In the case of TMDs, successful growth at BEOL-compatible temperatures has been demonstrated using PECVD.^27,70,71 Metal layers can be first deposited on dielectrics, followed by a conversion step by a PECVD process. For example, Mo and Ta thin films can be sulfurized by H₂S gas through a PECVD process and get converted into MoS₂^70,71 and TaS₂,²⁷ respectively, at BEOL-compatible temperatures. In addition to PECVD, metal-organic CVD (MOCVD) has also been adopted for a direct deposition of MoS₂ on dielectrics at 400–450 °C.^31,62 Methods for BEOL-compatible TMD growth are depicted in the bottom-right part of Fig. 10.

The importance of lower growth temperatures is highlighted in Fig. 11. The high temperature damage to dielectric can be observed by comparing the time-to-breakdown between two processes (green and red boxes). The green box represents the statistics of t_BD from devices with direct-deposited MoS₂ barriers at 850 °C.^30,72 When the same MoS₂ is transferred to a substrate that has not gone through the high temperature process, t_BD of devices increases obviously, as shown in the red box. Since the qualities of two MoS₂ films should be nearly identical, the enhanced t_BD indicates a better qualify of the latter dielectric, as a more defective dielectric will facilitate more Cu diffusion.^34,37

Although low-temperature synthesis can be realized by the above-mentioned approaches, growth at lower temperatures normally results in films with smaller grain sizes. Since grain boundaries are the main diffusion paths for Cu,²² barriers with smaller grain sizes will have inferior performance. For instance, with high-temperature CVD growth, the grain size is normally on the order of a few to tens of micrometers,^30,72 whereas grains sizes of tens of nanometers are often found in low-temperature-grown 2D materials.³¹ The compromised diffusion barrier property of low-temperature MoS₂ barrier can be noticed by comparing the red and blue boxes in Fig. 11. Since the dielectric is hardly damaged,³¹ the degraded performance is attributed to the smaller grain sizes or more grain boundaries, which facilitate more Cu diffusion. Nevertheless, the grain sizes of the 2D materials are still comparable to sputtered TaN and Ta whose grain sizes are also in the range to tens of nanometers.²⁰ In fact, the columnar structure in TaN/Ta^20,64,73 can possibly make grain boundary diffusion more severe than in 2D materials. In addition, although the grain size is limited by current CVD techniques, achieving single-layer 2D materials with a large grain size is fundamentally possible due to the material nature. This could be one of the future research focuses in this area. On the other hand, TaN/Ta would already be discontinued at the same atomic thickness due to their 3D natures.

Other growth methods, such as sputtering^74,75 and atomic-layer deposition (ALD),⁷⁶ have also been demonstrated to carry out 2D material synthesis at even lower temperatures (⁠$≪400°C$⁠). However, without annealing (>400 °C) processes, as-deposited films are nano-crystalline or even amorphous, which leads to an inferior diffusion barrier property, as discussed and shown in Fig. 11. More research needs to be done to grow high-quality 2D materials using these methods. In summary, growth recipes need to be further investigated to improve film quality as well as to reduce dielectric damage. In addition to reducing the thermal damage, it is also important to reduce the damage from other sources, such as plasma power, to minimize potential damages to dielectrics.

Finally, it is also important to investigate whether the synthesis methods can ensure conformal deposition in damascene structures with high aspect ratios. Therefore, efforts must also be made to deposit 2D materials in trench structures.^77,78 In principle, two methodologies have been utilized. In the MoS₂ work of Martella et al.,⁷⁸ ALD MoO_x layers were first deposited, followed by sulfurization; whereas Jin et al. directly deposited MoS₂ and WS₂ using MOCVD.⁷⁷ Here, we also demonstrate direct deposition of MoS₂ in trench structures using thermal CVD at a high temperature (just to explore the conformability), as shown in Fig. 12(a). Thick films are deposited for preliminary investigations with the focus on conformability at some critical positions in the trench. It is found that trench edges and sidewalls are much harder to cover compared to the bottom surface. Note that none of the works mentioned above is BEOL-compatible up to date. Therefore, lower growth temperatures, more conformal deposition, and thinner films are the goals to achieve for trench deposition. Since conformal deposition of Ta (and TaN) has already been developed by the industry, we believe that converting pre-deposited TaN/Ta into uniform TaS₂ in damascene through the PECVD sulfurization process²⁷ discussed above is potentially feasible, as illustrated in Fig. 12(b).

“Via” is a connection between interconnects from different levels, as sketched in Fig. 1. Via resistance has been one of the major bottlenecks for overall interconnect performance at advanced technology nodes. Since the selective deposition of barrier/liner only on the sidewalls rather than on the vias should be avoided due to electromigration concerns,^79,80 when current flows from an upper level Cu wire, through a via, to a lower-level wire, it has to go across the highly resistive Ta/TaN layer at the bottom of the via. As mentioned above, since the thickness of the barrier/liner stack cannot be scaled proportionally, the via resistance becomes even larger with the via width (area) scaling. Although the ultra-thin 2D barrier/liner has the advantage of enlarging the Cu cross-sectional area, the vertical current conduction across these novel materials has seldomly been discussed. Among the few 2D materials that have been investigated for BEOL applications, TaS₂ is chosen for the study here since it has been evaluated more thoroughly from various aspects and benchmarked with conventional materials, as described in Secs. II–IV. Early works have shown that in-plain room temperature resistivities of 1T-TaS₂ and 2H-TaS₂ are ∼300 μΩ cm and 150 μΩ cm, respectively,^81–83 both of which are lower than that of TaN (∼700 μΩ-cm).⁸⁴ However, unlike TaN or Ta, the conduction in 2D materials is anisotropic, meaning that the out-of-plane (vertical) resistivity of TaS₂ could be very different from their in-plane counterparts. In fact, the out-of-plane resistivity of 2H-TaS₂ is as high as ∼5000 μΩ-cm,⁸² while it reaches 7 × 10⁵ μΩ cm in 1T-TaS₂.⁸³ Despite the high vertical resistivity of TaS₂, the overall resistance of TaS₂/Cu via could still outperform the conventional structure of TaN/Ta/Cu since (i) the required thickness of TaS₂ can be thinner and (ii) the enlarged Cu volume by 2D barrier/liner becomes even more obvious in ultra-scaled dimensions, both of which will be elaborated in the following discussions.

To understand intrinsic properties and avoid deteriorated characteristics due to imperfect material synthesis at the current stage, we exfoliated TaS₂ films from commercially purchased crystals (2D Semiconductors) and performed electrical measurements on 2H-TaS₂ because of its lower out-of-plain resistivity⁸² and potentially lower growth temperatures as opposed to 1T-TaS₂.²⁴ Precautions were taken for the test structure design and fabrication since the vertical conduction can be affected by many subtle imperfections, such as surface oxidation of TaS₂ and electrodes or any process contamination. The device structure is shown in Fig. 13(a). A SiO₂ (60 nm) layer was deposited by an e-beam evaporator to isolate the top and bottom electrodes. A window was then opened in the SiO₂ layer to guide the current to flow through TaS₂ vertically, followed by the top electrode formation. The choice of the electrodes is critical since both oxidation and poor adhesion could severely affect the vertical conduction. Therefore, the bottom electrode is chosen to be Ti/Au (5 nm/25 nm) to avoid oxidation before exfoliating TaS₂ on it. The top electrode is selected to be Ti/Ni (35 nm/70 nm) to have a better adhesion. Note that since 2H-TaS₂ is metallic in the vertical direction at room temperature,^24,85 the choice of metal work function should be less critical on contact resistances. A set of control devices using the identical design but without TaS₂ flakes between the top and bottom electrodes were also fabricated to subtract parasitic resistances. The results from multiple devices in Fig. 13(b) show that the vertical resistivity can be as low as ∼2000 μΩ cm.

To estimate the overall via resistance with technology scaling, a semi-empirical model proposed by Ciofi et al.⁸⁶ was adopted to calculate Cu resistivity by considering its size effect. Contribution from Ta was first neglected for simplicity, which is a conservative assumption. As demonstrated in Fig. 13(d), even with a ∼3X higher resistivity of 2H-TaS₂, the contribution from TaS₂ is similar to that from TaN since TaS₂ can be thinner. The resistance contribution from Cu tremendously increases in extremely scaled dimensions because TaN occupies a huge portion. On the contrary, when TaS₂ is used, contribution from Cu is much lower due to the much larger Cu percentage. In summary, even with the higher vertical resistivity of TaS₂, replacing TaN/Ta with TaS₂ is still beneficial for via resistance, which further helps reduce the bottleneck of interconnect scaling.

So far, this article has discussed various aspects of using 2D materials as the diffusion barrier and liner for Cu interconnects. Moreover, 2D materials could offer other functions to different parts of Cu interconnects or even to other types interconnects, which will be briefly introduced in this section.

One of the limiting factors of the lifetime of a metal wire is its resistance to electromigration (EM). EM occurs in metal wires due to the momentum transfer between electrons and metal atoms.⁸⁷ Voids in metal wires and vias will eventually appear due to the current induced atom movement, leading to the malfunction of interconnects. According to the International Technology Roadmap for Semiconductors (http://www.itrs2.net/), reduced interconnect cross sections and boosted maximum chip operation frequency unavoidably increase the maximum current density (J_max) required for targeted performance to be close to or even exceed the current density (J_EM) for EM to occur. As a result, EM must be mitigated in order to maintain continuous performance improvement. As depicted in Fig. 1, a Cu wire is surrounded by a barrier/liner on the sidewalls and bottom of the trench. At the top surface, Cu is polished by the CMP process, as briefly mentioned in Sec. III. Studies have shown that this post-CMP surface becomes one of the dominant paths for EM to occur.⁴⁷ To alleviate the CMP damage and enhance EM lifetime, various materials, such as Co,⁸⁸ CoWP,^47,79 and the related,⁷⁹ have been capped on the top surface of Cu along the history of interconnect development. These layers are also referred to as the “capping layers.”

In addition to conventional capping layer materials, graphene has recently been shown to prolong EM lifetime.^89,90 It has been claimed that the Cu EM lifetime can be extended by ∼10× due to the improved interface between graphene and Cu.^89,90 Conventional capping layers are selectively deposited on the Cu surface. Therefore, graphene can fulfill the requirement quite well since it favors the deposition on Cu than on dielectrics, as discussed in Sec. IV. Although the thickness requirement may not be as critical as a barrier/liner in current and near-future technologies, it is still interesting to have more thorough understanding of impact of 2D materials on EM lifetime. In authors’ opinion, a few more tasks must be conducted before concluding graphene is a better EM lifetime enhancer than standard capping materials. First, in order to have a real EM failure instead of a failure from Joule heating, measurements had been performed at lower current densities, ranging from 0.6 MA/cm² to 3.6 MA/cm².^79,80,88,91 However, due to the limitation of the setups in research facilities, in the graphene works,^89,90 the current density is much higher (>20 MA/cm²) to accelerate the failure. In this case, it is difficult to determine whether the failure is mainly due to EM. On the contrary, days,^80,88,91 or even months,⁷⁹ of measurement for a single device can be performed in an industrial setup. To solve this issue, the low-frequency-noise method well developed by Beyne et al.⁹² can be adopted. Second, the depositions of graphene and standard capping layers (e.g., CoWP⁸⁹) could lead to completely different grain structures of the capped Cu due to the distinct deposition methods. To perform a fair comparison, the contribution from Cu needs to be eliminated, meaning that the Cu grain structure must be identical in both cases. If graphene eventually gets adopted by BEOL technologies as the capping layer, prior to the formation of the next-level vias, graphene needs to be selectively removed in the via areas by some unique etching techniques,^93,94 which does not involve O₂ plasma based conventional graphene etching recipes⁹⁵ to avoid Cu oxidation. Finally, the graphene demonstrated so far for EM measurements comes with a relatively thick amorphous carbon layer,^89,90 which certainly compromise the advantages of 2D materials. Thus, it is necessary to eliminate the carbon layer.

Cobalt (Co) and ruthenium (Ru) have been extensively investigated in the past few years as the replacement of Cu. Their promises lie in the possibility to be barrier-free, lower resistivity compared to Cu in extremely scaled dimensions due to a shorter mean free path^96–99 and superior EM lifetime.^92,100,101 Even without the need of a diffusion barrier, an adhesion layer, in analogy to the liner for Cu, is generally required.⁹⁶ Therefore, the surface/interface scattering between ultra-scaled Co or Ru and their adhesion layers could play a critical role in their resistivities,¹⁰² as discussed in Sec. III. In addition, despite the early presumption that a barrier would not be necessary, Co and Ru have been found to diffuse into dielectrics under certain conditions.^103,104 TaS₂ grown at 400 °C was tested to explore whether the benefits for Cu interconnects in terms of blocking diffusion and scattering reduction also apply to Co interconnects.⁵⁰ Figure 14(a) shows the test results of Co diffusion using the capacitor structure in Fig. 4(a). It can be observed that with TaS₂ in-between Co and SiO₂, t_BD of devices increases in general, indicating the suppression of Co diffusion. In addition, when thin Co (∼12 nm) is patterned in the Kelvin structure shown in Fig. 9(a) and is deposited on TaS₂, it is found in Fig. 14(b) that Co resistvity is reduced, indicating a more elastic surface/interface scattering facilitated by TaS₂. In short, TaS₂ provides desired barrier and liner properties for Co interconnects, which might be useful for future interconnect technologies.

With the emergence of 5G communication and increased interest in millimeter-wave (mm-wave) applications, much effort has been made to increase the maximum frequency of RF circuits and systems. This not only requires active devices with higher cut-off frequencies, but also requires passive components, such as transmission lines, to operate at higher frequencies. At higher frequencies, the RF power loss along typical metal transmission lines can increase drastically, limiting operational bandwidth of the entire circuit. Conventionally, RF transmission lines are designed on the top layers of interconnects since thicker and wider transmission lines exhibit lower power losses.¹⁰⁵ Recently, with the increased interest in the monolithic integration of mm-wave capabilities with CMOS technology, high bandwidth transmission lines with dimensions in the range of tens of nanometers are required to be comparable to the dimensions of low level interconnects in standard CMOS structures.^106,107 This highlights the need for RF “nano-transmission” lines in the recent years,^108–111 explored here using 2D layered materials.

The reason of integrating 2D layered materials with RF transmission lines lies in the fact that 2D materials can reduce inelastic surface/interface scattering of Cu wires and hence reduce Cu resistivity, as discussed in Sec. III. Reducing the line resistance directly translates to reduction of transmission line power loss.

In our experiments, we used our PECVD grown, large area TaS₂ films for initial prototype testing. The structure of the transmission line is shown in Fig. 15(a). 2-nm TaS₂ was first deposited on top of 1.5-μm SiO₂. Thick SiO₂ was selected to minimize the electrical feedthrough in the Si substrate during RF measurement. A 500-nm Al layer was then deposited and patterned to form electrodes for probing. Finally, 15-nm-thick/5-μm-wide Cu transmission line was deposited and patterned to connect the two Al electrodes. Such a thin Cu layer was chosen to enlarge surface/interface scattering, as discussed in Sec. III. In addition to the transmission line structure, “open” and “short” structures were also fabricated for the de-embedding process. “Open” structures have no Cu line between the two Al electrodes, while “short” structures connect Al signal pads directly to adjacent ground (GND) pads. RF characterization was performed using a standard two-port S-parameter measurement, with RF input power being set at −10 dBm. The measured information from the “open” and “short” features was used to de-embed the parasitic capacitance and inductance from the metal electrodes and electrical routing. Thus, the results after the de-embedding procedure reflect the behavior of the isolated Cu transmission line. Note that the conduction through the TaS₂ film is negligible here since the resistivity of TaS₂ (∼10⁷ μΩ cm) is orders of magnitude higher than Cu (∼10 μΩ cm with this dimension). The measured results of different devices with and without TaS₂ are shown in Fig. 15(b). It can be clearly observed that with the presence of TaS₂, the power loss of transmission lines is reduced, even when taking the device-to-device variation originated from the fabrication into account. The reduction of power loss is attributed to the reduction in Cu resistivity. In the DC regime, as shown in Ref. 27, the reduction in Cu resistivity is around 10%, while an average reduction of around 2% is obtained in the RF regime. Further power loss reduction can be achieved through quality improvement of the 2D films since we have observed a much larger resistivity reduction (∼45%) by using exfoliated, high quality MoS₂ films.⁷² Nevertheless, our results provide the initial validation that the benefits of 2D materials in the DC regime to reduce Cu resistivity can be translated to the RF regime to mitigate power loss.

To enable continued scaling of interconnect technology, 2D materials, owing to their atomic-thin-body nature, have been proposed and explored as the candidates for replacing conventional diffusion barriers and liners. This article has reviewed and summarized works on 2D materials such as Cu diffusion barrier and liner alternatives. DFT calculations have predicted that many 2D materials have the potential of being used as diffusion barriers. Experimental verifications of diffusion barrier properties using various techniques, including TVS, CV, and TDDB methods, have demonstrated that many 2D materials, including graphene, h-BN, MoS₂, and TaS₂, are suitable candidates. Since these techniques rely on large-area and continuous films, evaluations on many other 2D materials can be expected when their syntheses become more mature. In addition to diffusion barrier properties, liner properties are also critical when determining the potentials of 2D materials. Therefore, the tests of liner properties have been conducted in different aspects, including wettability, adhesion, and surface/interface scattering. Despite promising results in wettability and reduced surface scattering for many 2D materials, only TaS₂ has been shown to provide desirable adhesion with Cu up to date. Furthermore, the requirements and challenges of synthesizing 2D materials on dielectrics have also been discussed. One of the main challenges is the temperature required to realize high-quality films. Although BEOL compatible, low-temperature syntheses have been demonstrated and film quality could be compromised at low temperatures. Additionally, damage from plasma growth processes have to be mitigated to prevent quality degradation of low-k dielectrics. Finally, conformal deposition of ultra-thin 2D materials over damascene structures has to be carried out at BEOL compatible temperatures. In the aspect of circuit performance, since via resistance has become one of the bottlenecks, vertical conduction across these novel materials has to be studied. TaS₂ has been adopted as an example of conducting the study. In addition to serving as the barrier and liner for metal interconnects, 2D materials also possess promises in other applications, including eliminating electromigration and enhancing RF transmission line performance. The results have been demonstrated in the hope of encouraging more relevant research in the future. In summary, both the great potential and challenges of adopting 2D materials in BEOL have been extensively discussed throughout the article. Possible solutions for the remaining challenges and routes for future development have also been proposed.

The geometry optimization minimum potential energy surfaces for Cu diffusion across TMDs were carried out using DFT as implemented in the Vienna ab initio simulation package (VASP).^112,113 Projector-augmented-wave (PAW) potentials^114,115 were used to account for the electron–ion interactions, and the electron exchange-correlation potential was calculated using the generalized gradient approximation (GGA) within the Perdew–Burke–Ernzerhof (PBE)¹¹⁶ scheme using real-space projections. Since long-range dispersion interactions are not captured by the GGA functional, we employed Grimme’s DFT-D3 energy correction scheme to account for these interactions.¹¹⁷ In the DFT-D3 scheme, the Kohn–Sham DFT energy is corrected by adding a pairwise term that depends on the local environment of each atom. The kinetic energy cutoff for all calculations was set to 500 eV, and, due to the relatively large simulation size, a gamma-centered 4 × 4 × 1 mesh was used for the k-space sampling. A Gaussian smearing of 0.05 eV and an electronic relaxation tolerance of 1 × 10⁻⁵ eV was used for all calculations.

We used the climbing image nudged elastic band (NEB) method as implemented in VASP¹¹⁸ to determine the minimum potential energy surface and diffusion paths between known initial and final geometries with the Cu atom at local minima (on top of a metal atom for the 2H structures and opposite a chalcogen atom for the 1 T structures) on either side of a 4 × 4 monolayer TMD with ∼19–20 Å of vacuum between out-of-plane periodic images. The minima were obtained by structural relaxations using a conjugate gradient (CG) algorithm with a force tolerance of 0.01 eV/Å. The NEB calculations were initialized from a set of geometries interpolating between initial and final structures; then, the ionic positions of the different geometries are iteratively optimized using only the ionic-force components perpendicular to the hypertangent. The energy along the diffusion path was determined by spline interpolation based on the total energy of the individual geometries. Additional details regarding the NEB relaxations can be found in Subsection VIII C.

The NEB structural relaxations were carried out using either the damped molecular dynamics or quasi-Newton algorithms. If the NEB forces could not be converged to 0.01 eV/Å under “normal” precision (the VASP input specification PREC = Normal), the precision was increased (PREC = Accurate). If convergence could still not be achieved, the density of the FFT grid was increased (ADDGRID = True). Only 2H-TaS₂ could not be converged to 0.01 eV/Å and was instead converged to 0.05 eV/Å.

This work was supported in part by NEWLIMITS, a center in nCORE, a Semiconductor Research Corporation (SRC) program sponsored by NIST through Award No. 70NANB17H041. It is also funded by the National Science Foundation (NSF) through Grant No. CCF-1619062 and in part by the Center for Low Energy Systems Technology (LEAST), one of the six SRC STARnet Centers, sponsored by MARCO and DARPA. Computational resources from nanoHUB.org and Purdue University are gratefully acknowledged.

The data that support the findings of this study are available from the corresponding author upon reasonable request.