Superconducting optoelectronic loop neurons Open Access

Complete understanding of the information processing underlying cognition remains a significant scientific challenge. Progress in neuroscience, computer science, psychology, and neural engineering makes this a fruitful time for elucidation of intelligence. Biological experiments and software simulations would be greatly augmented by artificial hardware with complexity comparable to systems we know to be conscious. Intelligent systems implemented with hardware optimized for neural computing may inform us regarding the limits of cognition imposed by the speed of light while providing technological opportunities sufficient to spawn a new domain in the computing industry.

Neural computing appears uniquely capable of the distributed, yet integrated, information processing that characterizes intelligent systems. Many approaches to neural computing are being developed, and the maturity of the semicondutor industry makes CMOS a wise initial platform. Yet, the central role of communication in neural computing indicates that hardware incorporating different physics may be advantageous for this application. In previous work,¹ we considered the potential for superconducting optoelectronic hardware to perform neural operations. The principal assumption guiding the design of the hardware platform is that photons are the entities best suited for communication in large-scale neural systems. The hardware platform leverages optical communication over short and long distances to enable dense local fan-out as well as distant communication with the shortest possible delay. In this work, we present details of the design of superconducting optoelectronic neurons and networks that appear capable of achieving the functions required for cognitive computing.

This work expands upon the initial concepts presented in Ref. 1 in several ways. Most importantly, we introduce circuits that utilize light for communication between neurons but set synaptic weights in the electronic domain, thereby efficiently utilizing photons and enabling complex, event-based plasticity mechanisms. In Ref. 1, the proposed neural circuits were based on arrays of single-photon detectors (SPDs) in series or in parallel, and it was assumed that synaptic weights would be accomplished by varying the number of photons that reached the detector arrays. This approach to neuron design is inefficient because the production of photons dominates energy consumption in superconducting optoelectronic circuits, and more photons are generated than are used if the synaptic weight is established via variable attenuation in the photonic domain.

In the present work, we show that Josephson junctions (JJs) in conjunction with SPDs straightforwardly accomplish many neural operations and can be used to construct synapses that require a single photon for communication, with the synaptic weight set by the amount of electrical current generated during a photon-detection event. The simple SPD/JJ circuit investigated here transduces single-photon communication events to integrated supercurrent. We describe how to combine the signals of many such synapses in a shared integration loop using mutual inductors. We also discuss how to use these synapses to achieve inhibitory connections and dendritic processing. While the goal of photonic communication is to achieve high fan-out, in Ref. 1 fan-in was proposed to occur in the photonic domain. Here, we re-envision the dendritic tree and propose instead that a hierarchy of dendritic loops performs well for high fan-in. Regarding learning, we present techniques for controlling the synaptic weights, either through direct, electronic control for supervised training and machine learning or through correlated photon detection for spike-timing-dependent, short-term, homeostatic, and metaplasticity.

This work also goes beyond the initial concepts presented in Ref. 1 with the analysis of amplifier circuits capable of converting the current output from a JJ circuit to the voltage necessary to generate light from a semiconductor diode. Regarding scaling, this work builds on Ref. 1 with the consideration of networks characterized by graphs employed by cognitive systems. We analyze such networks to model spatial scaling and power consumption. We propose a routing architecture and consider the size of the computation and communication circuits in order to estimate network area and power density. We find that a network with 1$×106$ neurons and 200$×106$ synapses can fit on a 300 mm wafer and would dissipate less than 1 W of device power, illustrating the feasibility of cooling large-scale superconducting optoelectronic systems with conventional cryogenics. We conclude with the analysis of scaling limits due to the finite speed of light.

These refinements of superconducting optoelectronic network (SOEN) concepts have been summarized in a previous publication.² The present work is a more thorough treatment of the subject, exploring the conceptual motivation of this work as well as many details of circuit concepts and simulations that were not included in Ref. 2. We begin with a summary of the neuroscientific principles that guide the design of this hardware platform.

The foundational assumption of this work is that light is the physical entity best suited to achieve communication in cognitive neural systems. To motivate why light is essential for large-scale neural systems, we must describe the systems we intend to pursue.

Broadly speaking, we wish to pursue devices and networks capable of acquiring and assimilating information across a wide range of spatial, temporal, and categorical scales. In a neural cognitive system, spatial location within the network may correspond to information specific to content area or sensory modality, and spatial integration across the network corresponds to the integration across informational subjects and types. Information processing must occur across many levels of hierarchy with effective communication across local, regional, and global spatial scales, as well as temporal scales. These systems must continually place new information in context. It is required that a cognitive system maintain a slowly varying background representation of the world while transitioning between dynamical states under the influence of stimulus. The objective of this paper is to design general cognitive circuits with structural and dynamical attributes informed by neuroscience, network theory, and dynamical systems. Stated generally, systems combining functional specialization with functional integration are likely to perform well for many cognitive tasks.^3,4

The theme of localized, differentiated processing combined with information integration^5–11 across space^12,13 and time^14–18 is central to the device and network designs we consider here. In the spatial domain, the demand for integration of information from many local areas requires not only dense local connectivity (as measured by a clustering coefficient^19–21) but also connections between these local areas, which serve to combine the local information in a larger context at higher cognitive levels²² (as measured by a short average path length²³). High clustering combined with short average path length defines a small-world network.²⁴ For the highest performance, we expect this trend of integration of locally differentiated information to repeat across many scales in a nearly continuous manner^12,13 such that any node in the system is likely to be not only processing information with local neighbors but also receiving information from simpler, less-connected units, and transferring information to complex, highly connected units. Networks with this organization across scales are governed by power-law spatial scaling.²⁵ 

The patterns are related in the temporal domain where transient synchronized oscillations integrate information from various brain regions.^14–16 Information exchange can occur on very fast time scales, and results of these computations must be combined over longer times. The spatial structure of the network and its operation in the time domain are not independent.^3,4,26 Fast, local dynamics integrate information of closely related nodes through transient neuronal functional clusters,²⁷ while activity on slower scales can incorporate input from larger regions.²⁸ Networks with this organization in time are governed by a power-law frequency distribution,^17,18,29 characteristic of self-organized criticality.³⁰ Power-law spatial and temporal distributions underlie systems with fractal properties,^18,29 and self-similarity across space and time is advantageous for cognition.^18,30–34

These conceptual arguments regarding information integration across spatial and temporal scales lead us to anticipate networks utilizing hierarchical configuration, with processing on various scales being integrated at high levels to form a coherent cognitive state.²² The constitutive devices most capable of achieving these network functions are relaxation oscillators,^18,35 dynamical entities characterized by pulsing behavior³⁶ with resonant properties at many frequencies.^37,38 Neurons are a subset of relaxation oscillators with complex operations adapted for spike-based computation.³⁹ We return to relaxation oscillators shortly.

To illustrate how differentiated processing and information integration are implemented by neurons for cognition, consider vision.⁴⁰ In early stages of visual processing, neurons located near each other in space will show similar tuning curves⁴¹ in response to presented stimuli, thus forming locally coherent assemblies selecting for certain features of a visual scene.¹⁶ These locally differentiated processing units are constructed from architectural motifs^42,43 and are manifest in biological hardware as minicolumns and columns,⁴⁴ which are dedicated to modeling a subset of sensory space.⁴⁵ To form a more complete representation of an object within a visual scene, or to make sense of a complex visual scene with many objects, the visual system must combine the information from many differentiated processors. This integration is accomplished with lateral connections between columns³ as well as with feed-forward connections from earlier areas of visual cortex to later areas of visual cortex.⁴⁰ Such an architecture requires some of the neurons in any local region to have long-range projections, motivating the need for local connectivity for differentiated processing combined with distant connectivity for information integration across space.

To understand information integration in the time domain, consider synchronized oscillations at various frequencies in the context of the binding problem.^46,47 Stated as a question, the binding problem asks how the myriad stimuli presented to the brain can be quickly and continuously organized into a coherent cognitive moment. In the limited context of vision, we ask how a complex, dynamic visual scene can be structured into a discernible collection of objects that can be differentiated from each other and from an irrelevant background.⁴⁸ Many studies provide evidence that fast, local oscillations are modulated by slower oscillations encompassing more neurons across a larger portion of the network.^{14–18,28,49,50} In the case of columns in visual cortex, local clusters tuned to specific stimuli will form assemblies with transient synchronization at high frequencies (⁠$γ$ band, 20–80 Hz¹⁷). The information from many of these differentiated processors is integrated at higher levels of processing by synchronizing larger regions of neurons at lower frequencies (⁠$α$ band, 1–5 Hz, and $θ$ band, 4–10 Hz^17,28). The transient synchronization of neuronal assemblies is closely related to neuronal avalanches,^30,32 cascades of activity across many frequencies. Neuronal avalanches are observed in networks balanced at the critical point between order and chaos.^30–34 Self-similarity in the temporal domain implies operation at this critical point,^30,31,34 and operating at this phase transition is necessary to maximize the dynamic range of the network.³² Inhibition and activity-based plasticity are crucial for achieving this balance.^17,18,51

Networks of excitatory principal neurons interspersed with inhibitory interneurons⁵² with small-world characteristics naturally synchronize at frequencies determined by the circuit and network properties.¹⁸ Slower frequency collective oscillations of networks of inhibitory interneurons provide short windows when certain clusters of excitatory neurons are uninhibited and, therefore, susceptible to spiking.⁵³ This feedback through the inhibitory interneuron network provides a top-down means by which the dynamical state of the system can provide broad information to the local processing clusters.^16,50 Regions of cortex with higher information integration focus attention¹⁵ on certain aspects of stimulus by opening receptive frequency windows at the resonant frequencies of relevant subprocessors, providing a mechanism by which binding occurs and background is ignored.^16,17,49,50 The result of this inhibitory structuring of time is a network with dynamic effective connectivity.^22,50 By constructing a network with a small-world, power-law architecture from highly tunable relaxation oscillators and employing feedback through inhibitory oscillations, we produce a system that can change its effective structural and resonant properties very rapidly based on information gleaned from prior experiences of a large region of the network.^17,50

This model of binding requires a means by which the resonant frequencies of neuronal assemblies can be associated with certain stimuli, and a means by which the inhibitory interneuron network can learn to associate different assemblies with different frequencies. Plastic synaptic weights make such adaptation possible. Synapses provide a means for the connectivity of the network to shape dynamics and functionality, and synapses adapt their states based on internal and external activities. As cortex evolves through dynamical states on various temporal and spatial scales, information stored in synapses is integrated across the network and used as a feedback to distributed subprocessors.^16,50

For a cognitive system embedded in a dynamical environment to provide adaptive feedback as well as robust memory, the system must comprise a large number of synapses changing on different time scales due to different internal and external factors.⁵⁴ Synapses with many stable values of efficacy can significantly increase memory retention times,⁵⁵ and synapses that adapt not only their state of efficacy but also their probability of state transition are crucial for maximizing memory retention times.^54,56 Adaptation of probability of state transition is a mechanism of metaplasticity,⁵⁷ and many forms appear in biological systems. We expect a cognitive system to utilize differentiated regions of neurons, some with synapses changing readily between only two synaptic states, and other regions with synapses changing slowly between many distinguishable states. We further expect the network to update not only synaptic weights but also the probability of changing synaptic weights. The dynamical state of the system can then sample synaptic memory acquired at many times, in many contexts, while quickly adapting the dynamical trajectory as new stimulus is presented.

To summarize, cognition appears to require differentiated local processing combined with information integration across space, time, and experience. The structure of the network determines the dynamical state space, and the structure of the network adapts in response to stimulus and internal activity. We now ask the question: What physical systems are best equipped to perform these operations?

The aforementioned insights from neuroscience lead us to emphasize several features of neural systems in hardware for cognition. First, we must use a physical signaling mechanism capable of achieving communication across networks with dense local clustering, midrange connectivity, and large-scale integration. Second, the relaxation oscillators that constitute the computational primitives of the system must perform many dynamical functions with a wide variety of time constants to enable and maximally utilize information processing through transient synchronized assemblies. Third, a variety of synapses must be achievable, ranging from binary to multistable. The strength of these synapses must adjust due to network activity, as must the update frequency.

A principal challenge of differentiated computation with integrated information is communication. The core concept of the superconducting optoelectronic hardware platform is that light is excellent for this purpose. Light excels at communication for three reasons. First, light experiences no capacitance, resistance, or inductance, so dense, local clustering as well as long-range connections can be achieved without charge-based wiring parasitics. Second, it is possible to signal with single quanta of the electromagnetic field, thereby enabling the energy efficiency necessary for scaling. Third, light is the fastest entity in the universe. Short communication delays are ideal for maximizing the number of synchronized oscillations a neuron can participate in as well as the size of the neuronal pool participating in a synchronized oscillation. Light-speed communication, therefore, facilitates large networks with rich dynamics.

We have argued elsewhere¹ that parasitics of electronic interconnects limit communication in neural systems. These limitations are ultimately due to the charge of the electron and its mass. Signals in the brain are transmitted via ionic conduction. The operating voltage of biological neurons is near 70 mV, so the energy penalty of $CV2/2$ is significantly reduced relative to semiconducting technologies operating at 1 V, and direct connections are possible. Yet, the low mobility of ions results in slow signal velocities, severely limiting the total size of biological neural systems.¹⁸ Uncharged massless particles are better suited for communication in cognitive neural systems. Light is the natural candidate for this operation. It is possible for a single optical source to fan its signals out to a very large number of recipients. This fan-out can be implemented in free space, over fiber optic networks, or in dielectric waveguides at the chip and wafer scales. For large neural systems, it will be advantageous to employ all these media for signal routing. The presence of excellent waveguiding materials and a variety of light sources inclines us to utilize optical signals with $1μm≤λ≤2μm$⁠. Additionally, because the energy of a photon and its wavelength are inversely proportional, optoelectronic circuits face a power/area trade-off. Similar circuits to those presented here could be implemented with microwave circuits, but the system size would likely be cumbersome. Operation near telecommunication wavelengths appears to strike a suitable compromise.

The foundational conjecture of the proposed hardware platform is that light is optimal for communication in cognitive systems. The subsequent conjecture is that power consumption will be minimized if single photons of light can be sent and received as signals between neurons in the system. Superconducting single-photon detectors are the best candidate for receiving the photonic signals. In addition to selecting microscale light sources and dielectric waveguides, we choose to utilize superconduting-nanowire single-photon detectors^58–61 to receive photonic signals because of the speed,⁶² efficiency,⁶¹ and scalable fabrication⁶³ of these devices.

Utilizing superconducting single-photon detectors contributes to energy efficiency in three ways. First, because a single photon is a quantum of the electromagnetic field, it is not possible to signal with less energy at a given wavelength. Second, because the device is superconducting, it dissipates near zero power when it is not responding to a detection event. Third, the power dissipated by the detector during a detection event is on the order of the energy used to generate the photon being detected, so a significant additional energy penalty is not incurred.

The choice of employing superconductors has several important ramifications. It requires that we operate at temperatures that support a superconducting ground state (⁠$≈4K$⁠), so cryogenic cooling must be implemented. While cooling is an inconvenience, employment of superconducting detectors brings the opportunity to utilize the entire suite of superconducting electronic devices,^64–66 including JJs and thin-film components such as current^67,68 and voltage⁶⁹ amplifiers. Semiconductor light sources also benefit from low temperature,⁷⁰ and silicon light sources become an option.⁶³ 

We have emphasized that the charge and mass of electrons are a hindrance for communication. Yet, the interactions between electrons due to their charge make them well suited to perform the computation and memory functions of synapses and neurons. In particular, superconducting devices and circuits are exceptionally capable of achieving the complex dynamical systems necessary for cognition. To elucidate the specific type of dynamical devices we intend to employ, we now elaborate upon the strengths of relaxation oscillators for cognitive systems.

A defining aspect of cognitive systems is the ability to differentiate locally to create many subprocessors, but also to integrate the information from many small regions into a cohesive system, and to repeat this architecture across many spatial and temporal scales. A network of many dynamical nodes, each with the capability of operating at many frequencies, gives rise to a vast state space. As computational primitives that can enable such a dynamical system, oscillators are ideal candidates. In particular, relaxation oscillators^{18,35–38,49,71–73} with temporal dynamics on multiple time scales³⁷ have many attractive properties for neural computing, which is likely why the brain is constructed of such devices.⁷⁴ We define a relaxation oscillator as an element, circuit, or system that produces rapid surges of a physical quantity or signal as the result of a cycle of accumulation and discharge. Relaxation oscillators are energy efficient in that they generally experience a long quiescent period followed by a short burst of activity. Timing between these short pulses can be precisely defined and detected.¹⁸ Relaxation oscillators can operate at many frequencies³⁸ and engage with myriad dynamical interactions.⁴⁹ The oscillator’s response is tunable,³⁸ they are resilient to noise because their signals are effectively binary,⁷⁵ and they can encode information in their mean oscillation frequency as well as in higher-order timing correlations.^14,76–80

The relaxation oscillators we intend to employ as the computational primitives of superconducting optoelectronic networks can be as simple as integrate-and-fire neurons^39,41 or more complex with the addition of features such as dendritic processing^14,77–80 to inhibit specific sets of connections^17,18,52 or detect timing correlations and sequences of activity.^14,80 While our choice to use superconductors was motivated by the need to detect single photons, we find superconducting circuits combining SPDs and JJs are well suited for the construction of relaxation oscillators with the properties required for neural circuits.

We refer to relaxation oscillators sending few-photon signals that are received with superconducting detectors as superconducting optoelectronic neurons. In the specific neurons studied in this work, integration, synaptic plasticity, and dendritic processing are implemented with inductively coupled loops of supercurrent. We refer to devices of this type as loop neurons. The loop neuron presented in this paper is shown schematically in Fig. 1. A full circuit diagram is shown in Fig. 23. The remainder of this section is an overview of the circuits described in more detail in the rest of the paper. Operation of loop neurons is summarized as follows.

Photons from upstream neurons are received by superconducting SPDs at a neuron’s synapses. Using Josephson circuits, these detection events are converted into an integrated supercurrent which is stored in a superconducting loop. The amount of current that gets added to the integration loop during a photon detection event is determined by the synaptic weight. The synaptic weight is dynamically adjusted by another circuit combining SPDs and JJs. When the integrated current of a given neuron reaches a (dynamically variable) threshold, an amplification cascade begins, resulting in the production of light from a waveguide-integrated semiconductor light emitter. The photons thus produced fan out through a network of dielectric waveguides and arrive at the synaptic terminals of other neurons where the process repeats.

In these loop neurons, a synapse consists of an SPD in parallel with a JJ (which together transduce photons to supercurrent), and a superconducting loop, which stores a current proportional to the number of detected photon arrival events. This loop is referred to as the synaptic integration (SI) loop. Within each neuron, the loops of many synapses are inductively coupled to a larger superconducting loop, referred to as the neuronal receiving (NR) loop, thereby inducing an integrated current proportional to the current in all the neuron’s synapses. When the current in this NR loop reaches a threshold, the neuron produces a current pulse in the form of a flux quantum. This current is amplified and converted to voltage to produce photons from a semiconductor $p−i−n$ junction.

The currents in the synaptic and neuronal loops are analogous to the membrane potential of biological neurons,⁴¹ and the states of flux in these loops are the principal dynamical variables of the synapses and neurons in the system. Inhibitory synapses can be achieved through mutual inductors with the opposite sign of coupling. Dendritic processing can be implemented straightforwardly by adding intermediate mutually inductively coupled loops between the synaptic and neuronal loops. Synapses can be grouped on dendritic loops capable of local, nonlinear processing and inhibition.^14,18,52 Dendrites capable of detecting specific sequences of synaptic firing events^77,80 can also be achieved. Neurons with multiple levels of dendritic hierarchy can be implemented as multiple stages of integrating loops. Clustering synapses on multiple levels of hierarchy in this way enables information access at gradually larger length scales across the network through transient synchronization at gradually lower frequencies.²⁸ The temporal scales of the loops can be set with $L/r$ time constants, so different components can operate on different temporal scales, enabling relaxation oscillators with rich temporal dynamics. These relaxation oscillators can be combined in networks with dynamic functional connectivity, reconfigurable through inhibition and synaptic plasticity.^50,52 These receiver circuits and integration loops are presented in Sec. II.

Synaptic memory is also implemented based on the stored flux in a loop, referred to as the synaptic storage (SS) loop. The state of flux in the SS loop determines the current bias to the synaptic receiver circuit discussed above. This current bias is the synaptic weight. If the SS loop is created with a superconducting wire of high inductance, the loop can hold many discrete states of flux and, therefore, can implement many synaptic weights. In Sec. III, we investigate synapses with a pseudocontinuum of hundreds of stable synaptic levels between minimal and maximal saturation values, and we show that transitions between these levels can be induced based on the relative arrival times of photons from the presynaptic and postsynaptic neurons, thereby establishing a means for spike-timing-dependent plasticity (STDP) with one photon required for each step of the memory-update process.

While synapses with many stable levels are advantageous to extending memory retention times,⁵⁵ it is also important to implement synapses that change not only their efficacy based on pre- and postsynaptic spike timing but also their probability of changing their efficacy.⁵⁴ Just as the synaptic weight is adjusted through a current bias on the receiver circuit, the probability of changing the synaptic weight can be adjusted through a current bias on the synaptic update circuit. As in the dendrites, we see a hierarchy can be achieved. In the case of synaptic memory, the synaptic weight and its rates of change are implemented in a loop hierarchy, and the state of flux in the loops can be dynamically modified based on photons generated by neural activity. Similar mechanisms can be utilized to adjust the synaptic weight based on short-term activity from the presynaptic neuron⁸¹ or on a slowly varying temporal average of the postsynaptic activity.^82,83 The synaptic memory circuits we develop in Sec. III are logical extensions of binary memory cells utilized in superconducting digital electronics.^65,66

The aspect of superconducting optoelectronic neuron operation that is most difficult to achieve is the production of light. The superconducting electronic circuits that perform the aforementioned synaptic and neuronal operations operate at millivolt levels, whereas the production of the near-infrared photons desirable for communication requires a volt across a semiconductor diode. When a neuron reaches threshold, an amplification sequence begins. Current amplification is first performed, and the resulting large supercurrent is used to induce a superconducting-to-normal phase transition in a length of wire. When the current-biased wire becomes resistive, a voltage is produced via Ohm’s law. This device leverages the extreme nonlinearity of the quantum phase transition to quickly produce a large voltage and an optical pulse. These transmitter circuits are discussed in Sec. IV.

The photons of a neuronal pulse are distributed over a large axonal network of passive dielectric waveguides. These waveguides terminate at each of the downstream synaptic connections. A downstream synaptic firing event will occur with near-unity probability at any connection receiving one or more photons. Photons of multiple colors can be generated simultaneously or independently, and different colors can share routing waveguides, while being used for different functions on the receiving end, such as synaptic firing and synaptic update. The number of photons produced during a neuronal firing event determines the probability that distant connections will receive the signal, and this reach can be manipulated with the current bias to the light emitter. The network of waveguides that routes the communication events is discussed in Sec. V.

To make the analogy to biological neural hardware explicit, synapses are manifest as circuits comprising superconducting SPDs with JJs. These synapses transduce photonic communication signals to supercurrent for information processing, and this supercurrent plays the role of the membrane potential. The dendritic arbor is a spatial distribution of synapses interconnected with inductively coupled loops for intermediate integration and nonlinear processing. The integration function of the soma is also achieved with a superconducting loop, and the threshold is detected when a JJ in this loop is driven above its critical current. The firing function of the soma (or axon hillock) is carried out by a chain of superconducting current and voltage amplifiers that drive a semiconductor diode to produce light. The axonal arbor is manifest as dielectric waveguides that route photonic signals to downstream synaptic connections. Gap junctions may be realized with evanescent couplers between waveguides of the axonal arbor, but we do not consider gap junctions further in this paper.

Loop neurons combine several core devices: superconducting single-photon detectors,^58–61 Josephson junctions,^64–66 superconducting mutual inductors,⁸⁴ superconducting current^67,68 and voltage amplifiers,⁶⁹ semiconductor light sources,^1,63 and passive dielectric waveguide routing networks.^85–87 While all the components of these neurons have been demonstrated independently, their combined operation has not been shown. The experimental effort to achieve circuit integration is underway. The physical principles of their operation and the designs presented in this paper indicate the potential for loop neurons to achieve complex, large-scale systems. The straightforward implementation of inhibition; the realization of a variety of temporal scales through $L/r$ time constants; single-photon-induced synaptic plasticity; and dynamically variable learning rate, threshold, and reach indicate these relaxation oscillators are promising as computational primitives. In conjunction with dense local and fast distant communication over passive waveguides, the system appears capable of the spatial and temporal information integration necessary for cognition and binding.

We do not propose superconducting optoelectronic networks (SOENs) as an alternative to established neural hardware, but rather as a symbiotic technology. The success of neural CMOS (including optical communication above a certain spatial scale) will contribute to the success of SOENs, as it will be advantageous for SOENs to interface with CMOS via photonic signaling over fiber optic links between cryogenic and ambient environments. SOEN hardware is particularly well suited to interfacing with other cryogenic technologies such as imaging systems with superconducting sensors,^88,89 as are commonly employed for medical diagnostics,⁹⁰ exoplanet search,^91–93 cosmology,⁹⁴ and particle detectors.⁹⁵ Another intriguing application is in conjunction with other advanced computing technologies such as flux-based logic^96–98 and quantum computers.^99–103 One can envision a hybrid computational platform^104,105 wherein a quantum module utilizes entanglement and superposition, while a neural module performs quantum-limited measurements and learns the behavior of the quantum system, and classical fluxon logic controls the operation of both. A superconducting optoelectronic hardware platform is likely to satisfy the computation and communication requirements of this hybrid technology.

At this point, we have described the motivations for loop neurons, and we have summarized their operation. The remainder of the document contains technical details of circuit operations (Secs. II–IV) and scaling analysis (Sec. V).

The focus of this section is on the conversion of photonic communication events on many synapses to an integrated total signal stored in the neuron. These optoelectronic devices must meet several criteria: (1) the neuron must be able to achieve leaky integrate-and-fire functionality^39,41 wherein activity on multiple synapses contributes to an integrated signal with a controllable leak rate; (2) single-photon detection events must contribute to the integrated signal, and the amount each detection event contributes to the integrated signal should depend on a dynamically reconfigurable synaptic weight; (3) neurons that are sensitive to the sum of spike events must be achievable in order to make use of rate-coded signals,¹⁰⁶ and neurons that are sensitive to the timing between afferent spikes must also be achievable in order to make use of temporal coding;^14,39,75,77 (4) the circuits must scale to thousands of synaptic connections to integrate information across moderately sized cognitive circuits;¹⁸⁰ (5) the dynamic range of the neuron and synapses should allow activity on a large fraction of the synapses to contribute to a neuronal firing event, yet repeated activity on a small fraction of the synapses should also be able to induce a neuronal firing event; (6) synapses with inhibitory as well as excitatory functionality must be achievable, and inhibition must work in conjunction with dendrites^17,18,80 to enable synchronization on multiple time scales.^14–17,52 This section explores circuit designs satisfying these criteria.

The synaptic receiver is enclosed within the dashed boundary of Fig. 2(a). A simple instantiation of the synaptic circuit is shown in Fig. 2(b), and the operation of the synapse is illustrated schematically in Fig. 2(c). This receiver circuit in the context of the other components of the neural circuit is shown in Fig. 23 in Sec. IV. The synaptic receiver circuit comprises an SPD in parallel with a JJ embedded in a flux-storage loop. This design is a reasonable starting point for a single-photon-sensitive synapse because it achieves transduction of a photonic signal to a superconducting electronic signal with a simple circuit. The design is similar to other superconducting particle detector circuits, such as transition-edge bolometers.⁶⁵ 

The operation of the synaptic circuit proceeds as follows. The SPD, shown as a variable resistor in series with an inductor in Fig. 2(b), has zero resistance in the steady state, and it switches to a high-resistance state temporarily upon absorption of a photon. When a photon is detected, an electrical current is diverted from the SPD to a JJ, referred to as the synaptic firing junction (⁠$Jsf$⁠). The current diverted from the SPD [Fig. 2(c), part (i)] causes the net current through $Jsf$ to exceed $Ic$⁠, generating a series of fluxons [Fig. 2(c), part (ii)]. We refer to this detection of a photon by the SPD and subsequent generation of fluxons by the JJ as a synaptic firing event. The synaptic weight of the connection is implemented via the current bias across $Jsf$⁠, controlled by $Isy$⁠. The effect of this synaptic weight is to change the duration the JJ bias current exceeds $Ic$⁠, and, therefore, the number of fluxons generated during a synaptic firing event. If the synaptic weight is weak, a small number of fluxons, and, therefore, a small total amount of supercurrent, will be generated. If the synaptic weight is strong, a large number of fluxons, and, therefore, a large amount of supercurrent, will be generated during the synaptic firing event. The SPD response is virtually identical whether the number of photons present is one or greater than one, and for energy efficiency, it is advantageous to send the fewest number of photons possible to each synaptic connection. The SPD response also does not depend strongly on the frequency of light across a bandwidth broad enough for multiplexing.⁶¹ Implementing synaptic weight in the electronic domain in this manner makes use of both the speed and energy efficiency of JJs, while leveraging the strengths of light for communication.

The supercurrent generated during each synaptic firing event is added to a superconducting loop, called the synaptic integration (SI) loop, which integrates the total current from all synaptic firing events at that synapse [Fig. 2(c), part (iii)]. Many synapses will be coupled to a larger neuronal receiving (NR) loop via mutual inductors. The NR loop combines the signals from all the synapses connected to the neuron. Ultimately, the current coupled to the NR loop is increased using a current transformer that induces current in a final loop, the neuronal thresholding (NT) loop. The NT loop is a superconducting loop that contains a JJ (⁠$Jth$⁠) that produces an output current pulse when its critical current (threshold) is reached.¹⁰⁸ This threshold can be dynamically varied with a current bias. The current pulse generated when the neuron reaches threshold is amplified and ultimately used to trigger a photon-generation event.

The number of flux quanta generated in a synaptic firing event depends on the relation between $Ic$⁠, $Ispd$⁠, and $Isy$⁠, as well as the SPD time constant, $Lspd/rspd$⁠. If the bias current $I$ is close to but greater than $Ic$⁠, the time-averaged voltage across the junction will be given by $⟨V⟩≈RI2−Ic2$⁠, (in the limit of an overdamped junction⁶⁶) where $R$ is the junction resistance in the nonsuperconducting state. The rate of generation of flux quanta is given by $rfq=⟨V⟩/Φ0$⁠.⁶⁶ This generated flux is trapped in the SI loop. The utilization of a JJ in this circuit is advantageous to decouple the amount of current added to the loop from the time it is stored in the loop. The current in each SI loop decays with the $τsi=Lsi/rsi$ time constant, which can be chosen over a broad range. By choosing $τsi$ to be different for different synapses, one can diversify the temporal information provided to the neuron.^17,28,30,81

The circuit of Fig. 2(b) captures the concept of the receiver, but its performance is limited in this configuration because the SI loop saturates at a small current. Higher saturation current is achieved by separating the transduction operation from the SI loop by a Josephson transmission line (JTL),^65,66 as shown in Fig. 3(a). This form of the receiver circuit is the form used as a synapse in this work.

In the configuration of Fig. 3(a), the fluxons produced by the switching of $Jsf$ during a synaptic firing event propagate down a JTL (a single JJ in this study) and drive the switching of a junction inside the SI loop. The fluxons from multiple synaptic firing events can be stored in the SI loop, and, therefore, we may wish to use a loop that can contain many fluxons. The current added to the loop by a single fluxon is $Iϕ=Φ0/Lsi$⁠, where $Φ0=h/2e=2.07×10−15$ Wb is the magnetic flux quantum. The SI loop can maintain a linear response in the presence of many synaptic firing events if $Lsi$ is chosen to be large, or the SI loop can saturate if $Lsi$ is chosen to be small, thus providing one means of implementing short-term plasticity.⁸¹ 

The SI loops are inductively coupled to the NR loop, [Fig. 3(b)], which stores a current proportional to a weighted sum of the currents in all the SI loops. The use of mutual inductors allows many synapses to add current to an NR loop without introducing leakage current pathways. Finally, the NR loop couples to a third loop, the NT loop. The mutual inductor coupling the NR loop to the NT loop serves as a transformer to step up the current to be detected at threshold. The NT loop may not need to be a separate loop when the number of synapses, $Nsy$⁠, is small. The performance of the NT loop upon reaching current threshold is discussed in Sec. IV.

In Fig. 4, we simulate the operation of the synaptic receiver as it experiences a synaptic firing event. We use WRSpice¹⁰⁹ to model the circuit of Fig. 3(a). We treat the SPD as a current source with exponential rise with 100 ps time constant followed by exponential decay with 50 ns time constant. The amplitude of the SPD current pulse is $10μA$⁠. All circuit parameters used in this work are given in  Appendix A. Figures 4(a)–4(c) show the activity of a synaptic firing event for $Isy=800nA$⁠, $1μA$⁠, and $3μA$⁠. With $Isy=800nA$⁠, the junction is briefly driven above $Ic$⁠, and eight fluxons are transmitted to the SI loop. The synaptic firing event causes the current in the SI loop, $Isi$⁠, to increase by 1.7 nA. If we increase the bias current to $Isy=1μA$⁠, the synaptic firing event produces 33 fluxons and adds 7 nA to the SI loop. Further increasing the synaptic bias (SB) to $3μA$ gives the behavior shown in Fig. 4(c). In this case, 497 fluxons add 103 nA to the SI loop. The period of the voltage pulses is observed to decrease through the duration of the SPD pulse, demonstrating the decrease of $rfq$ as current returns to the SPD and the net bias across the JJ decays, as discussed above. Details of synaptic firing are shown in Figs. 4(d)–4(g). The energy consumed by a synaptic firing event is discussed in  Appendix A.

The analysis of Fig. 4 gives the currents and voltages present during a synaptic firing event for three values of $Isy$⁠. Systematic analysis of $Isi$ vs $Isy$ finds a quadratic trend. A principal objective of this analysis is to determine the range of synaptic bias currents over which we would like to operate. Operating with a minimum synaptic bias of $1μA$ enables us to work close to the energy-efficiency limit of the circuit, and we anticipate that the exact number of fluxons produced during a firing event will be noisy, much like the activity of a biological neuron.⁷⁵ The amount of current added to the SI loop during a synaptic firing event with strong synaptic weight should be significantly larger than the amount of current with a weak synaptic weight. We choose $Isy=3μA$ to be the largest synaptic bias at which we would like to operate, and thus, a synaptic firing event with a strong synaptic bias adds 15 times as much current to the SI loop (and, therefore, the NR loop and the NT loop) as a firing event with a weak synaptic bias. This ratio is entirely tunable based on the needs of the system. Learning—either supervised or unsupervised—should adjust the synaptic bias current over the range $1μA<Isy<3μA$ for the parameters considered here. Circuits accomplishing this are discussed in Sec. III.

In the circuit of Fig. 3(a), synaptic activity can result in saturation of the SI loop, wherein additional synaptic firing activity adds no additional current to the loop. The value of $Isi$ at which saturation occurs can be controlled in circuit design, and in the present work, it is near $10μA$⁠. The amount of current added to the loop by a single fluxon is given by $ΔIsi=Φ0/Lsi$⁠, so the number of synaptic firing events that cause saturation can be adjusted across a broad range. With a small value of $Lsi$⁠, a single synapse event can saturate the loop, and with a large value, the loop can maintain a linear response in the presence of many repeated synapse events. The SI loop with the design described above can receive over 1000 synaptic firing events when $Isy=1μA$⁠, and 82 synaptic firing events when $Isy=3μA$ before saturation of the loop occurs (assuming $Lsi=10μH$ and $τsi→∞$⁠). If the loop contains a resistance, the trapped flux will leak with the $L/r$ time constant, leaving the synapse ready to receive further synaptic firing events.

In general, a neuron will combine signals from many synaptic connections and produce a pulse when this combined signal reaches a threshold. We would like to know how devices will perform when many synapses are integrated with a single NR loop. An important question is how many SI loops must receive activity to drive the NT loop to threshold. We have analyzed the current induced in the NT loop as a function of the number of synapses inductively coupled to the NR loop. We find that with symmetrical mutual inductors of 100 pH, if the NR loop receives 1000 inputs, a saturated SI loop will still induce nearly 500 nA in the NT loop. If the NT loop requires $5μA$ to threshold (a number comfortably above the noise level), then 10 saturated synapses can cause the neuron to fire. Evidence from neuroscience indicates that a neuron with $N$ synapses is commonly driven to fire by activity on $N$ synapses^110,111 (with significant diversity in responses observed), and this analysis finds that coupling through mutual inductors makes the required synaptic strength possible, even when 1000 connections are made to a single NR loop. Further improvement is likely possible with asymmetric mutual inductors. Perhaps more importantly, in mature network architectures, neurons receiving input from thousands of synapses are likely to employ a complex dendritic tree. It is unlikely that any one dendrite will receive activity from 1000 synapses, and the range of synaptic efficacy achievable with these circuits is well-matched to the threshold current levels that will be convenient in practice.

We wish to know how inductively coupling multiple SI loops to a single NR loop affects the operation during synaptic firing events with regard to cross talk. Cross talk between synapses is small in this configuration, primarily because the self-inductance of each SI loop (⁠$Lsi$⁠) is much larger that the mutual inductance between each SI loop and the NR loop (⁠$Msy$⁠). For example, a typical value for $Lsi$ is on the order of 100 nH, while a typical value for $Msy$ is on the order of 100 pH. To arrive at analytical expressions for the cross talk between two SI loops coupled to the same NR loop, we assume that one synapse experiences a synaptic firing event, current is added to that SI loop, and we ask how much current is induced in the other SI loops due to their mutual coupling to the same NR loop. In the limit that $Lsi≫Msy$⁠, this induced parasitic current scales as $Msy/(NsyLsi)$⁠, where $Nsy$ is the total number of synapses (SI loops) coupled to the same NR loop. For typical values of $Msy$ and $Lsi$⁠, this quantity is on the order of $10−3$ for $Nsy=1$ and decreases as synapses are added to the loop. Therefore, cross talk between SI loops coupled to the same NR loop is not problematic with this fan-in design. We may also ask about the ratio of the intended current induced in the NR loop to the parasitic current induced in adjacent SI loops. This quantity is independent of $Nsy$⁠, and in the same limit of $Lsi≫Msy$⁠, we find that the ratio of the current induced in adjacent SI loops to the current induced in the NR loop is $Msy/Lsi$⁠, which again is on the order of $10−3$ for typical circuit parameters.

We have further investigated this cross talk numerically. WRSpice simulations show that a synaptic firing event of a neuron with a single synaptic connection and a synaptic firing event of a single synapse connected to an NR loop with 10 synaptic connections produce an identical number of fluxons with identical timing. The effect of timing delay between two synaptic firing events on different synapses in a neuron of $Nsy=10$ has also been considered. The total current added to the NR loop is independent of the timing delay between the two synaptic firing events. These linearities with respect to $Nsy$ and pulse timing delay are attractive features of inductively coupled synapses. Contexts in which nonlinearity with respect to arrival time is desirable, such as for temporal coding^14,77 or dendritic processing,^79,80 are likely to employ two-photon receiver circuits or dendritic loops as discussed in Sec. II C.

It is important for a neuron to be able to receive excitatory and inhibitory connections.^{41,52,110,112} Inhibitory connections keep the network from experiencing runaway activity and are crucial for temporal synchronization.^14–18 Inhibitory connections can be constructed with the same photon-to-fluxon transduction circuit presented thus far by changing the sign of $Msy$⁠. We investigate a neuron with seven excitatory and three inhibitory connections in Fig. 5. The figure shows a time trace of $Ini$ as three excitatory and two inhibitory synaptic firing events occur. An excitatory event and an inhibitory event occur in synapses with $Isy=1μA$⁠, and the other events occur in synapses with $Isy=3μA$⁠. This plot demonstrates the dynamic state of a multisynaptic neuron under the influence of excitation and inhibition.

The symmetry between inhibitory and excitatory synapses is broken by $Ibth$⁠, the current bias across the thresholding junction. The circuit can be designed so the saturation of all inhibitory SI loops is insufficient to add enough counter current to the NT loop to overcome $Ibth$ and reach threshold. Thus, repeated excitatory events can drive the neuron to spike, but repeated inhibitory events can only move the device further from threshold and cannot trigger a spike, much like the polarizing effects of inhibitory interneurons in biological neural systems.

In addition to neurons that integrate single-photon pulses, as described in Sec. II A, it is desirable to achieve neurons that detect coincident signals from two or more presynaptic neurons for detecting temporally coded information.^{14,77–80,113} The mutual information regarding a stimulus conveyed by two or more neurons can be approximated by a Volterra expansion³⁹ with the leading term corresponding to firing rate, and the second-order term representing correlations.⁷⁶ In biological neurons, temporal synaptic sequences can be detected using hardware nonlinearities present in dendrites,^79,80 which perform important cortical computations. Detection of timing correlations and sequences can be achieved in optoelectronic hardware using two (or more) SPDs in a similar circuit to the synaptic receiver of Fig. 3(a).

In Fig. 6, we analyze a two-photon symmetrical coincidence detection circuit. The circuit diagram is shown in Fig. 6(a). The two SPDs are biased symmetrically, and the circuit is designed such that if either SPD detects a photon in isolation, the current across $Jsf$ remains below $Ic$⁠, but if both detect a photon within a certain time window, the current across $Jsf$ can exceed $Ic$⁠, adding current to the SI loop. The amount of current added to the SI loop is plotted as a function of the difference in arrival times between two photons in Fig. 6(b). WRSpice was again used for these simulations, but in this case, the SPDs were modeled not as current sources but as resistors of $5kΩ$ with 200 ps duration occurring at specified photon-arrival times.⁶² The time scale over which correlated events are detected is set by the $Lspd/rspd$ time constant of the circuit. In the main panel, this time constant is 500 ns, and in the inset, it is 50 ns. Longer correlation windows can be straightforwardly achieved, and the shortest correlation window will be limited by the latching time of the SPDs.

Due to the symmetric biasing of the two SPDs, the circuit of Fig. 6 is insensitive to order of photon arrival. By breaking this symmetry, similar receiver circuits that detect ordered correlations can be used for Hebbian learning. The two-SPD circuit of Fig. 6 can also be extended to detect other sequences of activity, including sequences with more photons.

Dendritic processing can also be used for intermediate nonlinear processing between synapses and the NR loop.¹¹⁴ An example circuit is shown in Fig. 7. Here, multiple SI loops are inductively coupled to another loop, which contains a JJ. Only when the junction is driven above its critical current does an appreciable signal get added to the dendritic integration (DI) loop, which is an intermediate, nonlinear processor between the SI loop and the NR loop. In this case, the DI loops are analogous to dendrites. An important role of dendrites is in conjunction with inhibitory interneurons that can temporarily suppress the efficacy of an entire dendrite.^17,18,52 At the bottom of Fig. 7, we show how an inhibitory interneuron may be inductively coupled to a dendrite. When inhibition is applied to the loop, it may be impossible for the synaptic connections to drive the JJ above threshold and add flux to the DI loop. Many levels of loop hierarchies can be combined in this way to achieve various nonlinear functions as well as current amplification before the NT loop.

Dendritic processing in conjunction with inhibitory interneurons contributes to network synchronization on various temporal and spatial scales.^{14–16,18,27,52} The approach to dendrites shown in Fig. 7 is one way inhibition could be used with the synapses presented here to achieve these functions thought to be necessary for cognition.^17,50 In this context, engineering synaptic and dentritic circuits with a variety of time constants (analogous to membrane time constants) is important, as these time constants affect synchronization frequency⁴⁹ and enable neurons with a greater diversity of synapses.¹¹⁵ As discussed in Sec. I, power-law dynamics are necessary for information integration and self-organized criticality, and a power-law frequency distribution can be achieved through the superposition of exponential decay functions with a diversity of time constants.³⁰ To achieve this with the dendritic processors shown in Fig. 7, resistors are placed in each DI loop. The $L/r$ time constant of each DI loop will set its temporal response, and in this way, different dendrites can be given different time constants. Similarly, a resistor can be placed in each SI loop so that each synaptic excitation has a characteristic time constant, as discussed previously. These resistors will also accomplish the task of purging flux from the SI and DI loops to avoid saturation. As indicated in Fig. 7, inhibition can be applied at various points in the loop hierarchy, including specific synaptic loops, dendritic loops, the neuronal loop, and even the current source to the light emitter. These different structural implementations of inhibition are analogous to the three main forms of inhibition observed in biological neurons, wherein interneurons target dendrites, the soma, and the axon initial segment.⁵² 

The present section has investigated a superconducting optoelectronic neuron receiver circuit utilizing an analog photon-to-fluxon transducer, based on an SPD in parallel with a JJ, that couples flux to a storage loop. The synaptic weight can be enacted by changing the bias to the JJ. One thousand of these synapses can be inductively coupled to an integration loop and ultimately to a thresholding JJ. Designs for single-photon-sensitive receivers capable of operating on rate-coded signals as well as two-photon-sensitive receivers capable of operating on temporally coded signals have been discussed. Excitatory as well as inhibitory behavior has been simulated, and a hierarchy of loops for dendritic processing has been proposed.

An important area of future investigation regards the resilience of the proposed circuits to flux noise. There are several reasons why flux noise is less likely to be problematic in this context than in superconducting digital circuits or superconducting qubits. First, loop neurons are likely to utilize flux-storage loops with large inductance, and thermal current noise scales as $L−1/2$⁠. Second, during a synaptic firing event, tens to hundreds of flux quanta are generated. Therefore, thermal fluctuations that result in the production of order one flux quantum at a synaptic firing junction are of little consequence. This form of noise will lead to a reduction in the resolution of synaptic weights (reduced synaptic bit depth), but will otherwise maintain viability. Third, this form of information processing is classical, so issues related to noise in the phase of the superconducting wave function that are relevant to superconducting qubits are not pertinent to loop neurons. Fourth, many of the loops used in these computational circuits have $L/r$ leak rates by design. Flux that may be trapped in loops during initial cooling will be dissipated rapidly. The synaptic storage loops (to be discussed in Sec. III) are intended to store memories without leak, and, therefore, these loops may be susceptible to unwanted flux trapping. However, even this effect may not be problematic, resulting only in a statistical distribution of initial synaptic weights. The plasticity mechanisms to be discussed next will adapt the network’s synapses to a functional operating point. Nevertheless, these qualitative arguments regarding resilience to noise require more rigorous theoretical and experimental investigation, which will be the subject of future work.

In Sec. I, we argue that cognitive systems benefit from information integration across spatial and temporal scales. Temporal integration is achieved with a power-law distribution of neural oscillation frequencies. The receiver circuits presented in this work enable this functionality in at least two ways. First, they are fast and can detect photon communication events at 20 MHz and possibly faster. The brain oscillates at frequencies from 0.05 Hz to 600 Hz.¹⁷ We assume that loop neurons can oscillate from 1 Hz to 20 MHz, and the actual range may be larger. While the human brain oscillates at frequencies spanning 4 orders of magnitude, these receivers could contribute to oscillations across 7 orders of magnitude or more, indicating potential for information integration across very large networks²⁸ (see Sec. V C 3). The second manner in which these receivers are well suited to achieving a power-law frequency distribution is that their oscillatory response is tunable, so each neuron can participate in a broad range of oscillations. This tunable response is achievable by changing synaptic weights as well as the threshold of the JJ in the NR loop or DR loops via bias currents. Tunability also results from changing which synapses are effective at a given time using inhibition and dendritic processing. Such dynamic effects in synapses and neurons in the brain are crucial for maximally utilizing the time domain for information integration.¹⁸ 

Finally, we point out that while the circuits presented here utilize photons for communication and to trigger synaptic firing events, similar functionality is achievable using only fluxons. The SPD in Fig. 2(b) can be replaced by a JJ. The same techniques of utilizing a hierarchy of integration loops, dendritic processing, and synaptic weighting can be used in those circuits as well. Achieving the communication necessary for large networks¹⁰⁷ will be cumbersome with purely electronic circuits. Yet, such neurons may fire at rates beyond 10 GHz with very low power consumption when driving up to $≈20$ synaptic connections. Networks combining electronic and optoelectronic neurons extend the power-law degree distribution to lower degree and the power-law frequency distribution to higher frequency. Purely electronic, JJ-based neurons and synapses have been proposed^108,116,117 and demonstrated.^118,119 We point out how the circuits presented here can be converted to purely electrical neurons to illustrate the continuity of electronic and photonic implementations and to show that networks with both electrical and optical neurons working in conjunction based on the same neural principles and fabrication process can be achieved.

The synaptic weights between nodes of a neural system are crucial memory elements that affect dynamics and computation.^18,51,80,81 In the loop neurons under consideration, the photon-to-fluxon transduction that occurs during a synaptic firing event is implemented with an SPD in parallel with a JJ, as described in Sec. II. To change the number of fluxons generated during the synaptic firing event, one can simply change the current bias across $Jsf$⁠. The circuits presented in this section are designed to dynamically modify the current bias $Isy$ to $Jsf$ (see Fig. 2). We refer to the circuits that modify $Isy$ as synaptic update circuits.

In general, there will be a chosen weakest synaptic strength and strongest synaptic strength at each synapse, and in general, the weakest synaptic strength may be achieved with $Isymin>0$⁠. Thus, it is the goal of a synaptic update circuit to vary $Isy$ over some range $Isymin≤Isy≤Isymax$⁠. In certain contexts, it is sufficient for $Isy$ to only be able to take two values,¹²⁰ while in other learning environments, it may be advantageous to access many values of $Isy$ between $Isymin$ and $Isymax$⁠. In Sec. II, we identified $Isymin=1μA$ and $Isymax=3μA$⁠.

The circuits described in this section modify $Isy$ in either a supervised manner using JJs or an unsupervised manner using SPDs in conjunction with JJs. For supervised operation, controlled inputs are presented to the system, and the system provides an output. The output from the system is compared to a desired output, and an error is calculated based on a cost function. This error is then used to update the configuration of the system, often through backpropagation.¹²¹ The objective of supervised learning is usually to train the hardware to perform a specific task.¹²² 

For larger neural systems performing general cognitive functions, it is advantageous to operate in an unsupervised manner. Unsupervised learning often refers to the process of learning to categorize unlabeled data. Here, we use the term in a more general sense to refer to systems that learn without any supervisory control. In this modality, no outside entity modifies synaptic weights. Such an approach to learning is scalable in that a user is not required to calculate or adjust the network parameters, so systems with many degrees of freedom can be realized. Unsupervised learning requires that internal activity of the network be capable of adjusting the degrees of freedom to form a useful representation of the information it is expected to process. This operation is achieved through a variety of activity-based plasticity mechanisms, including spike-timing-dependent plasticity (STDP).

For either supervised of unsupervised learning, the memory update signals add or remove flux from a storage loop, which is inductively coupled to $Isy$⁠. This loop is referred to as the synaptic storage (SS) loop, and the flux stored in this loop functions as the memory for the synapse.

For large-scale cognitive computing, we are interested in systems that will interact continuously with their environment, be capable of immediately assimilating new information, and also capable of remembering events as long as possible. Such competing memory demands are sometimes referred to as the adaptability-precision trade-off,⁵⁶ and the best-performing synapses in this regard are complex⁵⁴ and may have many stable levels.⁵⁵ In human subjects, memories have been observed to fade with a power-law temporal dependence.^123,124 It is difficult to do better than power-law forgetting with plastic synapses that continually adapt,⁵⁴ and simple synapses lose their memory trace most quickly.⁵⁵ Here, we show synapses with a number of stable states ranging from two to hundreds. These synapses have dynamically variable memory update rates, making the synapses suitable for power-law memory retention.

The circuits implemented to control $Isy$ must meet several criteria: (1) transition between the minimum and maximum values of $Isy$ should be possible with a specified number of increments to control the learning rate; (2) the circuit should not be able to set $Isy$ outside of this range so that simple update rules or training algorithms do not result in excessively large synaptic weights; (3) it should be possible to cycle the value of $Isy$ from minimum to maximum and back repeatedly without degradation; (4) in addition to a means by which the synaptic weights can be incremented by an external supervisor, there should be a means by which correlated photon signals from the two neurons associated with a synapse can strengthen or weaken the synaptic weight depending on the relative arrival times of the signals from the two neurons; (5) within this unsupervised mode of operation, synaptic update events should be induced by single-photon signals to fully exploit the energy efficiency of superconducting optoelectronic hardware; and (6) the transition probability between synaptic states should also be dynamically adjustable based on photonic signals to achieve metaplastic behavior. This section explores circuit designs satisfying these criteria.

Qualitative explanation of the memory update process is shown in Fig. 8(a) for supervised learning and in Fig. 8(b) for unsupervised learning. For the simplest supervised binary synapse, a flux-quantum memory cell can be used to switch between the strong and weak synaptic states in 50 ps. This binary design can be extended to a multistable synapse that can modify the synaptic weight between the fully potentiated and fully depressed states with hundreds of stable intermediate levels, and implementations with more or less resolution are straightforward to achieve. For unsupervised learning, we consider a circuit that can implement a Hebbian learning rule that potentiates a synaptic connection using one photon from the presynaptic neuron and one photon from the postsynaptic neuron. We generalize this circuit to implement full STDP wherein a synaptic weight can be either potentiated or depressed based on timing correlations. This STDP circuit uses single-photon signals at four ports. Implementations of short-term plasticity, homeostatic plasticity, and metaplasticity are also possible. By combining these synaptic update circuits, it is possible to realize neurons with a distribution of synapses that update at different rates as well as ensembles of neurons wherein different neurons store information about different stimuli learned at different times, thus achieving a network with rapid adaptability and long memory retention times necessary for cognition.

At the present stage of development, it is not clear which application spaces will be best served by superconducting optoelectronic hardware. The main emphasis of this work is on general cognitive systems, yet we begin the exploration of synaptic plasticity with supervised synapses to explore the possibilities and because the unsupervised circuits are straightforward extensions of these supervised circuits. To implement supervised learning, we would like to control the flux stored in the SS loop using simple control signals, which we take to be square current pulses. For many applications in machine learning, neural networks, and neuroscience, synapses are treated as binary elements that can switch between strong (potentiated) and weak (depressed) states.^55,120,125 In Sec. II, it was shown that in a superconducting optoelectronic loop neuron, changing $Isy$ from $1μA$ to $3μA$ changes the contribution to the neuron’s integrated signal by a factor of 15. The circuit for enacting a binary synapse is shown in Fig. 9. For systems with many neurons each with many synapses, we would like to use a single current source to establish the baseline synaptic bias to all synapses (⁠$I1$ in Fig. 9), keeping in mind that we may need the baseline synaptic bias to be different for different synapses. This can be achieved by using a single current bias, $I1$⁠, and using mutual inductors to couple this current to each synapse. The synaptic firing circuit is thus biased by a superconducting loop, referred to as the synaptic bias (SB) loop, and the objective of the synaptic update circuit is to change the current in the SB loop, also through mutual inductors. This concept is shown in Fig. 9, where the SB loop is coupled to both the main bias, $I1$⁠, and the dynamic synaptic bias based on the flux trapped in the SS loop. All circuits presented in the remainder of this section provide a means to adjust the flux stored in the SS loop.

The two-JJ circuit of Fig. 9 is a standard flux-quantum memory cell^65,66 coupled to the SB loop via a mutual inductor.⁸⁴ When there are no fluxons in the SS loop, $Isy=1μA$⁠, the minimum value. In this state, the bias currents (⁠$Issb1$ and $Issb2$⁠) are chosen such that a weakening synaptic update signal (⁠$I−$⁠) cannot add a fluxon to the loop, so the synaptic weight cannot be further depressed. A strengthening signal can, however, switch $Jsu+$ and add one fluxon to the loop. This transitions the circuit to the potentiated state, wherein $Isy=3μA$⁠. At this point, further potentiating signals cannot add additional flux to the loop. The loop can store only a single fluxon, and it is characterized by $βL/2π=LIc/Φ0=1.8$⁠.^65,66 The junction and circuit parameters are given in  Appendix A. These parameters are typical for superconducting electronic circuits and straightforward to realize in hardware.

Figure 10 shows WRSpice simulations of the temporal behavior of the circuit as it switches between states. In Fig. 10(a), the circuit is initially in the depressed state. A pulse of $10μA$ drives the circuit to the potentiated state. Repeated current pulses do not switch the state, and after the input pulses cease, the cell holds the value of $Isy$⁠. Upon the application of a single $10μA$ pulse into the weakening port (⁠$Issb2$⁠), the circuit switches back to the depressed state, and repeated applications of this signal do not further switch the circuit.

In Fig. 10(b), we show the synapse switching between the depressed and potentiated states every 50 ps. The time scale of Fig. 10 is extremely fast compared to biological neural circuits. The speed of these circuits offers intriguing possibilities. Figure 10(c) shows a temporal zoom of a full cycle of the binary synapse occurring within 50 ps. The operation considered in Fig. 10 is intended to show the operating range of the synapse, but in practice repeated switching in this manner is unlikely to be useful for neural operation.

For deep learning in neural networks, it can be advantageous to increment the synaptic weights in small steps. To achieve fine weight update, a superconducting loop capable of storing more than one flux quantum is utilized, as shown in Fig. 11. Flux quanta can be added one by one using DC-to-SFQ converters.^65,66 The binary synapse has been modified to include two DC-to-SFQ converters: one for potentiating and one for depressing. When a fluxon is produced by the potentiating DC-to-SFQ converter by the introduction of a current pulse, $I+$⁠, the fluxon is added to the SS loop. When a fluxon is produced by the depressing DC-to-SFQ converter by the introduction of a current pulse, $I−$⁠, the fluxon counter propagates in the SS loop. The inductors of the SS loop, $Lss$ and $Mss$⁠, can be chosen over a broad range of values to determine the learning rate and range of synaptic weights achieved.

Controlled increase of synaptic bias current is again demonstrated using WRSpice. The results are shown in Fig. 12. In this calculation, a periodic square wave drives the DC-to-SFQ converter with $10μA$ pulses of 1 ns duration and 2 ns period. Current is added to the SS loop in fluxon increments over many input cycles [Fig. 12(a)]. In this case, the value of $Isy$ before any flux has been added to the SS loop is $2μA$⁠, chosen to be in the middle of the operational range identified in Sec. II. For this calculation, the inductance of the SS loop is 200 nH (⁠$βL/2π=LIc/Φ0=3.8×103$⁠), leading to the addition of 2.5 nA to $Isy$ with the addition of each fluxon to the loop. This value of inductance (and, therefore, $ΔIsy$⁠) can be chosen over a broad range to set the synaptic update increment and number of synaptic levels. This value was chosen to create a SS loop that can store over 1000 fluxons between the minimum and maximum values of $Isy$⁠.

The inset of Fig. 12(a) shows the behavior of $Isy$ as a function of time as it is potentiated to saturation. A fluxon is added to the loop every 2 ns. After approximately 500 fluxons have been added to the loop, the value of $Isy$ saturates just above $3μA$⁠. This saturation behavior is advantageous so that a learning algorithm cannot cause a synaptic weight to grow without bound.

Figure 12(b) shows $Isy$ as a function of time as the potentiating and depressing DC-to-SFQ converters are alternately employed, analogous to the two drives of the binary synapse in Fig. 9. For these calculations, an SS loop with 20 nH inductance was considered to reduce the time required to achieve saturation. Initially, $Isy=2μA$⁠. Fluxons are added to the SS loop for 200 ns, and $Isy$ reaches its maximum value of $3.2μA$⁠. Once the SS loop reaches saturation, the value of $Isy$ cannot be increased. The figure further shows that after the synaptic strengthening drive is turned off, $Isy$ maintains its value (i.e., during the time from 200 ns to 250 ns), a feature enabled by the use of dissipationless superconducting circuits. After 250 ns, fluxons of the opposite sign begin to be added to the SS loop via the synaptic weakening drive (⁠$I−$⁠), and $Isy$ can be driven down to the minimum value (800 nA in this case). Cycling these drives results in the periodic behavior seen in Fig. 12(b). During each strengthening and weakening cycle, $Isy$ vs time has two regions with different slopes. This is because when the current in the SS loop is outside a certain range, the DC-to-SFQ converter releases two fluxons per drive cycle. This characteristic is likely of little consequence and may be eliminated with improved circuit design, possibly by separating the DC-to-SFQ converter from the SS loop with a JTL. The numerical simulation of the circuits through periodic cycling (Figs. 10 and 12) is intended to demonstrate the range of synaptic states, the transitions between them, and saturation behavior. In practice, the synapses are unlikely to be cycled in this manner and will instead be updated as needed by the learning algorithm.

The circuits of Figs. 9 and 11 have several strengths when used to establish the synaptic weight of a superconducting optoelectronic neuron. The nature of the flux-storage Josephson circuits enables modifying the synaptic weights as many times as necessary without material degradation. The maximum and minimum values of $Isy$ can be designed to achieve a broad range of operating conditions. Upon reaching the maximum and minimum values, the device saturates, eliminating the possibility of runaway values of synaptic weight. Synaptic update can be carried out in a specified number of increments based on the choice of inductance of the SS loop. The size of these increments will contribute to the learning/forgetting rate of the synapse.

While these characteristics of the circuits are conducive to implementing a variety of training algorithms based on back propagation,¹²¹ we would also like to enable systems that learn using only activity within the network. We next consider a Hebbian learning circuit, which strengthens the synaptic weight between two neurons that fire in succession. This will lead to the discussion of a circuit achieving STDP based on the timing between pre- and postsynaptic activity.

The Hebbian update circuit under consideration is shown in Fig. 13(a). The operation of this circuit is based on a similar principle to the supervised learning circuits discussed in Sec. III A in that the synaptic bias current $Isy$ is adjusted based on the flux stored in the SS loop. The DC-to-SFQ converter of Fig. 11 can be replaced by SPDs to enable flux to be added to the SS loop based on temporally correlated photonic activity within the network. The circuit of Fig. 13(a) implements a Hebbian update rule that potentiates a synaptic connection between pre- and postsynaptic neurons when the presynaptic neuron contributes to the firing of the postsynaptic neuron.⁴¹ 

The Hebbian rule requires a two-photon temporal-correlation circuit, like the temporal-code receiver of Sec. II, except the asymmetry of Hebbian update requires an asymmetrical initial bias to the two SPDs. Operation of the Hebbian update circuit can be described qualitatively as follows. When no photons have been detected, the bias $Ispd$ is directed through $SPD1$⁠. The resistor $r1$ ensures that $SPD2$ is unbiased until $SPD1$ receives a photon, and, therefore, photons incident on $SPD2$ have no effect on the circuit unless they are incident during a time window following a detection event by $SPD1$⁠. Once a photon has been detected by $SPD1$⁠, $Ispd$ is redirected to $I2$ and $I3$⁠. The current returns to $I1$ with a time constant of $τ1=L1/r1$⁠. If a photon is detected by $SPD2$ during $τ1$⁠, $Ispd$ is predominantly redirected to $I3$⁠, which can be sufficient to switch $Jsu$⁠, the synaptic update JJ, perhaps many times depending on the bias currents, $Ispd$ and $Isu$⁠, and the difference in arrival times between the two photons, $Δt$⁠. Details of circuit design are included in  Appendix A.

In Fig. 13(b), we analyze the current added to the SS loop as a function of the delay, $Δt$⁠, for four values of $Isu$ with $Ispd$ fixed at $10μA$⁠. We plot the change in current in the SS loop (⁠$ΔIss$⁠) as a percentage of the SS loop saturation current (⁠$Isssat$⁠) during Hebbian update events characterized by delay $Δt$⁠. The amount of synaptic weight modification depends strongly on the temporal delay, dropping to zero after roughly $τ1$ (50 ns in this case). We also see that the effect depends on $Isu$⁠, enabling the memory update rate to be dynamically adjusted during operation via a DC bias current. This dependence on $Isu$ provides a means to implement metaplasticity. The quantity $ΔIss/Isssat$ represents the fraction of the synapse dynamic range that is acquired in an update event. Although the current in the SS loop (and, therefore, $Isy$⁠) can only change by an integer number of flux quanta, the use of high-kinetic-inductance flux-storage loops wherein thousands of flux quanta can be stored makes this effectively an analog circuit. For the SS loop investigated in Fig. 13(a), $βL/2π=1.9×104$⁠.

During circuit operation, we assume that when the presynaptic neuron fires a photonic pulse, one or more photons will reach a synaptic firing circuit of the postsynaptic neuron and bring the neuron closer to its threshold, as discussed in Sec. II. We also assume that additional photons have a probability of reaching SPD$1$ of the synaptic update circuit shown in Fig. 13(a) to perform the first step in implementing the Hebbian rule. This photon is labeled “1” in Fig. 13(a). The probability of reaching $SPD1$ may be controlled to modify the learning rate. Similarly, it is assumed that during a neuronal firing event, the local neuron will send photons not only to its downstream connections but also to its local synaptic update circuits to activate learning by striking $SPD2$⁠. This photon is labeled “2” in Fig. 13(a). This self-feedback is also illustrated in Fig. 1.

Hebbian learning rules may be based on average firing rates of pre- and postsynaptic neurons or on timing between individual spikes from these neurons.³⁹ Here, we consider the latter. A timing-dependent learning rule often takes the form of exponential decay as a function of the difference in arrival times of pre- and postsynaptic signals. The form shown in Fig. 13(b) is slightly different due to Josephson nonlinearities. This modified temporal dependence is likely of little consequence as it maintains the principal function of timing-dependent plasticity, which is to modify the synaptic weight based on temporal correlation within a specified time window surrounding a neuronal firing event.

While the quantity $ΔIss$ represents the change in synaptic weight due to one Hebbian update event, the area under the curves in Fig. 13(b) will be related to the learning rate when averaged over many events, because the delay between the two photons, $Δt$⁠, will vary across events. The integral of the curve with $Isu=35μA$ is 3.6% of the integral of the curve with $Isu=38μA$⁠. For $Isu=36μA$⁠, the value is 18%, and for $Isu=37μA$⁠, the value is 48%. The learning rate can be dynamically adjusted across a broad range via $Isu$⁠.

Learning rules that can both strengthen and weaken the synaptic connection are required for neural computing. Spike-timing-dependent plasticity requires the Hebbian potentiating operation described in Sec. III B and also a depressing operation wherein a neuronal firing event at the postsynaptic neuron followed closely by a neuronal firing event at a presynaptic neuron depresses the synaptic weight between the two neurons. A circuit capable of producing this STDP is depicted in Fig. 14(a). The full circuit with the STDP module delivering $Isy$ to $Jsf$ is shown in Fig. 23. Much as strengthening and weakening were accomplished in Sec. III A by adding a mirror image of the strengthening circuit to the SS loop, here we duplicate the Hebbian circuit of Sec. III B to achieve STDP. The similarity of the SPD circuit of Fig. 14(a) and the JJ circuit of Fig. 11 is apparent. In Fig. 14(a), each SPD is assumed to be connected to a different photonic port. Two of the ports receive photons from the presynaptic neuron, and two of the ports receive photons from the postsynaptic neuron. In this circuit, photons coming from the presynaptic neuron are drawn coming from the left, and photons from the postsynaptic neuron are drawn coming from the right.

The symmetry between the strengthening and weakening receiver circuits in the STDP circuit of Fig. 14(a) is broken based on whether the SPD that is biased in the steady state receives photons from the presynaptic or postsynaptic neuron. In the synaptic-weakening receiver circuit, a postsynaptic photon detected by $SPD3$ followed by a photon from a presynaptic neuron detected by $SPD4$ introduces counter-circulating flux to the SS loop. The time constants and biases of the strengthening and weakening receivers can be adjusted independently.

To demonstrate the feasibility of implementing STDP, Fig. 14(b) shows a plot of the change in current in the SS loop vs the relative arrival time of photons at the pre- and postsynaptic detectors as calculated with WRSpice, again modeling photon-detection events as transient resistance pulses. The time delay, $Δt$⁠, is defined as the time of arrival of the postsynaptic photon minus the time of arrival of the presynaptic photon. The upper right quadrant is essentially the same as the Hebbian behavior discussed in Sec. III B. When $Δt$ becomes negative, the upper portion of the circuit makes no modification to the current in the SS loop. The lower portion of the circuit is nearly identical to the upper portion, except that the pre- and postsynaptic photons are routed to the opposite SPDs, and current added to the SS loop by the lower portion circulates in the opposite direction as when added by the upper portion of the circuit. Thus, the lower portion of the circuit only adds flux to the SS loop when the postsynaptic photon arrives before the presynaptic neuron, and in this event, the synaptic weight is weakened. In both the potentiating and depressing cases, this model indicates the synaptic update abruptly drops to zero when the photon arrival times are in the reverse order. In practice, this effect would be smeared out by the timing jitter of the light sources and detectors, and the synaptic update represented in Fig. 14(b) would be convoluted with the source and detector jitter when averaged over many firing events.

To gain intuition regarding the dynamical operation of the STDP circuit, Figs. 14(c) and 14(d) illustrate the circuit in operation, as simulated with WRSpice. Two synaptic strengthening events and two synaptic-weakening events occur. The currents associated with synaptic strengthening and weakening, $I+$ and $I−$⁠, are shown in Fig. 14(c) with colors related to the currents labeled in Fig. 14(a). $Isy$ delivered to $Jsf$ is shown in Fig. 14(d). A synaptic strengthening event occurs with $Δt=20ns$⁠, followed by a weakening event with $Δt=10ns$ and another with $Δt=25ns$⁠. A final strengthening event occurs with $Δt=5ns$⁠. The synaptic bias current, $Isy$⁠, is observed to respond as expected based on the Hebbian analysis in Sec. III B. In this calculation, $Lss=20$ nH, and we mention again that the amount of current added to $Iss$ and, therefore, $Isy$ during a synaptic update event can be scaled with $Lss$ in hardware and with $Isu$ dynamically. The memory update rate of the STDP synapse can be controlled by adjusting the frequency of photon absorption events.

While crucial to learning and the interplay between the structure and function of neural systems, STDP is only one of many synaptic plasticity mechanisms. Despite their significance, we do not discuss short-term plasticity, homeostatic plasticity, or metaplasticity here. Further investigation of these circuits will be the subject of future work.

This section has explored synaptic update circuits capable of delivering a variable synaptic bias current to the synaptic firing circuits presented in Sec. II. Manipulation of the synaptic weight through external input of square wave pulses and via photon-detection events has been simulated.

For STDP, the synaptic update circuits described here provide ports for four photons: one strengthening photon from both the presynaptic and postsynaptic neuron, and one weakening photon from both the presynaptic and postsynaptic neuron. For a single synaptic strengthening or weakening event, two of these photons must be present. When optically implementing a synaptic update rule based on timing correlation, it is difficult to achieve a circuit requiring fewer than two photons.

Other forms of photonic synapses have recently been developed and offer utility in multiple neural contexts.^126–131 One can leverage phase shifts in microrings^127,128 or Mach-Zehnder interferometers (MZIs)¹²⁹ to adjust synaptic weight. Thermal tuning is often employed to implement the phase shifts. Thermal tuning requires more power than is suitable for this hardware platform. Phase shifters may also be large if MZIs are used, and phase shifters may require exotic materials that limit scaling if electro-optic effects are leveraged. If different synapses are addressed with different frequencies of light, the out-degree of a node in the network is limited by the multiplexed channel spacing. Approaches using MZIs for weighting and routing have the disadvantage that STDP cannot be implemented, because modifying a single phase shifter in the network affects many synaptic weights. One approach to synaptic weighting in the photonic domain utilizes a variable optical attenuator at each synaptic connection. Phase-change materials have been employed as such variable attenuators,¹³⁰ and the absorption of phase-change materials can be affected with pulses of light, thus introducing a Hebbian-type synaptic weight update process. While such an approach may be useful for certain types of neural circuits, update of these synapses requires too many photons to be useful for the neural computing scheme developed here (billions of photons per update operation for phase change vs single photons for superconducting optoelectronics). Further, making use of the arrival times is difficult with phase-change materials. It remains to be seen if other synaptic operations such as short-term plasticity, homeostatic plasticity, and metaplasticity can be achieved with phase-change materials.

In general, synaptic weights that attenuate a signal in the optical domain require more light from neuronal firing events, and many photons are simply absorbed at weak synapses. By contrast, using photons for communication but weighting in the superconducting domain uses fluxons to change the synaptic weight, and they can be generated with orders of magnitude less energy than photons. While all of these approaches to synaptic weighting may be useful in different contexts, we have developed the synapses presented in this work based on simultaneous considerations of power, complexity, scalability, speed, and size in the context of the superconducting optoelectronic hardware platform.

An important weakness of the synapses presented here is they lose all memory when superconductivity is broken. The neuromorphic system must remain below $Tc$ to preserve what has been learned. This class of Frosty the Snowman memory may be augmented by devices that can be heated, such as magnetic Josephson junctions.^117,119,132 It would be appealing if the state of memory in the plastic synapses described here could be transferred to long-term magnetic memory, perhaps during a sleep phase.

Another potential challenge for this type of loop neuron memory is flux trapping. The SI loops discussed in Sec. II are likely to include resistors to give a leak rate. Trapped flux in those loops will be less problematic. The SS loops that set the synaptic weights are intended to store flux for a long time to maintain memory, so they will not include resistors. Trapped flux will produce variations in the initial synaptic weights across an ensemble. For binary synapses, this will result in some synapses being initialized with strong synaptic weight and some with weak. For SS loops with high inductance, stray flux will induce a small current, so the perturbation may be small relative to the dynamic range of the synapse. For large ensembles of synapses, the statistical variation may be tolerable or even advantageous. If flux proves problematic, techniques used to shield superconducting qubits can be employed.¹³³ 

In Sec. I, we argue that a dynamical system capable of differentiated processing and information integration across spatial and temporal scales underlies cognition. In Sec. II, we introduced the relaxation oscillators and dendritic processing loops capable of implementing the temporal synchronization operations necessary for integrating information in time. Network synchronization and synaptic plasticity are mutually constructive phenomena, in that synaptic strengthening through spike timing is more likely to occur when the firing of two neurons is correlated, and the strengthened synapses, in turn, make the correlated neurons more likely to synchronize. Networks with small-world structure^13,24 and dynamics characterized by self-organized criticality are crucial to achieving information integration. Hebbian learning rules and STDP have been shown to convert random networks into small-world networks and to give rise to self-organized criticality.^34,51 Creation of hardware capable of supporting complex networks and synaptic learning mechanisms will provide a powerful tool for the investigation of the relation between critical network dynamics and cognitive function. We have shown some of the complex synaptic behaviors necessary for rapid adaptation, long-term memory retention, and synaptic update based on network activity. Networks of neurons connected by these synapses will be capable of integrating information learned at many times in many contexts in a single dynamical state.

Synaptic receivers must partner with a light source to generate a neuronal firing event when the integrated current reaches a threshold. In Sec. II, we discuss how a JJ could be used as a thresholding element. In this section, we show that the flux quantum generated by a thresholding JJ can trigger an amplification sequence resulting in an optical pulse containing 1–100 000 photons. These superconductor/semiconductor hybrid circuits achieve electrical-to-optical transduction and facilitate communication with high fan-out and light-speed delays in complex networks of superconducting optoelectronic neurons. We refer to these amplifier circuits as the transmitter of the neuron.

A central technical challenge in designing superconducting optoelectronic hardware is to produce optical signals at telecommunication wavelengths with superconducting electronic circuits. The superconducting energy gap⁶⁴ is in the millivolt range, making it difficult for superconducting circuits to produce the one volt needed to appreciably alter the carrier concentrations in semiconductor electronic and optoelectronic devices. This voltage mismatch makes it difficult for superconducting electronic circuits to interface with CMOS logic⁶⁶ and memory.¹³⁴ 

A common approach to increase voltage in superconducting circuits is to place JJs in series.¹³⁵ The achievable voltage scales as the superconducting energy gap multiplied by the number of junctions. Order of one thousand junctions must be utilized to drive the light sources we intend to employ.^1,63 While superconducting circuits operate at low voltage, they can sustain large current. Supercurrent can be converted to voltage with a resistor. A microamp across a megaohm produces a volt. A small meandering wire of a superconducting thin film can easily produce a megaohm resistance in the normal-metal state. Thus, we can convert a current-biased superconducting wire into a voltage source by switching the wire between the superconducting and normal states.

Such a voltage source is not commonly used in superconducting electronics because it tends to be slow and consume more energy per operation than a JJ. The advantages of superconducting electronics for digital computing are largely speed and efficiency, while the advantages of superconducting optoelectronic networks are largely communication and efficiency. While superconducting electronics aspire to operate above 100 GHz, superconducting optoelectronic networks comprising neurons firing up to 20 MHz would be a radical increase relative to the maximum frequency of 600 Hz in biological neural systems.^17,18,28 The goal of neural rather than digital computing liberates us to use superconducting devices slower than JJs for events that only occur once per neuronal firing. The speed and efficiency of JJs are still leveraged by loop neurons to distinguish synaptic efficacy during each synaptic firing event. Thus, we can use a switching element leveraging the superconductor-to-normal phase transition in a neural context, provided it operates every neuronal firing event and not every synaptic firing event.

An effective means of breaking the superconducting phase is to heat the wire locally. Thermal devices are generally slow and power hungry, but the small volume, small temperature change, and small heat capacity at low temperature^136,137 enable switching times on the order of a nanosecond with femtojoules of energy. While such an amplifier is not suitable for the high speed and low power of flux-quantum logic,^96–98,138 a single firing of the switch can produce thousands of photons, making it very useful and efficient in this neural context where each synapse can be activated by a single photon.

This high-impedance, phase-change switch is called an hTron.⁶⁹ The heating operation required to switch the hTron from the superconducting to metal state can be achieved through dissipation in a Joule heater. Fairly large current is required to provide sufficient power. While the hTron is equipped to deliver voltage to drive the semiconductor light source, the thresholding JJ will provide only fluxons when the neuron’s threshold is reached. These fluxons are insufficient to thermally switch the state of the hTron. An intermediate current amplifier is required to convert fluxons from the thresholding JJ into current across the joule heating element of the hTron. For this step of the amplification process, an nTron⁶⁷ will suffice. The nTron is a three-terminal thin-film superconducting current amplifier. A small current in the constricted gate can exceed the local critical current and drive the path from source to drain normal. An impedance on the order of a kilohm can be produced quickly, and the current from the source to drain will be diverted to a load. In the present case, that load is the $≈10Ω$ resistive element of the hTron.

A summary of the circuit operation is shown in Fig. 15. The schematic and circuit diagram are shown in Fig. 15(a), and the sequence of events in the operation of the transmitter is shown in Fig. 15(b). The NT loop described in Sec. II reaches threshold due to integrated current from synaptic firing events, and the thresholding JJ produces one or more fluxons. These fluxons enter the gate of the nTron, exceeding the gate critical current. The nTron source/drain current is then diverted to the hTron gate. Joule heating in the hTron gate produces a temperature shift of several kelvins, switching the hTron to the high-impedance state. The hTron source-drain current suddenly experiences $1MΩ$⁠, and the current rapidly switches to first charge the LED capacitor, and then, once sufficient voltage is achieved across the capacitor, current is driven through the diode. This current generates photons through electron-hole recombination. These photons are the optical source for neural communication.

This amplifier circuit is relatively complex and uses the most power of any part of the neural circuit. A more elegant solution may be possible. Any solution must meet several operating criteria: (1) the transmitter must threshold on a low-current signal from the NT loop; (2) the amplifier chain must convert this signal to the voltage necessary to produce light from a semiconductor diode; (3) the operation should happen at least as fast as the recovery of the single-photon detectors in the loop neuron synapses (a few tens of nanoseconds); (4) a number of photons appropriate to communicate with the neuron’s synaptic connections must be produced; (5) the number of photons created must be dynamically variable with a bias current; (6) the energy of a firing event must be low enough that an ensemble of neurons in realistic network operation have power density low enough for heat to be removed by liquid helium; and (7) total power consumption must be low enough to enable scaling to neural systems with billions of interacting nodes. The transmitter circuits presented here satisfy these criteria. We begin with the design of the hTron driving the LED and work backward through the circuit of Fig. 15(a).

We must ensure that the voltage required to drive the LED can be sustained for a duration commensurate with the number of photons required. This duration will depend on the drive current, the capacitance of the LED, the efficiency of the LED, and the number of synaptic connections served by the neuron. Once the drive requirements of the LED are understood, we can proceed to design an hTron that can meet these drive requirements.

The LED circuit under consideration is shown in Fig. 16. The LED is modeled as a variable resistor in parallel to a capacitor. The variable resistor is modeled with the DC $I−V$ characteristic of a $p−n$ junction, as described in  Appendix A. The hTron is modeled as a variable resistor in series with an inductor. This variable resistor is treated as a step function with zero resistance abruptly switching to $800kΩ$⁠. This model is intended to capture the behavior of the hTron driving the LED as the superconducting channel of the hTron is driven above its transition temperature. A thermal model of the hTron is presented in Sec. IV B.

The equations of motion for the circuit of Fig. 16 are given in  Appendix A. Solving these equations, we obtain the circuit currents and voltages as a function of time. From these quantities, we can determine the energy dissipated during a firing event as well as the number of photons produced. The number of photons produced is calculated as

where $ηqe$ is the quantum efficiency of the diode and $e$ is the electron charge. The efficiency of the circuit of Fig. 16 is calculated as $ηRC=hνNph/ERC$⁠, where $h$ is Planck’s constant, $ν$ is the frequency of a photon (taken to be $c/1.22μm$⁶³), and $ERC$ is the total energy dissipated by the $RC$ circuit of Fig. 16 during a firing event as calculated with the model given in  Appendix A. In calculating $ηRC$⁠, we use Eq. (1) with $ηqe=1$⁠.

At least two other factors will contribute to the efficiency of the circuit in Fig. 16. First, carriers injected into the $p−n$ junction may recombine nonradiatively. This loss mechanism is captured in the internal quantum efficiency, $ηqe$⁠. Second, light generated by electron-hole recombination events may not couple to the guided mode of the axonal waveguide and will, therefore, not couple to the synaptic terminals. This loss mechanism is captured in the waveguide coupling efficiency, $ηwg$⁠. The total LED efficiency is given by $ηLED=ηRCηqeηwg$⁠.

Circuit performance is shown in Fig. 17. Voltage transients across the $p−n$ junction are shown in Fig. 17(a), where two values of capacitance and two values of quantum efficiency are considered. For each of the four traces, the hTron pulse duration was chosen to produce 10 000 photons. We assume that 10 photons are generated per out-directed synaptic connection to compensate for loss, reduce noise, and implement learning functions. Thus, these voltage pulses are appropriate to neurons with out-degree of 1000. If the LED capacitance can be made as low as 10 fF, and $ηqe$ can be made as high as 0.1, the hTron gate must only be normal for 2.9 ns. Under these operating conditions, 25 fJ of energy is dissipated, of which 64% is dissipated as current through the $p−n$ junction (⁠$ηRC=0.64$⁠). If the LED performance is worse, with $C=100fF$ and $ηqe=0.01$⁠, the drive must be applied for 29 ns. This operation dissipates 251 fJ of energy, also with 64% through the junction.

General trends for the number of photons produced by the circuit as a function of the time the hTron gate is above $Tc$ are shown in Fig. 17(b) for several values of capacitance and quantum efficiency. In these calculations, the bias current (⁠$ILED$⁠) is fixed at $10μA$⁠. The capacitance determines the minimum hTron pulse duration necessary to achieve the voltage for photon production, and the quantum efficiency determines the slope (⁠$y$-intercept of this log-log plot) for longer hTron pulses.

As implied by the reach drive current depicted in Fig. 1, we would like a means to dynamically control the number of photons produced in a firing event. We can achieve this by varying the bias current diverted to the LED when the channel of the hTron becomes resistive, $ILED$⁠. In Fig. 17(c), we show $Nph$ as a function of $ILED$ for various values of the LED capacitance in a case where the hTron channel is driven normal for 10 ns and the LED quantum efficiency is assumed to be 0.01.⁷⁰ This current bias provides a means to change the strength of neuronal activity. With fewer photons produced, the probability of reaching distant connections diminishes. With more photons produced, the neuron makes a stronger contribution to network activity. The synapses considered in this work do not decode the amplitude of the photonic signal, so the objective of changing the number of photons produced in a neuronal firing event is not to encode information, but rather to adjust how many synaptic connections are reached. The routing architecture can be designed so that with a given value of $ILED$ some synapses receive 10 photons on average from a synaptic firing event, while others receive only one. By decreasing $ILED$⁠, the strongest synapses will still receive more than one photon, while the weakest will receive less than one and are effectively eliminated. Thus, $ILED$ provides an additional means to adapt the structural network into multiple functional networks at different times. This current bias may be modified by a supervisory user or by internal activity within the network.

The efficiency of the light-production circuit is considered with the rest of the transmitter circuit in Sec. IV D. Based on the calculations of this section, we know the hTron drive requirements for light production across a range of capacitance and quantum efficiency values. If a neuron needs to produce 10 000 photons to communicate to 1000 synaptic connections, an hTron biased with a channel current of $10μA$ must produce a resistance of $800kΩ$ for 1 ns–100 ns, depending on the achievable LED performance. We now proceed to consider the operation of an hTron when driven by the current from an nTron.

To produce the voltage across the LED required to generate light, a resistance of $800kΩ$ must be established rapidly and sustained for 1 ns–100 ns. One way to achieve this is to switch a length of superconducting wire to the normal-metal state. This can be straightforwardly accomplished by raising the temperature of a superconducting wire above $Tc$⁠. An hTron is a device that switches a channel resistance from zero ohms to a large value when current is driven through the gate.⁶⁹ The current through the gate dissipates power in a resistive element through joule heating, and this power locally raises the channel above $Tc$⁠. We show a schematic in Fig. 18(a), wherein a resistive layer is separated from a nanowire meander by a thin insulator.

While thermal devices can be too slow and consume too much power for some applications, there are several reasons why the hTron is suitable for the present purpose. First, the device has a compact footprint of $5×5μm2$⁠, so a very small mass must be heated. Second, the specific heat of all materials involved falls as $T3$⁠, so at the desired operating temperature of 4.2 K, the specific heat is orders of magnitude smaller than at room temperature. Third, the required temperature swing is small (⁠$≈2K$⁠). These factors taken together make the hTron a suitable device to achieve the voltage necessary to produce light from a semiconductor diode with the power and speed required for the neural application under consideration.

To quantify the performance of the hTron when driving the LED of Sec. IV A, we consider the transient dynamics of the thermal circuit shown in Fig. 18(b). A heat source $Q$ is delivered to the stack of materials shown in Fig. 18(c). The equations of motion and material parameters used in these calculations are given in  Appendix A. Figure 19(a) shows temperature transients of the superconducting layer when power is delivered to the hTron gate long enough to drive the hTron channel normal for 1 ns and for 10 ns. In this plot, the hTron gate is driven with square current pulses to illustrate the temporal dynamics of the thermal components. In this model, the hTron can switch to the resistive state in roughly 1 ns. While this time scale is not suitable for many operations in superconducting digital electronics, it is more that fast enough for a neuronal firing event in the system under consideration.

While a square pulse is most efficient for driving the hTron, exponentially rising and decaying pulses will be generated by the nTron.⁶⁷ The nTron is a three-terminal, thin-film device. In the off state, a supercurrent flows from the source to drain, and the gate is in the superconducting state. The gate comprises a small constriction, and when the current delivered to the gate exceeds the critical current, it is driven locally to the normal state. Joule heating spreads the normal domain and quickly causes the channel between the source and drain to be driven normal across the entire wire width. This normal domain provides a few squares of resistance (roughly $1kΩ$⁠), at which point the source-drain current is diverted to a load. In the present case, the load is the gate of the hTron [$10Ω$ in this study, the resistance of the upper layer in Fig. 18]. When the gate current to the nTron ceases and the channel returns to the superconducting state, the channel current returns with the $L/r$ time constant of the system. Thus, the current pulse from the nTron to the hTron will have an exponential time dependence.

In Fig. 19(b), we show the temporal response of the hTron channel temperature when the gate is driven by an exponential current pulse of 1.2 mA amplitude from an nTron. In this case, the rise time of the pulse is 300 ps, and the fall time is 30 ns. These time constants are controlled by the $L/r$ time constants of the circuit. The fall time is set by $LnT/rnT$⁠, where $LnT$ is the inductance of the nTron channel and $rnT$ is the load of the nTron, which in this case is the gate resistance of the hTron. To achieve the power necessary to switch the hTron, 1.2 mA from the nTron is required across the $10Ω$ of the hTron gate.

Driving the hTron with the exponential pulses of the nTron is far less efficient than driving with square pulses, because power continues to be dissipated in the exponential tail of the current pulse long after the temperature of the hTron channel drops back below $Tc$⁠. In the case considered in Fig. 19(b), the $LnT/rnT$ time constant is 30 ns, and the hTron channel is held above $Tc$ for 4.7 ns. A square pulse of 6 ns would achieve the same duration of the hTron in the resistive state. Figure 20(a) illustrates this inefficiency. The required $LnT/rnT$ time constant is plotted as a function of the time the hTron channel must be held above $Tc$⁠, referred to as $thot$⁠. The time $thot$ depends on the LED capacitance, efficiency, and the number of photons produced during the pulse, which is determined by the number of synapses formed by the neuron. The $LnT/rnT$ time constant must be nearly ten times $thot$⁠. Improved drive circuit designs are likely possible, but we proceed with the single-nTron example to illustrate that even with first-generation circuit designs, sufficient efficiency can be achieved.

We wish to connect the number of photons produced in a neuronal firing event to the $τnT$ time constant that must be implemented in hardware. In Sec. V, we study networks with neurons making 20–1000 synaptic connections. We would like neuronal firing events to produce ten times as many photons as the neuron’s out-degree to compensate for loss, reduce noise, and perform memory update operations. We are, therefore, interested primarily in neuronal firing events producing 200–10 000 photons, and large hub neurons may need to produce 100 000 photons or more. Such photon numbers will require the hTron channel to be driven normal for some duration, which necessitates current drive from the nTron to the hTron gate for some proportional duration [Fig. 20(a)]. We, therefore, must calculate the number of photons produced by the LED as a function of the $τnT=LnT/rnT$ time constant, taking the LED capacitance and efficiency into account. The results of these calculations are shown in Fig. 20(b). To produce 200 photons from an LED with 10 fF capacitance and 1% efficiency, $τnT$ must be 8 ns, and to produce 10 000 photons $τnT$ must be 100 ns. An nTron channel inductor achieving this time constant and carrying the requisite 1.2 mA necessary to drive the hTron gate can be achieved in an area commensurate with the area required for the synaptic wiring and routing waveguides comprising the dendritic and axonal arbors of the loop neurons.

The next task is to show a JJ in the NT loop delivering the current to switch the gate of the nTron.

The circuit considered for detecting threshold in the NT loop is shown in Fig. 15(a). The parameters are given in  Appendix A. When the current in the NT loop reaches the switching current of the thresholding junction, $Jth$⁠, that junction will transmit a fluxon to the relaxation oscillator junction, $Jro$⁠. A relaxation oscillator junction has the property that, upon switching, it temporarily enters a latched state. In the latched state, the junction is resistive, and the bias current is diverted to a load. A relaxation oscillator junction can be physically implemented by utilizing only the internal shunting of a superconductor-insulator-superconductor junction, resulting in a hysteretic current-voltage relationship.⁶⁵ The relaxation oscillator junction utilized here is designed to enter a transient resistive period upon arrival of a fluxon from $Jth$⁠. The current from $Jro$ switches the gate of the nTron, diverting the nTron channel current to the gate of the hTron.

Spice simulations of the thresholding event are shown in Fig. 21. For these simulations, Cadence was used. In Fig. 21(a), the thresholding junction switches, producing a current pulse from the relaxation oscillator junction. In Fig. 21(b), the gate of the nTron switches, and the nTron channel current is diverted to the gate of the hTron, returning with the $τnT$ time constant.

The series of events shown in Fig. 21 comprises the detection of neuronal threshold (which occurs when $Jth$ switches), and the subsequent current amplification, beginning with the switching of $Jro$⁠, and leading to the switching of the nTron. The 1.2 mA current pulse coming from the nTron and driving the gate of the hTron is shown in Sec. IV B to be sufficient to switch the hTron, resulting in a voltage pulse and light generation from the LED. The $L/r$ time constant in this simulation was 50 ns, corresponding to 500 nH in series with the $10Ω$ of the hTron gate. Figure 20(b) shows this nTron time constant is sufficient to produce more than 3000 photons if the LED capacitance is 10 fF and the LED efficiency is 1%. Increasing the nTron inductance can extend the pulse duration and thereby produce more photons. With the material and device parameters used in this model of the nTron, 50 ns recovery was sufficient to keep the nTron from latching, and shorter recovery times may be possible, depending on electrothermal device engineering. As discussed in Sec. IV B, a square rather than exponential current pulse would have a significant impact on the light-production efficiency. Such operation may be achieved with cascaded hTrons in place of the nTron.

Having demonstrated threshold detection, current amplification, and voltage amplification, we have completed the description of the amplification chain of the neuronal transmitter circuit. We next discuss the efficiency of the amplifier chain.

In Secs. IV A–IV C, we describe circuits capable of detecting threshold in the NT loop, amplifying the signal, and producing the voltage necessary to generate light from a semiconductor diode. We have calculated the energy consumed by each element of the amplifier chain when generating the number of photons necessary for neuronal communication in realistic networks. These networks will comprise a variety of neurons with a range of numbers of synapses. The number of out-directed synapses made by a neuron is referred to as the out-degree, $kout$⁠. The number of photons that must be produced in a neuronal firing event depends on $kout$⁠, and, therefore, so does the energy of a neuronal firing event, which we denote by $Eout$⁠.

In an ideal case, a neuron could produce one photon per synaptic connection with unity production efficiency, the photons would reach their destination without loss, and they would be detected at the synapse with unity detection efficiency. In this case, we would have $Eout=hνkout$⁠. In an actual network implemented in hardware, waveguides will have propagation loss, and detectors will have efficiency less than unity. To account for these loss mechanisms, a neuron will produce a number of photons greater than one per synaptic connection. We refer to the number of photons produced per synaptic connection as $ζ$⁠. If $ζ$ is too large, neurons are wasting power. If $ζ$ is too small, communication will be unreliable. The synapses of Sec. II have the same response if they receive one or more photons. Therefore, the noise is not shot noise, as it would be if the synapse were attempting to detect the precise number of incident photons. The communication error can be calculated from the Poisson distribution. Given an average number of incident photons on a synapse due to an upstream neuronal firing event, we use the Poisson distribution to calculate the probability that a synapse will receive zero photons due to a neuronal firing event. If the average number of incident photons is five, the probability that the synapse will receive zero photons is less than 1%. A neural system is likely to be able to tolerate this level of error.⁷⁵ In the case of lossy waveguides with low-efficiency detectors, 3 dB loss may be incurred between a neuron and a synaptic target. We thus consider $ζ=10$ to be a representative number to use in calculations of network power consumption.

In addition to propagation loss and detector inefficiency, the circuits described in this work are not entirely efficient at producing photons. The total energy consumed by the amplifier chain during a neuronal firing event is given by

where $ηamp=ηLEDηhT$⁠. Note that $ηhT$ includes all contributions from the nTron and the hTron. The Josephson circuits driving the nTron contribute negligible energy consumption. The calculations of Secs. IV A and IV B provide us with numbers for $ηLED$ and $ηhT$ for several values of LED capacitance and internal quantum efficiency. These functions are plotted in Figs. 22(a) and 22(b). Figure 22(c) shows the total amplifier efficiency, $ηamp$⁠. We see that driving the hTron with the nTron [Fig. 22(b)] dominates power consumption, yet the amount of time the hTron must be on is determined by the emitter capacitance and efficiency, and, therefore, emitter improvement is necessary for system improvement. The circuits can also be made more efficient with improved thermal design of the hTron (through phonon localization) and current pulse shaping into the hTron gate.

In practice, achieving small, waveguide-integrated LEDs with low capacitance should be possible. A simple parallel plate model indicates 1 fF should be achievable, and 10 fF should not be particularly challenging, even with wiring parasitics. In Fig. 22, we consider values as poor as 100 fF. The quantum efficiency of the device is harder to predict. Waveguide-integrated light-emitting diodes with efficiency near 0.01 have been demonstrated,⁷⁰ and low-temperature operation helps significantly in this regard. We expect quantum efficiency of 0.01 to be achievable at large scale, but in Fig. 22, we consider values as poor as $10−3$⁠. Considering an LED with 10 fF capacitance or less, if the LED efficiency is as poor $10−3$⁠, the total photon production efficiency of the amplifier chain is $ηamp≈10−4$ when more than 200 photons are produced. For calculating the power consumption of the networks described in Sec. V, we use Eq. (2) with $ζ=10$ and $ηamp=10−4$⁠.

With the design of the transmitter portion of the circuit, the neuron model presented in this paper is complete. The full circuit is shown in Fig. 23. The analysis presented here points to two conclusions. The first conclusion is that to produce photons with short pulses from the hTron, it is necessary to fabricate LEDs with low capacitance. Other integrated photonic applications find that capacitance dictates the scale at which light becomes advantageous.¹³⁹ The second conclusion is that the overall photon production efficiency is limited by the internal quantum efficiency of the LED when producing large numbers of photons. As argued in Sec. I, cognitive neural systems are likely to utilize some neurons with relatively small out-degree making only local connections as well as other neurons with high degree making local and long-range connections. The value of capacitance achievable by the LED will determine the lowest degree practical to implement with photonic connectivity.

While capacitance limits utility for low-degree operation, internal quantum efficiency determines system power consumption dominated by neurons with high degree. The maximum achievable quantum efficiency will depend on emitter design, materials employed, and fabrication optimization. The requirements for this approach to neural computing differ from the requirements of other integrated photonics applications. Emitters with carrier recombination times as long as 50 ns, the same as the SPD recovery time, can be tolerated. For many integrated photonics applications, such a light source would be too slow. The ability to produce light at multiple frequencies may be advantageous, but spectral coherence is not required. Compound semiconductors have these spectral and temporal properties, and they can be integrated with silicon waveguides⁷⁰ with high efficiency, particularly at cryogenic temperature. Yet, fabrication with compound semiconductors is more expensive and more difficult to scale than silicon. Cryogenic operation enables several types of silicon light sources,^63,140,141 which bring the advantage of simpler process integration. Whatever the material, sources providing incoherent pulses with 10 000 photons produced with an internal quantum efficiency of $10−3$ operating at 20 MHz at 4.2 K are sufficient to enable a massively scalable neural computing platform with connectivity comparable to the brain and 30 000 times faster speed.

It may not be necessary to incorporate a light source at each neuron. Perhaps, an architecture can be utilized with circulating light in waveguides that are tapped by a modulator during each neuronal firing event. Such a system would have the benefit of keeping light sources out of the cryostat and separate from superconducting circuits. In the case of shared off-chip light sources, the new challenges become to develop very low loss waveguides; compact, efficient modulators with low insertion loss that do not need to be tuned; and extensive fiber-to-chip coupling. Initial calculations indicate that such an approach is less efficient unless waveguides can be made with very low propagation loss, and modulators can be made with very low insertion loss. Yet, device and system limits are far from understood. Amplifier circuits similar to those presented here may be useful when driving the modulators of such a system.

The synaptic receiver and synaptic weight update circuits in the forms presented in Secs. II and III utilize separate photons for synaptic firing and synaptic update. In this work, circuit operation culminates by producing light from a single LED, yet it may be desirable to implement transmitters that fire different LEDs for the different operations. This is one way that the power used for synaptic firing events can be decoupled from the power used for synaptic update events. If different colors are used for each of these operations, the same waveguide routing network can be employed for the three signals (synaptic firing, synaptic strengthening, and synaptic weakening), and the demultiplexers located at each downstream neuron can separate the signals and route them locally to the three synaptic ports. Similarly, the spike-timing-dependent plasticity circuit of Sec. III requires not only photons from the presynaptic neurons, but also photons from the local, postsynaptic neuron. Two additional light sources may be useful at each neuron to be utilized locally for synaptic update. The schematic diagram in Fig. 1 shows these five light sources. While producing five light sources instead of just one adds hardware overhead, the light sources are extremely compact compared to the routing waveguides and inductors associated with the synapses. By utilizing independent light sources, it may be possible to reduce network area as well as power consumption.

The ability of a neuron to hold a refractory period is important for spiking operation. In the neuron under consideration, one way to achieve this is by cutting the bias to $Jth$ upon neuronal firing. This makes it impossible for $Jth$ to be driven above $Ic$ and can be straightforwardly implemented with feedback from the output of the nTron or hTron.

In the schematic of Fig. 1, we emphasize three main current biases that affect the operation of each neuron. A current bias into the synaptic update circuit of Sec. III affects the learning rate. A current bias into the neuronal threshold loop affects the neuron threshold. A current bias into the light emitter affects the number of photons produced in a neuronal firing event, which we refer to as the reach of the neuron. With each of these currents fixed, the neurons and the network will have rich spatiotemporal dynamics. Yet, a network with the ability to dynamically vary these currents will be capable of achieving further complexity over longer time periods. For example, with the learning rate current fixed, spike-timing-dependent plasticity occurs at a fixed rate. By changing this current, the network can make certain regions more adaptive at certain times, and it can make those regions maintain synaptic weights at other times. Similarly, with a fixed reach current into the transmitter, the neuron will address each of its downstream connections with a given probability. By changing the reach current, the number of photons produced in a neuronal firing event can be adjusted, and, therefore, the probability of reaching downstream connections can be tuned. Changing these bias currents is analogous to changing various neuromodulators in biological systems. The values of each of these neuromodulatory control currents can be modified with photonic or electronic signals set externally or based on the internal network activity. These neuromodulatory control currents provide powerful means to dynamically transform a given structural network into myriad functional networks.

As we have seen in this section, production of light during each neuronal firing event requires an amplifier chain that consumes considerable energy relative to the Josephson circuits comprising the synapses and dendrites of the neuron. The choice to communicate with light brings this energy cost and necessitates the integration of superconductors with semiconductors. These costs are important to consider as one weighs options for advanced cognitive hardware. It would be simpler if all computation and communication could be achieved with electronic circuits, but an all-electronic communication infrastructure that can feasibly interconnect large numbers of neurons at the scale necessary for cognition without traffic-based delays has yet to be proposed. While photonic communication adds to the energy per neuronal firing event as well as to hardware requirements, the analysis of this section indicates that the total energy of a neuronal firing event is still quite reasonable, and if silicon light sources can be demonstrated to meet the specifications of these circuits, hardware integration will be tractable.

Neural computation depends critically on the structure of the network.³ Whether the application of the network is for control, sensory processing, or cognition, efficient information processing requires the architecture to possess certain features. For example, in visual processing, local clusters of neurons must be differentiated to independently code for certain stimuli, yet the information from many such clusters must be combined at a larger scale to identify groupings of features and trends across a visual field.⁴⁵ Such differentiated local processing combined with broad integration repeats at multiple levels of hierarchy.^17,28 This hierarchical architecture leads to systems with fractal properties in space and time.^12,18 Such an architecture balances differentiated, local information processing with efficient integration of information across the system.⁷ In this section, we begin to explore networks in which superconducting optoelectronic neurons can be connected to achieve the desired fractal network architectures.

We would like superconducting optoelectronic networks (SOENs) to meet several criteria: (1) physical instantiations must accomplish the networks in a manner that can be straightforwardly fabricated with conventional lithographic techniques; (2) the networks must achieve a hierarchical architecture that can be manufactured from the scale of a single die up to a 300 mm wafer; (3) for efficient information integration, systems at the die scale must contain hub nodes with thousands of synaptic connections, and at the scale of a wafer, which we would like to serve as a column in cortex, high-degree nodes with tens of thousands of edges must be possible;¹⁰⁷ (4) considering these systems as modules, we extrapolate to neural systems at very large scales, where it must be possible to connect modules with dense local clustering into systems of billions of neurons for human-scale cognition; and (5) the power density of these networks must be low enough for cooling with $4He$ at 4.2 K to be utilized. In this section, we present SOEN designs satisfying these criteria.

Optical communication between neurons provides three major strengths. First, because photons are uncharged and massless, optical interconnects have no capacitance, resistance, or inductance, enabling massive fan-out. Nodes with very high degree can be achieved without the need for multiplexed communication lines and signal arbitration.¹²⁰ Second, it is possible to send and receive single-photon signals, leading to communication with high energy efficiency.⁶¹ Third, because light travels at the highest velocity in the universe, systems signaling with light can integrate the largest area of neurons with coherent oscillations. Yet, devices based on optical signals have an important disadvantage: the device size is difficult to shrink below the wavelength of light. While superconducting optoelectronic neurons can make many connections, operate with high energy efficiency, and integrate a large area with coherent oscillations, the total number of neurons that can cooperate coherently depends on the total area of the system (limited by the speed of light) divided by the area of the individual neurons (limited by the wavelength of light). To begin to assess the potential of SOENs for near-term technological applications, we must analyze the types of systems that can be achieved on a single die, such as $1×1cm2$⁠. To assess the ultimate scaling potential of these networks when limited by light-speed communication, we must analyze what can be achieved within an area limited by the distance light can travel in the period of a network oscillation. We consider both these scales here.

Whether for near-term technological applications or long-term cognitive systems, the networks we wish to employ are likely to share several characteristics.¹² For cognitive systems large and small, differentiated processing balanced with information integration across spatial and temporal scales is crucial for performance.^{6,7,11,13,18,45,142} Several network theory metrics can be employed to assess the fitness of a network for neural computing. We focus on three metrics relevant to differentiated processing and information integration.

The first metric is clustering, which quantifies the prevalence of triangles in the network. Triangles refer to groups of three nodes connected by edges. High clustering enables information to be shared locally. To achieve differentiated information processing, we seek networks with a high degree of clustering compared to a random network with the same number of edges on the same vertex set.

The second network metric is average path length. For a given network, we can calculate the shortest distance from every node to every other node. Averaging this distance over all pairs of nodes yields the average path length. To achieve information integration across spatial scales, the average path length should be nearly as small as the corresponding random network. High clustering with short path length characterize a small-world network.²⁴ 

The third network metric is the degree distribution. The degree of a node refers to the number of edges it forms with other nodes. In the present work, we consider two degree distributions: power-law and delta-function. For information integration across spatial scales with efficient wiring,¹⁴³ the degree distribution of the nodes in the network may follow a power law, thereby achieving a scale-free network.²⁵ Small-world, power-law networks have efficient communication, a balance of differentiation and integration, fractal properties of self-similarity across spatial scales, and are observed in many natural settings, including the networks of the brain.¹⁴⁴ We also consider structures closer to random networks, characterized by Gaussian degree distribution, which are optimized for short path lengths. Highly connected random networks with short path lengths are ideal for associative memories, such as the hippocampus. We approximate the narrow Gaussian with a delta function, meaning that all nodes of the network have the same degree.

To achieve information integration across time, concepts of self-organized criticality^29,145 are pertinent. In the temporal domain, differentiated local processing combined with large-scale information integration result in a power-law frequency distribution of transient synchronized oscillations.^17,18 This $1/f$ behavior leads to fractal use of time as well as space, and gives rise to neuronal avalanches³⁰ and criticality thought to be necessary for information integration and cognition.^30–32,34 In the human brain, $1/f$ behavior is observed from 0.05 Hz to 600 Hz, spanning 4 orders of magnitude.^17,18 For SOENs to achieve criticality, the devices and the network must support oscillations with frequencies obeying a power-law distribution¹⁸ over several orders of magnitude. As we have argued, SOENs will support oscillations up to at least 20 MHz, potentially spanning many more orders of magnitude that the brain.

Here, we consider specific networks with high clustering, short average path length, and power-law degree distribution that are suitable for differentiated processing combined with hierarchical information integration. We approximate the area and power consumption of such networks when implemented with superconducting optoelectronic hardware, and we anticipate the scaling of these networks when limited by light-speed communication. We focus here on microarchitecture at the level of neuron connectivity with the goal of identifying scaling laws for systems achievable in the near term. To develop a correspondence between the adjacency matrix of the network¹⁹ and the physical hardware that will perform the neural operations, we model the spatial extent of neurons and construct a routing scheme to calculate the area of waveguide interconnects (analogous to white matter in the brain).

To achieve high clustering, short average path, and power-law degree distribution while setting ourselves up for straightforward, modular fabrication, we construct our adjacency matrix in a hierarchical manner, as shown schematically in Fig. 24. At the smallest network scale, neurons are tiled in a grid to form a local sector [Fig. 24(b)]. Sectors can then be tiled to form regions. Regions can then be tiled to form modules. In the present work, we consider these three levels of hierarchy, but the algorithm for creating the adjacency matrix can be repeated indefinitely. Networks constructed in accordance with the schematic of Fig. 24(c) with dense intrasector connectivity, few connections between sectors within a region, and sparse connectivity across a module are modeled after the horizontal connections in minicolumns and columns within cortex.^3,22,44,45 Feed-forward, vertical connections are likely to be achieved by stacking such networks, either through sequential processing or multidie assemblies.

Networks with high clustering and average path length close to that of a random network can be constructed in many ways. Here, we use a network growth algorithm. The concept is that the adjacency matrix of a local sector of neurons is formed by adding neurons one by one to the pool, establishing edges based on spatial location as well as the degree of the existing nodes. Such an algorithm introduces winner-take-more development, leading to a few nodes with very high degree, thereby extending the degree distribution to larger values. The next level of hierarchy can be generated by tiling the adjacency matrix of the sector along the diagonal of a larger adjacency matrix representing the region, and forming intersector connections in a manner that again depends on space and node degree. Networks of increasing scale can be achieved by repeating this procedure, thereby achieving the fractal, power-law degree distribution conducive to efficient information integration across the physical substrate of the network. The spatial dependence gives high clustering, which leads to functional differentiation. Reciprocal connection rules contribute to clustering as well as re-entrant connections,³ which give rise to transient temporal correlations that are necessary for information integration across time. The degree dependence of the growth algorithm gives rise to the long tail of the degree distribution, including nodes with high degree, which are advantageous for information integration across space. We have used this growth algorithm to generate a specific network adjacency matrix with 8100 nodes and 330 430 edges in the hierarchical configuration of Fig. 24(c).

It is important to disambiguate two senses in which a network may have fractal spatial properties. We have been discussing the power-law degree distribution, which relates to a network that is scale-free in terms of connectivity. We can also consider the spatial scales across which connections are made. Rentian scaling quantifies fractal properties related to the number of connections made through various partitions of the network. This scaling relates the number of nodes within a topological partition, $n$⁠, to the number of edges crossing the boundary of that partition, $e$⁠.¹⁴⁶ If the relation between $e$ and $n$ follows the form $e∝npT$⁠, the network shows fractal topology, and the Rent exponent, $pT$⁠, is given by $pT=log(e)/log(n)$⁠. The Rent exponent is related to the topological dimension, $DT$⁠, by $pT≥1−1DT$⁠. Consideration of Rentian scaling and topological dimension provide a means to assess a network’s connectivity across various levels of hierarchy.

In the present context, Rentian analysis provides one way to assess the potential for information integration across the physical space of the network. The larger the topological dimension, the more access nodes will have to distant members of the network. For the hierarchical network designed with the growth algorithm, we can approximate $pT$ by considering the number of nodes and edges at each of the three levels of hierarchy. For the specific network under consideration, averaging over the neurons in a local sector, we find there are 17.1 edges into each neuron from other neurons within the sector. Considering a region, there are 17.8 edges into each neuron from other neurons within the region, but not in the same sector. And at the scale of the module there are 17.6 edges into each neuron from neurons in other regions. Based on this analysis, we calculate a Rentian exponent very close to unity. This gives a topological dimension of $DT→∞$⁠. This implies the network can integrate information up to infinite levels of hierarchy, which of course is not possible, as the network only comprises three levels of hierarchy. Networks with large topological dimension support self-organized criticality,^30,34 which is advantageous for information integration in neural systems.^30–34 In networks from Caenorhabditis elegans to the human brain as well as in VLSI wiring, the Rentian exponent is closer to 0.75.¹⁴⁶ This analysis indicates that the network considered here has slightly more long-range connectivity than is necessary. The Rentian exponent can be adjusted within the growth algorithm by adjusting the number of connections made to higher levels of hierarchy.

We seek estimates for physical aspects of SOENs, including size and power dissipation. We first introduce a plausible routing scenario for connecting the neurons in the network described in Sec. V B.

To achieve the massive connectivity required of a neural system, each neuron must send its signals to many different destinations. To achieve this with optical signals in a controlled manner, multiple planes of dielectric waveguides^85–87 must be employed to keep waveguide crossing losses as low as possible and to reduce the area occupied by passive routing. We anticipate employing waveguide planes in pairs. Within each pair, one plane runs predominantly north-south, the other predominantly east-west. The vertical gap between waveguides in a pair is smaller than between the top waveguide in one pair and the bottom waveguide of the subsequent pair. The lowest pairs of waveguides will be used for the most local connections, with higher pairs for successively longer distances. Materials with lower index contrast may be used on higher planes to minimize loss in long-distance connections. In the context of the network discussed in Sec. V B, it is natural to use one pair of waveguide planes for intrasector connections, a second pair for intraregional connections, and a third pair for intramodular connections.

In Fig. 25, we show a row-column routing scheme that connects all neurons in a sector to all other neurons in that sector. This approach to routing results in rows and columns densely packed with communication lines, analogous to the white matter of axons in biological neural systems. The connections from a single neuron are highlighted, and interplanar couplers are drawn as pairs of triangles. We utilize row-column routing to minimize the number of interplanar couplers required. The rules governing the routing are described in  Appendix C, which also discusses routing in feed-forward networks that are used in many machine-learning applications.

While we have shown Fig. 25 to depict neurons connected in a sector, the diagram can also be interpreted as showing sectors connected in a region or regions connected in a module. This fractal spatial property is a result of the hierarchical architecture we intend to employ for cognitive computing, and it is typical of networks characterized by high topological dimension. So far, we have considered networks with three levels of hierarchy, but this fractal pattern can extend indefinitely. In the present context, we envision the row-column routing architecture extending beyond even the chip or wafer scale into multichip and multiwafer assemblies with fiber optics forming dense white-matter connections between modules in three dimensions.

The size of the neurons described in Secs. II–IV, when arranged in the networks described in Sec. V B, is calculated in  Appendix C. We use a spatial model of a superconducting optoelectronic neuron and routing waveguides shown in Fig. 26(a). A schematic of how fabricated layers may be stacked is shown in Fig. 26(b). Applying the analysis of  Appendix C to the network of 8100 neurons discussed in Sec. V B, we calculate that the network will fit on a die $1×1cm2$ using a pair of waveguide planes for intrasector routing, another pair for intersector routing within each region, and a third pair for interregional connectivity.

We would like to approximate the size of networks with more neurons. The model informs us that the area of a neuron will follow a power law as a function of node degree. We show the area of a network as a function of the total number of neurons in the network in Fig. 27(a) for the cases of three pairs of waveguide planes and nine pairs of waveguide planes. In both cases, the degree distribution of the nodes takes the form $p(k)=Bk−γ$ with $γ=1.6$⁠, where $p(k)dk$ is the probability of a node having degree between $k$ and $k+dk$⁠. We find that by utilizing nine pairs of waveguide planes, we can accommodate an integrated system of 1$×106$ neurons on a 300 mm wafer. This network would comprise over 200$×106$ complex synapses, as described in Sec. III. Considering instead a network with delta function degree distribution [Fig. 27(b)], we find a network of 3000 neurons each with 300 synapses will occupy a $1×1cm2$ die. A 300 mm wafer will support 40 000 neurons with 4000 connections per neuron. The number of synapses within a given area is similar for the power-law degree distribution and the delta function degree distribution. The main difference is the power-law degree distribution contains more neurons with fewer synapses and a few neurons with many synapses. Both network architectures are likely to be useful for certain types of information processing.

 Appendix C describes the calculation of the area of a neuron based on consideration of optical waveguides and single-photon detectors. From this area estimate, we can calculate the area available for the superconducting electronic components that contribute to the neuron, assuming they are patterned above the waveguides in repeating layer modules, as shown in Fig. 26(b). The area available for superconducting inductors, mutual inductors, and Josephson junctions is given by the area of the node divided by the in-degree. This area is multiplied by the number of repeating layers utilized in the fabrication process. We find the area available for superconducting electronic components is at least $30×30μm2$⁠. A $1μH$ inductor is on the larger end of what is likely to be utilized by the SI loop or SS loop. When constructed of a material such as MoSi with high-kinetic inductance (⁠$180pH/□$⁠) and patterned with 50 nm lines, the area is $5×5μm2$⁠. This leaves plenty of area for multiple inductors and wiring. The mutual inductors required to couple the SI loop to the NR loop will be patterned with a different superconducting material separated from the high-kinetic-inductance layer by an insulator. Mutual inductance of 100 pH is desirable. Again, it is quite possible to fabricate a 100 pH mutual inductor from two superconducting coils within this area. Each synapse also requires on the order of 10 JJs with $Ic$ near $40μA$⁠. These devices are approximately $1×1μm2$ and will easily fit in the available area. Finally, the largest components of the neurons are likely to be the amplifiers that drive the light emitters and the mutual inductor coupling the neuronal receiving loop to the neuronal thresholding loop. These devices are not required at every synapse, but rather only at each neuron. Therefore, area is not likely to be a problem. Passive photonic waveguides are likely to dictate the area, and they are limited by the wavelength of light.

We have mentioned in this paper that neurons based on similar JJ circuits, but using no optical components, could be created with much the same design as the neurons in Sec. II and synapses in Sec. III. The purely electrical neurons would have difficulty achieving the fan-out necessary for the networks discussed here. Nevertheless, the electrical neurons could potentially achieve $k≈20$ with a more compact footprint, lower power dissipation, and higher speed. It may be advantageous to construct a hybrid network with nodes from $k=2$ to $k=20$ being purely electrical neurons with flux quanta playing the role of photons. We consider a network with power-law distribution wherein nodes with $k=2$ to $k=20$ are assumed to be electrical neurons, and nodes with $k>20$ are assumed to be optical neurons. We perform an area calculation using modified forms of Eqs. (C2) and (C3) using physical dimensions appropriate to superconducting wiring rather than photonic waveguides. Whereas a network of just over 1$×106$ optoelectronic neurons fit on a 300 mm wafer, a network of 4$×106$ total neurons can be achieved if we combine low-degree superconducting neurons with high-degree photonic neurons. This network would comprise over 1$×109$ synaptic connections. Such an architecture would extend the spatial power-law distribution to lower degree while extending the temporal power-law distribution to higher frequency.

In addition to comparing to the size of a die or a 300 mm wafer, we must also consider the largest SOEN that can be established. This limit is not technological or economic in nature, but rather it is a physical limitation set by the velocity of communication.

Consider two neurons separated by a distance $d$⁠. At time $t1$⁠, neuron one produces a pulse. At time $t2$⁠, neuron two produces a pulse. We ask whether the pulse generated by neuron one may have contributed to the pulse by neuron two. In particular, we are interested in whether neuron one may drive neuron two to synchronize. For this consideration, the time scale we consider is the inverse of the frequency of oscillation, $T=1/f$⁠. Thus, if

neuron one can induce neuron two to synchronize with oscillations at frequency $f$⁠. In Eq. (3), $v$ is the velocity of signal propagation. For the present discussion, we take the value of $d$ that saturates the inequality of Eq. (3) to define the diameter of the neuronal pool. This result of the size of the coherent neuronal pool decreasing as the inverse of the frequency of synchronized oscillations⁴⁹ is consistent with observations from neuroscience¹⁴⁷ where the slow conduction velocity of axons is a severe limitation to the size of a synchronized network.^17,18,27

Based on Eq. (3), we see the area of the neuronal pool scales as $Ap∝(v/f)2$⁠. The number of neurons in the pool depends also on the size of the neurons. We consider spatial scaling in terms of the size of a synapse, because neurons may have any number of synapses, and, therefore, may span a wide range of sizes, whereas the size of synapses depends less on the degree of the neuron to which they are connected or the total size of the system in which they operate. We suppose that the synapses in a network can be characterized by an average width, $w$⁠. If we assume that a network has connectivity predominantly in a plane (as is the case for mammalian cortex and as we expect from lithography on wafers), the area of a single synapse scales as $An∝w2$⁠. For a given hardware platform sending signals at velocity $v$ to synapses of width $w$⁠, the number of synapses within a neuronal pool with synchronized oscillations at frequency $f$ scales as $Np∝Ap/An∝(v/fw)2$⁠.

We wish to compare the number of synapses in the pool of two different hardware platforms oscillating at the same frequency, $f$⁠. In particular, we wish to compare SOENs to the human brain. Denoting the two hardware platforms with superscripts, we find

A 300 mm wafer can support roughly $2×108$ superconducting optoelectronic synapses, giving $w(soen)=1.9×10−5m$⁠. The area of the human cerebral cortex is $0.095m2$⁠,¹⁴⁸ and it contains $1.6×1010$ neurons.^149,150 If we assume that each neuron has, on average, $104$ synapses,¹⁵¹ this gives $w(brain)=2.4×10−8m$⁠. A biological synapse is 1000 times smaller than a superconducting optoelectronic synapse in width, and 1$×106$ times smaller in area. The speed of signals in cortex is roughly 2 m/s.¹⁵² Axons with larger diameter can propagate signals above 100 m/s, but for the dense connectivity of cortex, such large fibers cannot be supported. The speed of light is $3×108m/s$⁠.¹⁵³ Thus, comparing SOENs to biological networks, we find $Np(soen)/Np(brain)≈1010$⁠. The neuronal pool enabled by light-speed communication can contain 10$×109$ times the number of synapses as the pool enabled by ionic signal propagation along biological axons. Signaling at the speed of light brings a tremendous advantage in this regard, an advantage made more significant in networks spanning a volume rather than an area. This simple scaling analysis does not take into account factors that may be significant for very large systems, such as volume required for liquid helium flow for cooling or the volume of white matter occupied by optical fibers carrying signals between large modules. Suppose these factors introduce a quadratic error, and the correct scaling is the square root of this estimate. We would still be considering a system with 100 000 times the number of synapses as the human brain. Despite the coarse nature of this comparison, we include it here to emphasize a crucial point. Communication at the speed of light may enable neural systems with many more neurons and synapses than the human brain even though photonic neurons and synapses are significantly larger than their biological counterparts.

It has been hypothesized that the conduction velocity of axons limits the size of biological neural systems and that scaling of a single cognitive system much beyond the human cortex may not be possible with biological axon conduction velocities.^18,154 Based on these scaling arguments, we expect the largest cognitive systems in the universe to communicate at the speed of light, enabling full utilization of each neuron’s light cone. While other approaches to neural computing may utilize light for communication, it is unlikely other photonic neural devices will be significantly smaller than those presented here, as the optical wavelength imposes a practical spatial limit. In Fig. 27(c), we show the area of the neuronal pool as a function of oscillation frequency $f$ for a general neural system communicating at the speed of light. When oscillating at 1 MHz, an area the size of a large data center (⁠$105m2$⁠) can be coherently synchronized. When oscillating at 10 Hz (near the $θ$ and $β$ bands of the human cortex), an area the size of the surface of the earth can be coherently synchronized. Cognitive systems far beyond our comprehension may be possible with light-speed communication and single-photon efficiency.

In addition to the size of a SOEN, we must also consider its power consumption, which depends on the energy per synapse event, the degree distribution of the neurons, and the firing frequency distribution of the neurons. Analysis of power consumption in the networks under consideration is detailed in  Appendix D. From that analysis, we find if we assume the total photon production efficiency of $ηtot=10−4$⁠, the network of 8100 neurons will dissipate 1 mW of device power, a trivial load for a modern cryogenic system. Including the power dissipated to establish bias currents, total on-chip power will be less than 10 mW. The dominant power draw is the cryo cooler, and for this system, it would require a few hundred watts. For the system of 1$×106$ neurons and 200$×106$ synapses on a 300 mm wafer, the total device power dissipation would be approximately 1 W. This is the cooling power of a common Gifford-McMahon cryocooler with base temperature of 4.2 K, drawing roughly 1 kW.

In addition to low total power, the power density of these systems is also quite small. For the case of the network on a wafer, the power density is $10W/m2$ if a poor total light-generation efficiency of $ηtot=10−4$ is assumed. The heat produced can be straightforwardly removed, and immersion in a liquid helium bath will be excellent for this purpose.¹⁵⁵ This power density is far below the threshold for boiling liquid helium. Liquid helium is transparent at telecommunication wavelengths with an index of refraction very close to one. Thus, optical signals can be sent between neural modules in this environment without attenuation at the maximum speed allowed in the universe. Because the area of devices grows as a faster function of node degree than the power dissipation, cooling SOENs is possible in principle up to systems with size limited by the speed of light.

We have argued that neural systems benefit from at least three network structural characteristics: clustering, short paths, and power-law scaling. We have utilized an algorithm to generate adjacency matrices with these characteristics that correspond to networks hierarchically arranged across spatial scales, and we have proposed that such networks could be implemented with superconducting optoelectronic hardware using 300 mm lithographic technology. Networks with millions of neurons and hundreds of millions of synapses can be fabricated on a 300 mm wafer. While Moore’s law has been sustained through feature size reduction, scaling of SOENs will be enabled by scaling the process up in terms of the number of processed layers, lithographic field area, wafer size, and multiwafer assemblies. Whereas economics has driven CMOS to bigger wafers, network scaling will drive SOENs to bigger wafers. Fortunately, feature sizes in all devices of this system are easily achievable with 190-nm lithography.

As described in Sec. I A, this work is motivated by the intention to develop artificial cognitive systems. We have investigated the utility of superconducting optoelectronics to achieve multiple neuronal functions with adaptation across a wide range of time scales, meeting many of the needs for relaxation oscillators in complex cognitive circuits. We have investigated the communication networks necessary to enable dense local clustering as well as long-range connectivity for efficient communication across temporal and spatial scales. We have considered area and power consumption, and we find compelling evidence that this hardware platform has extraordinary potential to perform the functions underlying cognition. We think this work makes a strong case that a significant experimental effort to develop superconducting optoelectronic hardware is justified.

We are interested in systems with near-term feasibility. Considering the aforementioned network of 8100 neurons and 330 430 synapses, the network occupies $1×1cm2$ when processed with 3 pairs of waveguiding planes. Operating at 20 MHz and possibly far beyond, the dynamical state space of this system would be extraordinarily complex and could provide a fascinating experimental setting for many subjects including self-organized criticality^30–34 in an artificial network approximating cortex. Such a neural module is also likely to offer significant technological opportunities in applications such as visual and auditory sensory processing, language recognition, and mechanical control.

When combined with an artificial retina based on superconducting detectors, a powerful artificial vision system could result. A three-chip stack could accomplish this. One chip would serve as a retina, and the other two chips would serve as layers of visual cortex, arranged in a manner analogous to the columnar organization of the mammalian visual cortex.⁴⁴ Feed-forward communication is likely to make use of vertical optical links with light in a lower layer being sent vertically with a grating coupler and received by a single-photon detector at a neuron on a higher layer. Such a model, capturing the columnar, vertical flow of information between layers as well as the laminar, horizontal flow within layers,^3,22,49 has been shown to function well for object recognition in computer simulations.⁴⁵ Using visual systems as a testbed of SOEN hardware is beneficial because photon detectors are native to the hardware, and also because the visual system is the most studied system of the mammalian cortex. Investigation of binding in vision^{15,16,45–47,156} can inform other neural computing systems including motor control systems, language processing, or other cognitive architectures.

Similar modules are also likely to tile well into larger networks. With a $10×10$ grid of interconnected die, the system would contain as many neurons as a bumble bee, a creature observed to have advanced navigational skills;¹⁵⁷ multimodal communication and learning;¹⁵⁸ cognitive flexibility;¹⁵⁹ and emotions.¹⁶⁰ A 300 mm wafer would yield enough die for six of these small brains. Each system would comprise nearly 1$×106$ neurons and over 33$×106$ synapses with complex plasticity and metaplasticity. These neurons and synapses would operate up to 30 000 times faster than any known living creature. Such a system would be readily accommodated by existing cryostats.

If one chose to utilize an entire 300 mm wafer for a single module, neurons with as many as 10 000 synapses could integrate the activity of networks with 1$×106$ neurons. Such a structure would be analogous to a module in cortex, except for the significant increase in speed. Considering such modules as the building blocks of larger systems, stacks of wafers could be assembled with free-space and fiber coupling between. We can consider an interconnected stack of wafers as a column. An arrangement of columns could be interconnected to contain tens of billions of neurons, matching the number in the human neocortex.^150,151 A SOEN with the same number of neurons as human cortex would occupy a volume less than 2 m on a side.

While it may be difficult to build systems larger than 10$×106$ neurons in the near term, such a system is not physically limited. Like the brain, such limits will be incurred due to the velocity of signal propagation. From Fig. 27(c), we know that networks as large as data centers can sustain coherent oscillations at 1 MHz. Such a facility would house $108$ 300 mm wafers if they were stacked 100 deep. This would result in 100$×1012$ neurons per data center across modules interconnected with another power-law distribution.

It is conceivable that networks could continue to scale beyond the size of data centers, and information integration through slow-wave system-wide activity could occur at 1 kHz—faster than any oscillation of the human brain. In this case, the neuronal pool could occupy a significant fraction of the earth’s surface and employ quintillions of neurons. We do not wish to cover earth in such devices, but asteroids provide ample, uncontroversial real estate. The materials for this hardware are abundant on M-type and S-type asteroids.^161–165 It appears possible for an asteroid belt to form the nodes and light to form the edges of a solar-system-scale intelligent network. Asteroids can be separated by billions of meters, so light-speed communication delays may be several seconds or longer. For cognitive systems oscillating up to 20 MHz, such delays would cause individual modules to operate as separate cognitive systems, much like a society of humans.

We thank Dr. Alexandra Artusio-Glimpse, Bryce Primavera, and Dr. Alexander Tait for helpful conversations and insights.

This is a contribution of National Institute of Standards and Technology (NIST), an agency of the U.S. government, not subject to copyright.

Unless otherwise specified, we take $Ispd=10μA$⁠, comparable to the switching current of MoSi¹⁶⁶ SPDs. Designs with lower $Ispd$⁠, as would be present in WSi nanowires,⁶¹ or higher $Ispd$⁠, as would be present in NbN⁵⁸ or NbTiN¹⁶⁷ nanowires are also straightforward to achieve. The variable resistor of the SPD has zero resistance in the steady state, and it switches to a high-resistance state (⁠$≈5kΩ$⁠) temporarily (⁠$≈200ps$⁠) upon absorption of a photon.⁶² Typical values for the parameters in Fig. 3(a) are $Lspd=100nH$⁠, $Ispd=10μA$⁠, $rspd=2Ω$⁠, $Isy=800nA−4μA$⁠, $Lsf=200pH$⁠, $Ib=7μA−9μA$⁠, $Lsi=100nH−10μH$⁠, and $Msy=1nH$⁠. $Ic$ of JJs is chosen to be $10μA$ in Sec. II to improve energy efficiency. In  Appendix D, we argue this is not necessary, and implementation with junctions of $Ic=40μA$ or higher is probably a better design choice. The JJs used in simulations in this work have $βc=0.95$⁠, where $βc=2eIcCR2/ℏ$⁠, with $C$ being the junction capacitance and $R$ being the junction resistance in the RCSJ model.^65,66 The parameter $βc$ corresponds to the junction damping (with $βc=1$ corresponding to critical damping), and for this study, we consider slightly over-damped junctions. Typical values for the transformer inductors in Fig. 3(b) are $Lt1=1μH$⁠, $Lt2=100pH$⁠, and $Lt3=10pH$⁠.

In all flux-storage loops, there is a trade-off between inductance and area. High-kinetic-inductance materials such as WSi have inductance per square as large as $250pH/□$⁠. By patterning a nanowire of such a material in a meander geometry, we can produce an inductor with $10μH$ in an area of $35×35μm2$ with a minimum feature size of 50 nm. We argue in Sec. V that these relatively large inductors are still compatible with scaling to neurons with 1000 synapses because the area of photonic routing is generally the limiting factor.