We report on the experimental demonstration of all-dry stamp transferred single- and few-layer (1L to 3L) molybdenum disulfide (MoS2) field effect transistors (FETs), with a significant enhancement of device performance by employing thermal annealing in moderate vacuum. Three orders of magnitude reduction in both contact and channel resistances have been attained via thermal annealing. We obtain a low contact resistance of 22 kΩ μm after thermal annealing of 1L MoS2 FETs stamp-transferred onto gold (Au) contact electrodes. Furthermore, nearly two orders of magnitude enhancement of field effect mobility are also observed after thermal annealing. Finally, we employ Raman and photoluminescence measurements to reveal the phenomena of alloying or hybridization between 1L MoS2 and its contacting electrodes during annealing, which is responsible for attaining the low contact resistance.

Two-dimensional (2D) transition metal di-chalcogenides (TMDCs) have emerged as excellent candidates for future low-power electronics and optoelectronics. Thanks to the sizeable and thickness-dependent bandgaps in semiconducting 2H-phase crystals, the TMDC field effect transistors (FETs) offer sufficient on/off ratio for logic applications. This attribute makes 2D TMDC FETs promising devices beyond graphene FETs, which cannot be effectively switched off due to its zero bandgap. Molybdenum disulfide (MoS2), a forerunner in the TMDCs family, has been extensively employed for making 2D FETs. Importantly, compared with other TMDCs, MoS2 processes a larger energy barrier against oxidation1 and degradation,2 making even its single-layer (1L) form stable in ambient, enabling persistent and robust 2D FETs. Various studies have been performed to demonstrate single-, few- and multilayer MoS2 field effect transistors.3–5 Although these studies reveal that MoS2 FETs display a very high On/Off ratio (up to ∼106–108), most of these FETs suffer from relatively low mobility (especially compared to graphene FETs). Despite the demonstration of very high hall mobility of 34 000 cm2/V s for six-layer MoS2 at low temperature using careful contact engineering and dielectric encapsulation,6 at room temperature, the highest field effect mobility is still around 500 cm2/V s for multilayer MoS2 FETs.7 Without any encapsulation and chemically doping or treatment, measured field effect mobility of 1L MoS2 in room temperature is even more compromised, which is mostly around 0.1–10 cm2/V s.8 

In devices at room temperature, the origin of this low mobility stems from the defects and impurity, interfacial scattering, and very high contact resistance.9 From previous studies, it has been observed that MoS2 could adsorb a noticeable amount of impurities including carbon (C), oxygen (O) from air.9 Moreover, it has been known that the humidity in air can affect the performance of MoS2 FETs due to adsorbed water molecules.10 Besides, very high contact resistance due to Schottky barrier (SB) is an open challenge for achieving high performance TMDC FETs. One way to reduce the Schottky barrier height of MoS2 FETs is to choose low work function metals, e.g., Ti, Ni, and Sc.5 However, the MoS2-metal interface is strongly impacted by a Fermi-level pinning irrespective of the choice of metal for contacts.5 Another approach to address these challenges and enhance the performance of MoS2 FETs is vacuum thermal annealing, which can efficiently remove the surface impurities or adsorbates and lower contact resistance. Vacuum thermal annealing is an effective means of eliminating the adsorbed water molecules, and thus is naturally beneficial for resolving the humidity effects and associated limitations on the MoS2 FETs of our interest. It has been proven that vacuum thermal annealing of MoS2 greatly improves the performance of multilayer MoS2 FETs.11 The effectiveness of thermal annealing on 1–3L MoS2 FETs, however, remains elusive and is largely unexplored yet. Besides, the device physics behind the reduction of contact resistance due to thermal annealing is not clearly understood. In this study, we focus on a clear experimental investigation of the thermal annealing effects on the performance of 1–3L MoS2 FETs. We observe a salient performance enhancement of 1–3L MoS2 FETs after thermal annealing in moderate vacuum: thermal annealing reduces both the contact and channel resistances significantly and greatly improves the field effect mobility. We also investigate the origin of lowering contact resistance after thermal annealing by using Raman and photoluminescence (PL) measurements.

1–3L MoS2 FETs are fabricated by dry transferring mechanically exfoliated MoS2 flakes to 290 nm SiO2-on-Si substrate with pre-patterned electrodes (5 nm Cr for the adhesive layer and 40 nm Au for the contact electrode).11 The crystal quality and thickness of 1–3L MoS2 flakes are verified by using both Raman and PL measurements. In contrast to conventional MoS2 FETs, where metal is deposited on the top of MoS2 for contacts, MoS2 in our devices is transferred on the top of the electrodes. This unique device configuration enables us to optically characterize the exposed MoS2 on the top of the metal contact without additional chemical modifications that may alter the MoS2 material properties (e.g., chemically removing electrodes to access buried MoS2 at its contact, in conventional devices). In addition to being facile and additive and thus completely avoiding wet chemicals, the all-dry stamp transfer and approach is an intrinsically suitable and advantageous method for fabricating atomic layer crystalline 2D devices on various substrates, especially on curved surfaces and flexible substrates. Ultimately, all-dry stamp transfer techniques are also expected to scale up to large-scale transfer printing and/or roll-to-roll transfer processes.

We employ a home-built split-tube furnace system to conduct thermal annealing of MoS2 FETs. The system consists of a nitrogen (N2) gas source, flow rate control valves, a 1-in.-diameter horizontal quartz tube furnace and a vacuum pump.11 Our typical annealing procedure is as follows: after putting the device in the furnace, the vacuum pump is turned on to reach moderate vacuum (15 mTorr). Then, a N2 flow (50 sccm) is introduced, raising the chamber pressure to 5 Torr. We then increase the furnace temperature to 250 °C and maintain it for 1 h. After completion, the furnace is cooled down for about 30 min, and the device is retrieved after slowly venting the furnace tube with N2.

We perform electrical measurement of MoS2 FETs both before and after vacuum thermal annealing to explore the effects of thermal annealing on the device performance. Figure 1(a) shows the schematic of our MoS2 transistors and their electrode configurations. Electrical measurements are performed using a Keithley 4200-SCS semiconductor parameter analyzer. During measurements, a source measurement unit (SMU, VG) is connected to the back gate (G) and another SMU (VD) is connected to the drain (D) of the MoS2 FET, while the source (S) electrode is grounded. Figure 1(b) shows the cross-section of the MoS2 FET, where 300 nm SiO2 is used as gate oxide and heavily doped p-type Si is used as global back gate. Figure 1(c) presents the optical microscope image of the two devices for our experiment. Device 1 is a 1L MoS2 FET (length L ≈ 2 μm and width w ≈ 11 μm) and Device 2 is a MoS2 FET, which comprises variable thickness from 1L to 3L (L ≈ 2 μm and w ≈ 16 μm).

FIG. 1.

(a) Illustration of the electrical measurement system and schematic of the experiment. (b) The cross-section view of the FET devices and (c) the optical microscope image of our two devices (marked by yellow dashed line) for this experiment. 1–3L regions of the flake are also marked in the image.

FIG. 1.

(a) Illustration of the electrical measurement system and schematic of the experiment. (b) The cross-section view of the FET devices and (c) the optical microscope image of our two devices (marked by yellow dashed line) for this experiment. 1–3L regions of the flake are also marked in the image.

Close modal

We perform Raman and PL measurements by using a customized system. A 532 nm diode laser is focused on the sample by a 50× objective lens and scattered light (for Raman)/photoluminescence (for PL) from the sample is collected in backscattering geometry and is then guided to a spectrometer (Horiba iHR550) with a 2400 g mm−1 (for Raman)/1200 g mm−1 grating (for PL). The Raman/PL signals are recorded using a liquid-nitrogen-cooled CCD. The spot size of the laser is optimized at ∼1 μm. The laser power on the sample is kept at ∼200 μW.

Figures 2 and 3 show the measured transport and transistor characteristics of fabricated MoS2 FETs before and after annealing. To systematically understand the thermal annealing effects on device performance, we extract important parameters (e.g., contact resistance and mobility). In order to estimate the contact resistance of MoS2 FETs, we employ the Y-function method (YFM).12,13 According to YFM, the Y-function can be expressed as12 

Y=IDgm=μ0CoxVDWL(VGVT),
(1)

where ID is the drain current, gm is the transconductance, μ0 is the intrinsic mobility and Cox is the gate capacitance. Using the linear fit in the plot of Y-function with respect to VG (at On-state), μ0 can be extracted. The expression of mobility attenuation factor (θ) due to contact resistance, surface roughness, and phonon scattering as a function of VG can be written as13 

θ=[ID/(gm(VGVT))1]/(VGVT).
(2)
FIG. 2.

(a) and (c) Electrical transport (ID-VD) characteristics for Device 1, measured before and after annealing respectively. (b) and (d) Transfer characteristics (ID-VG) of the same device, before and after annealing.

FIG. 2.

(a) and (c) Electrical transport (ID-VD) characteristics for Device 1, measured before and after annealing respectively. (b) and (d) Transfer characteristics (ID-VG) of the same device, before and after annealing.

Close modal
FIG. 3.

(a) and (c) Electrical transport (ID-VD) characteristics for Device 2, measured before and after annealing respectively. (b) and (d) Transfer characteristics (ID-VG) of the same device, before and after annealing.

FIG. 3.

(a) and (c) Electrical transport (ID-VD) characteristics for Device 2, measured before and after annealing respectively. (b) and (d) Transfer characteristics (ID-VG) of the same device, before and after annealing.

Close modal

If we only consider the effect of contact resistance (Rc) in θ, then Rc can be determined as follows:12,14

2Rc=θ/(μ0CoxWL).
(3)

Using (1)–(3), we first estimate Rc of the 1L MoS2 FET (Device 1). After knowing Rc, we can also determine the channel resistance (Rch) from ID-VD curve. Before thermal annealing, ID-VD curves show a very low On current [see Fig. 2(a)]. These characteristics might be attributed to the high channel resistance and high Schottky barrier at 1L MoS2-Au contact stemmed from large work function of Au. Further, our analysis reveals that before annealing, Rch ≈ 112 MΩ and Rc ≈ 4 MΩ. After thermal annealing, we find a remarkable reduction of Rch and Rc. As shown in Fig. 2(c), the low field ID-VD curves exhibit a clear linear characteristic with higher current. Based on our analysis, it turns out that thermal annealing reduces both Rch and Rc, up to ∼650 and ∼2000 times, respectively. Particularly, it is worth noting that for 1L MoS2-Au, Rc ≈ 2 kΩ (22 kΩ μm), comparable to the low Rc for the 1L MoS2 FET enabled by the metal deposition on MoS2.14,15 In reality, the Y-function method can overestimate Rc for our devices due to the fact that we neglect the effect of surface roughness and phonon scattering on θ, which dictates that actual Rc can be lower than the mentioned values.12 

In addition, we have investigated the annealing effects on effective field effect mobility. The effective field effect mobility (μeff) is extracted from the ID-VG characteristics [Figs. 2(b) and 2(d)]. After annealing, μeff is improved from 0.1 cm2/V s to 8 cm2/V s. From Figs. 2(b) and 2(d), it can be observed that hysteresis in ID-VG curve is reduced slightly after annealing, but is not completely removed due to the interfacial scattering with the substrate. We note that the On/Off ratio is also improved by 10 times even using low drain bias (VD = 2.5 mV) after annealing. Similar improvement of performance is also observed for Device 2: ∼430 and ∼800 times reduction of Rch and Rc [Figs. 3(a) and 3(c)], and 225 times μeff enhancement after annealing. All extracted parameters (before and after annealing) for the two devices are summarized in Table I. From the electrical measurements, it is obvious that thermal annealing can improve the device performance significantly. It is worth mentioning that thermal annealing not only reduces Rch by removing surface adsorbates, but also drastically reduces the Rc, which indicates that alloying or hybridization between Au contact and MoS2 may occur during annealing that changes the material properties of adjacent MoS2 layer. It will be investigated in the Discussions section below by employing Raman and PL measurements.

TABLE I.

Comparison of performance.

Device parametersDevice 1Device 2
Before annealingAfter annealingBefore annealingAfter annealing
Channel resistance (Rch112 MΩ 171 kΩ 60 MΩ 140 kΩ 
Contact resistance (Rc4 MΩ 2 kΩ 10 MΩ 13 kΩ 
Rc/(Rc + Rch) (%) 6.67 2.4 33 18 
Effective mobility (μeff) (cm2/V s) 0.1 0.02 4.5 
On/Off ratio ∼105 (VD = 0.1 V) ∼106 (VD = 2.5 mV) ∼105 (VD = 0.1 V) ∼105 (VD = 2.5 mV) 
Threshold voltage (Vt) (V) −5 −7 −10 
Device parametersDevice 1Device 2
Before annealingAfter annealingBefore annealingAfter annealing
Channel resistance (Rch112 MΩ 171 kΩ 60 MΩ 140 kΩ 
Contact resistance (Rc4 MΩ 2 kΩ 10 MΩ 13 kΩ 
Rc/(Rc + Rch) (%) 6.67 2.4 33 18 
Effective mobility (μeff) (cm2/V s) 0.1 0.02 4.5 
On/Off ratio ∼105 (VD = 0.1 V) ∼106 (VD = 2.5 mV) ∼105 (VD = 0.1 V) ∼105 (VD = 2.5 mV) 
Threshold voltage (Vt) (V) −5 −7 −10 

As we have learnt from some theoretical DFT calculations,16–18 there is a weak adhesion between Au and MoS2 because of weaker binding energy right after fabrication. As a result, initially, we obtain very high contact resistance due to the existence of a tunnel barrier (TB) originated from van der Waals (vdW) gap between MoS2 and Au in addition to a large Schottky barrier (SB) [Fig. 4(e)]. According to our hypothesis, vacuum thermal annealing increases the adhesion and binding energy, which eliminates the vdW gap and its associated TB. Therefore, we should obtain a stronger d orbital overlap between the d orbitals of Mo and Au, which will cause the formation of a covalent bond19 between Au and MoS2. Properties of monolayer MoS2 can be easily distorted by the strong orbital overlaps (covalent bonds). Thus, due to this alloying or hybridization, the electronic properties of the MoS2 on the top of the contact change. In other words, the Au-MoS2 alloy at the Au and MoS2 interface can be expected to be a new material with lower work function, compared with that of the unalloyed MoS2 in the channel.17,18 As a result, due to the lower work function of the alloyed material, Schottky barrier (SB) should be reduced, for which we obtain lower contact resistance. Recently, there is a study20 which presents contact-induced semiconductor-to-metal transition in single-layer WS2, which strongly supports our hypothesis.

FIG. 4.

(a) and (b) Photoluminescence (PL) measurements for 1–3L MoS2 on SiO2/Si substrate and on Au contact electrode. (c) and (d) Raman measurements for 1–3L MoS2 on SiO2/Si substrate and Au contact electrode. All these measurements are performed before and after thermal annealing. Raman intensities are normalized by the peak intensity of Si. (e) Illustration of the effect of thermal annealing in improving the contact.

FIG. 4.

(a) and (b) Photoluminescence (PL) measurements for 1–3L MoS2 on SiO2/Si substrate and on Au contact electrode. (c) and (d) Raman measurements for 1–3L MoS2 on SiO2/Si substrate and Au contact electrode. All these measurements are performed before and after thermal annealing. Raman intensities are normalized by the peak intensity of Si. (e) Illustration of the effect of thermal annealing in improving the contact.

Close modal

We would like to investigate whether there is really any change of properties or crystal quality in MoS2 on the top of the Au electrode which is related to lower contact resistance. As PL and Raman spectroscopy are powerful and precision tools for investigating the crystal quality of materials, by monitoring PL and Raman data before and after annealing, we will be able to probe and quantify alteration or modification in crystal quality. PL and Raman measurements at MoS2 on SiO2/Si show the clear signatures of 1–3L MoS2 [Figs. 4(a) and 4(c)].21,22 Owing to almost same PL and Raman peak intensities before and after annealing [Figs. 4(a) and 4(c)], it can be seen that thermal annealing does not change the intrinsic material properties of MoS2 on SiO2/Si substrate. However, PL and Raman measurements [Figs. 4(b) and 4(d)] of MoS2 on Au contact reveal some clear changes in the properties of MoS2 after thermal annealing. Especially, for 1L MoS2, PL and Raman peak intensities decrease significantly after annealing compared with the intensities before annealing. These results suggest that there might be an alloying or hybridization that takes place during annealing between MoS2 and Au at contacts, which alters the pristine crystal quality of single layer of MoS2. Interestingly, although the PL intensities of 2–3L MoS2 on Au contact show some reduction (possibly due to alteration in the single layer adjacent to the contact) [Fig. 4(b)], Raman peak intensities remain almost the same after annealing [Fig. 4(d)]. These results indicate that the alloying occurs mostly in the single layer of MoS2 in contact with Au, which significantly reduces the Rc [Fig. 4(e)]. In summary, due to annealing, TB due to van der Waals gap between Au and MoS2 disappears and SB has also been reduced because of lower work function of the Au-MoS2 alloy at the Au and MoS2 interface, which reduces Rc considerably [Fig. 4(e)]. As we use all-dry-transfer method to fabricate our devices, which is free from chemical contaminants or residues associated with conventional, mainstream lithographical and/or wet-transfer processes, changes in the surface morphology or roughness of the flakes due to annealing, if any, are expected to be minimal. Thanks to our device structure (MoS2 on Au), we get the opportunity to investigate this phenomenon, which is inaccessible for conventional device structure with post-deposited electrodes on MoS2. Although it has been previously known that this sort of metal-MoS2 alloying or hybridization can only occur for a low work function metal like Ti,17,18 these results suggest that thermal annealing may play a role in the alloying or hybridization process even for larger work function metal like Au. Therefore, our results shed light on the important understanding of the device physics pertaining to the reduction of contact resistance due to thermal annealing.

In summary, in this study, we have experimentally demonstrated significant improvement in the performance of all-dry stamp transferred single- and few-layer (1L to 3L) MoS2 FETs, enabled by vacuum thermal annealing. In addition to the careful contact engineering and dielectric encapsulation, thermal annealing manifests itself toward playing a vital role for realizing high-performance TMDC FETs. Finally, we have demonstrated, the existence of alloying between MoS2 and Au contact electrode after thermal annealing, which is the main reason for the observed salient reduction of contact resistance in these devices.

We acknowledge the support from National Science Foundation CAREER Award (ECCS-1454570). Part of the device fabrication was performed at the Cornell NanoScale Science and Technology Facility (CNF), a member of the National Nanotechnology Infrastructure Network (NNIN), supported by the National Science Foundation (ECCS-0335765).

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