We present an investigation of the effects of asymmetric contacts on the photoresponse of a thin film tungsten diselenide (WSe2) phototransistor. We observe different scenarios in photoresponse during gate modulation depending on the metal-semiconductor contacts through which majority carrier (hole) injection occurs. Under illumination, a peak in drain current is observed during gate modulation when hole injection occurs from the higher Schottky barrier contact. On the other hand, regular behavior in photoresponse during gate modulation is observed when hole injection occurs from the opposite direction, the lower Schottky barrier contact. Further, we analyze the possibilities of realizing WSe2 phototransistors with improved performance in terms of responsivity, response time, and detectivity by utilizing asymmetric contact engineering and proper gating. In addition, an interesting shift of the aforementioned peak is detected, with increasing incident light intensity during gate modulation. We demonstrate that this peak shift can be explained by the photogating effect caused by trapped charges.

Photodetectors are among the most important components of modern optical communication and digital imaging. Recently spurred by the discoveries of graphene and other two-dimensional (2D) crystals derived from layered materials, there has been a growing thrust towards research on photodetectors of such materials. Initially, graphene photodetectors have earned significant interest due to their very fast responses.1 It has been observed, however, that due to rapid electron-hole recombination induced by its zero bandgap and fast carrier transfer, graphene photodetectors often suffer from low responsivity.2 Meantime a family of 2D layered materials, transitional metal di-chalcogenides (TMDCs), show great promise thanks to their strong light-matter interactions.3 In contrast to graphene photodetectors, TMDC photodetectors benefit from their sizeable bandgaps and show excellent photoresponsivity in the broad visible range. Compared to traditional bulk Si and other III-V photodetectors, these layered materials have much higher absorption efficiency despite their ultrathin bodies.2,4,5 Further, their ultrathin nature, outstanding mechanical strength, and ultrahigh stretchability (strain limit often >20%) hold promise for realizing flexible or stretchable photodetector devices. Moreover, strain induced bandgap change may engender new features in TMDC photodetectors.6 Many studies are being performed in order to design highly photoresponsive, low noise, and fast TMDC phototransistors. Single- or few-layer TMDC (e.g., MoS2, MoSe2 WSe2, MoTe2, WS2, etc.) phototransistors have already shown higher responsivity than traditional Si or III-V photodetectors.7–11 The origin of high responsivity in TMDC phototransistors is the long carrier recombination time at trap states and the presence of photogating effect.4 However, the contribution of these long lived trap states in photocurrent generation can result in slow response time on the order of few seconds in TMDC phototransistors.4 In order to attain a fast photoresponse, it is imperative to reduce these trap states. One approach can be applying dielectric passivation;12 another could be employing Schottky contacts.

Schottky barriers (ϕB) at the metal/semiconductor interfaces of a phototransistor can play significant roles in photodetection.13 By operating the phototransistors with Schottky contacts in the Off state, fast photoresponse can be achieved as photogenerated electron-hole pairs can be separated fast and effectively by the internal electric field generated at the depletion regions of Schottky contacts, without being trapped in the long lived trap states. In addition to improving the response time of the phototransistor, Schottky contacts reduce dark current (IDark) of the phototransistor. Lately, it has been demonstrated that Schottky contacts can substantially improve the response time for the WSe2 phototransistor,14,15 down to millisecond (ms) using metal contacts which form a high ϕB at contact. The responsivity (=IphP, where, Iph= photocurrent and P = incident power), however, becomes lower as the photovoltaic effect is dominant in this case which lacks the internal gain mechanism in contrast to the photoconductive effect.4 Two important figures-of-merit (FOMs) for low-noise photodetectors are noise equivalent power (NEP) and detectivity (D*). For low NEP and high D*, IDark is required to be as small as possible. In order to keep the IDark low, phototransistors can be operated in the Off state. Recently, a study has been performed on the MoS2 phototransistor to demonstrate gate voltage (VG) dependence of ℜ and D* (Ref. 12). It is shown that D* increases at the Off state of the phototransistor, whereas ℜ decreases a few orders of magnitude at the Off state.12 Therefore, there is a clear trade-off between ℜ and D* or NEP of a phototransistor. As a result, it requires careful investigations to find ways to enhance or optimize the overall performance of 2D photodetectors. Here in this study, we demonstrate the effects of asymmetric contacts on the photoresponse of the WSe2 phototransistor during gate modulation. As VG modulates the Schottky contacts and thus controls the photocurrent, it can optimize the photoresponse of the WSe2 phototransistor with Schottky contacts. Interestingly, we observe a photocurrent peak during gate modulation, which not only depends on the VG but also on the nature of the metal/semiconductor contact from which carrier injection occurs. We will show that by using asymmetric contacts, it can be possible to improve the performance of the phototransistor. Finally, we also study the effects of trap states due to surface adsorption on the photoresponse of the WSe2 phototransistor.

We fabricate WSe2 field effect transistors (FETs) by transferring mechanically exfoliated flakes on a pre-patterned substrate with electrodes, by using a dry-transfer method.16 The 290 nm-thick SiO2 on the Si substrate has been patterned by photolithography, followed by metallization (5 nm Cr followed by 30 nm Au) and liftoff. By choosing proper substrates with pre-patterned electrodes, it is possible to fabricate multiple FETs from a single WSe2 flake. Here, heavily doped p-type Si is used as the global back gate. Figure 1 shows the device structure and optical microscope image of one of the devices. We use flakes of different thicknesses estimated by optical microscopy contrast studies. Electrical characterization has been performed using a Keithley 4200-SCS semiconductor parameter analyzer in ambient condition at room temperature. For illumination, a Mitutoyo 150 fiber-optic illuminator has been used with a 20× microscope objective lens (∼3 mm spot size), which can be treated as global illumination. Therefore, the entire WSe2 thin film between the electrodes is the active area of the phototransistor.

FIG. 1.

Device structure and measurement scheme of the WSe2 phototransistor are shown in (a) and optical microscope image (scale bar: 10 μm) of one of the WSe2 phototransistors is shown in (b).

FIG. 1.

Device structure and measurement scheme of the WSe2 phototransistor are shown in (a) and optical microscope image (scale bar: 10 μm) of one of the WSe2 phototransistors is shown in (b).

Close modal

After fabricating the devices, we measure the transport characteristics (IDVD) between different pairs of electrodes. From the transfer characteristics shown in Fig. 2(a), the WSe2 phototransistor shows p-type behavior. For drain voltage VD = 3 V (source voltage VS = 0 V), we observe a On/Off ratio of Ion/Ioff ∼105 and a subthreshold swing of SS ∼ 1 V/dec. We have also found from the transistor characteristics that drain current (ID) varies over orders of magnitude when the polarity of VD is changed. Figure 2(b) shows the transport characteristics, where for VD > 0 we get more than one order of magnitude higher drain current than for VD < 0. This indicates that although we have used the same gold (Au) electrodes, we are getting lower ϕB or nearly ohmic at one contact and higher ϕB at the other contact. Generally, asymmetric contacts can be obtained by using metals of different work function. However, the reason behind getting asymmetric transport characteristics (IDVD) despite using the same Au electrodes is the formation of asymmetric ϕB at contacts due to Fermi-level pinning. It has been previously reported that the metal-to-TMDC interface is strongly influenced by Fermi level pinning.17,18 Owing to Fermi-level pinning, ϕB height no longer depends on the work function difference between the metal and semiconductor, rather it is determined by defects or trap states originated from physisorbed molecules such as O2 and H2O which electrically deplete the channel by withdrawing electrons from the channel12 [Fig. 2(c)]. Therefore, ϕB height is dependent on the existence of trap states at a particular location in the flake, where the metal-semiconductor junction is formed. As a result, it is possible to obtain different ϕB heights at two contacts of a FET despite using the same metals because of Fermi-level pinning. In addition to the possibility of Fermi-level pinning, there is a practical possibility that the interface between the metal and WSe2 flake can be different at source and drain contacts after dry-transfer of the WSe2 flake on pre-patterned electrodes, which might also contribute to the asymmetric Schottky barrier contacts. Besides, as we have used a global back gate, the asymmetry at the source and drain contacts cannot be generated from gate voltage. Therefore, the asymmetric IDVD curve can only indicate the formation of asymmetric Schottky contacts. As a result, from Fig. 2(b), due to the lower drain current at VD < 0, it can be inferred that the ϕB at the source contact is higher than that of the drain contact [Fig. 2(d)].

FIG. 2.

Transistor and transport characteristics (inset shows the linear plot) of the device showing effects of asymmetric ϕB [(a) and (b)], where for VD > 0 and VD < 0, we get lower and higher ID respectively. High ϕB is formed due to Fermi-level pinning and low ϕB is formed due to metal-semiconductor work function difference at the drain and source contact, respectively, which are shown in (c) and (d).

FIG. 2.

Transistor and transport characteristics (inset shows the linear plot) of the device showing effects of asymmetric ϕB [(a) and (b)], where for VD > 0 and VD < 0, we get lower and higher ID respectively. High ϕB is formed due to Fermi-level pinning and low ϕB is formed due to metal-semiconductor work function difference at the drain and source contact, respectively, which are shown in (c) and (d).

Close modal

In order to analyze the photoresponse of the WSe2 phototransistor, we consider separately both VD > 0 and VD < 0. We have lower ϕB at the drain contact and higher ϕB at the source contact, which can be inferred from the transport characteristics in Fig. 3(c). At first, we consider when VD > 0. In this case, when VG < 0, the transistor is On and majority carrier, hole injection occurs from the low ϕB drain contact by tunneling [Fig. 3(a) (I)]. Under illumination, generated electron-hole pairs are also separated effectively by the external electric field and contribute to photocurrent (Iph) which is added to IDark to give the total drain current under illumination, ID,ph = IDark + Iph. Here, the Iph generation process is due to the photoconductive effect. As a result, we have a high photoconductive gain which results in high Iph and thus high ℜ. When we increase VG, from the qualitative band diagram shown in Fig. 3(a) (II), it can be observed that the conduction and valence bands bend downward causing increase of tunneling barrier thickness, eventually which only allows thermionic emission of carriers instead of tunneling. As a result, both IDark and Iph decrease monotonically. At more positive VG [Fig. 3(a) (III)], IDark becomes very low as the amount of carrier injection from both contacts becomes very low due to the formation of barrier [Fig. 3(b)]. Iph also becomes small as photo-generated electrons are blocked and cannot be collected [Fig. 3(b)]. Moreover, at the Off state, we have two separate depletion regions of similar length for ϕB at drain (WD) and source (WS) contacts, WD WS. As a result, photo-generated holes are divided in two directions due to opposite electric fields at those depletion regions, resulting in further low net Iph [Fig. 3(a) (III)].

FIG. 3.

Modification of band diagram with respect to change in VG is shown for VD > 0 at (a); panel (b) shows transistor characteristics at dark and under illumination for VD = 1 V [the dashed red line shown in transport characteristics at (c)]. Here the filled and empty circles denote electrons and holes, respectively; black and red color represents electrically generated and photo-generated carriers, respectively. WD and WS denote the depletion regions of drain and source Schottky contacts, respectively. Similarly, panel (d) and (e) show modification of band diagram and transistor characteristics at dark and under illumination for VD = −1 V, which is marked in (f).

FIG. 3.

Modification of band diagram with respect to change in VG is shown for VD > 0 at (a); panel (b) shows transistor characteristics at dark and under illumination for VD = 1 V [the dashed red line shown in transport characteristics at (c)]. Here the filled and empty circles denote electrons and holes, respectively; black and red color represents electrically generated and photo-generated carriers, respectively. WD and WS denote the depletion regions of drain and source Schottky contacts, respectively. Similarly, panel (d) and (e) show modification of band diagram and transistor characteristics at dark and under illumination for VD = −1 V, which is marked in (f).

Close modal

On the other hand, when VD < 0, hole injection occurs from the high ϕB contact side [Fig. 3(d)]. Due to high ϕB, comparatively small IDark (about one order of magnitude smaller) is observed at the On state of the transistor [Fig. 3(e)]. Moreover, because of low photoconductive gain due to high contact resistance originated from large ϕB, ID,ph is also low at the On state [Fig. 3(d) (I)]. Interestingly, a peak in ID,ph is observed at a certain positive VG [Fig. 3(e)]. The origin of this peak can be explained by examining the band diagram. As shown in Fig. 3(d), for a certain VG > 0, the optimized gating condition is achieved, where photo-generated electron-hole pairs [Fig. 3(d) (II)] can be separated and collected most effectively to contribute maximum photocurrent due to minimized or no barrier at both contact ends. Also noticeable is that ID,ph is higher at the Off state [Fig. 3(e)]. In this case, at the Off state, we obtain a very large depletion region at the drain contact compared to that at the source contact, WD > WS. Under illumination, most of the photogenerated holes will be collected effectively at the drain contact by the internal electric field at WD and external electric field from VD. As a result, net Iph obtained from photogenerated holes is higher at the Off state in contrast to the previous case. Therefore, we obtain three times higher ID,ph at the Off state compared to the previous case (VD > 0).

We perform the same experiment on more devices with different transport characteristics depending on the strong/weak Fermi-level pinning effect, where we find that the above explanation also applies well. Device 1 is with two other Au contact electrodes of the same flake (∼50 nm) as Device 0 we examined above. Device 2 is based on a relatively thinner flake (∼12 nm); and Device 3 is a comparatively thicker flake (∼100 nm). Device 1 has higher ϕB at the drain contact and lower ϕB at the source contact [Fig. 4(a)]. So we observe similar behavior, a peak in ID,ph at VD > 0 and monotonic decrease of ID,ph at VD < 0 during gate modulation [Fig. 4(d)]. In Device 2, we observe high ϕB at both contacts [Fig. 4(b)] (strong Fermi-level pining at both contacts). Therefore, ID,ph peaks are observed for both VD > 0 and VD < 0 [Fig. 4(e)]. In Device 3, however, almost symmetric low ϕB contacts at both ends are attained [Fig. 4(c)], consequently no ID,ph peak is observed [Fig. 4(f)].

FIG. 4.

Effects of asymmetric Schottky contacts during gate modulation on different devices. The red circles in (a)–(c) denote the drain bias conditions of 3 devices for corresponding gate modulation shown in (d)–(f). The corresponding device images are shown at the top (scale bar: 10 μm).

FIG. 4.

Effects of asymmetric Schottky contacts during gate modulation on different devices. The red circles in (a)–(c) denote the drain bias conditions of 3 devices for corresponding gate modulation shown in (d)–(f). The corresponding device images are shown at the top (scale bar: 10 μm).

Close modal

Although trap induced asymmetric Schottky contacts in the WSe2 phototransistor have not yet been formed in a controlled manner in this study, one can obtain asymmetric Schottky contacts by work function engineering, i.e., using metal electrodes with two different work functions. High work function metals [e.g., gold (Au), palladium (Pd), etc.] and low work function metals [e.g., titanium (Ti), nickel (Ni), etc.] will form low and high Schottky barriers, respectively, for hole injection in the WSe2 field effect transistor, provided that there is no Fermi-level pinning. In order to prevent Fermi-level pinning, vacuum thermal annealing can be used to remove physisorbed adsorbates, which can generate trap states in WSe2. Therefore, it is possible to realize WSe2 phototransistors with asymmetric Schottky contacts, with control, via work function engineering. This feature of asymmetric Schottky contacts can be used to enhance the performance of the WSe2 phototransistor. An often evaluated FOM of the phototransistor, D*, is defined as following:4 

D*=×(AB)1/2/iN,
(1)

where A is the effective area of the photodetector, B is the bandwidth, and iN is the shot noise which contains IDark as the main noise source. Another important measure for the photodetector, the normalized photocurrent to dark current ratio (NPDR), is defined as below19 

NPDRIph/IDarkP=1NEP2qIDark.
(2)

In order to obtain high D* and NPDR, we need to attain low IDark and NEP. Therefore, we should operate the phototransistor at the Off state. The phototransistor can be operated at the On state, where high ℜ can compensate the necessity of low IDark.20 However, this will increase NEP and decrease NPDR, which will limit the capability to detect low power light. Using asymmetric Schottky contacts, it is possible to achieve higher Iph at the Off state. As a result, ℜ and NPDR of the phototransistor will be higher at the Off state. A similar technique has also been demonstrated previously for the silicon metal-semiconductor-metal (MSM) photodetector to suppress IDark and improve NPDR.19,21 Further, we can also properly apply the VG to operate the phototransistor near the peak of Iph to enhance ℜ and NPDR. Moreover, at the Off state, as most of the Iph is generated at the large depletion region near one of the contacts, we will attain a fast response time due to fast electron-hole separation by the electric field in the depletion region without being affected by the trap states. In summary, in order to achieve high D*, high NPDR, fast response and reasonable ℜ, we can operate the phototransistor with asymmetric contacts at the Off state and VD should be such that carrier transport occurs from the high ϕB contact end.

We now focus on the effects of defects or trap states on the photoresponse of the WSe2 phototransistor. As we increase the intensity of illumination, the ID,ph peak shifts towards higher VG [Fig. 5(a)]. This phenomenon can be explained by the photogating effect.4 Photogating is a special case of the photoconductive effect where holes/electrons are trapped in localized states and act as an effective local gate, modulating the resistance of the material. This effect is also found in studies on graphene and other TMDC photodetectors.22–25 Similarly, in the p-type WSe2 phototransistors here, with increasing illumination power, more photo-generated electrons are trapped at the surface trap states near conduction band minima which will act as the increasing negative gating voltage. The valence band will then bend a little bit upward [Fig. 5(c)], consequently, we need a little higher VG to achieve the gating condition for which photo-generated carriers will face no barrier. This explains why we observe the ID,ph peak shift with increasing optical power during gate modulation. Furthermore, sublinear photocurrent dependence on incident optical illumination confirms the existence of the photogating effect [Fig. 5(b)]. The number of available electron traps is reduced at higher illumination intensity, which eventually causes the decrease in the overall responsivity.26 We note that recently a similar type of photogating behavior was also reported for the black phosphorous mid-IR photodetector.26 

FIG. 5.

Effects of trap states showing shift of peaks in ID,ph (a), photocurrent dependence with intensity is presented in (b), the reason of this shift is explained by the photogating effect shown in (c) where the dashed blue lines show the band bending caused by the trap induced photogating effect.

FIG. 5.

Effects of trap states showing shift of peaks in ID,ph (a), photocurrent dependence with intensity is presented in (b), the reason of this shift is explained by the photogating effect shown in (c) where the dashed blue lines show the band bending caused by the trap induced photogating effect.

Close modal

In conclusion, we have demonstrated the effects of trap or defect induced asymmetric Schottky contacts on the photoresponse of WSe2 phototransistors during gate modulation. We have analyzed and illustrated the origin of peak in ID,ph during gate modulation by using band diagrams. Further, we discuss the possibilities of obtaining low noise WSe2 phototransistors with higher ℜ, NPDR values, and faster photodetection using asymmetric contacts compared to symmetric contacts. Finally, we have also demonstrated clearly the existence of photogating effect in WSe2 phototransistors.

We thank Jaesung Lee and Subrina Rafique for useful technical discussions. We acknowledge the support from the National Science Foundation CAREER Award (ECCS-1454570). Part of the device fabrication was performed at the Cornell Nanoscale Science and Technology Facility (CNF), a member of the National Nanotechnology Infrastructure Network (NNIN), and supported by the National Science Foundation (ECCS-0335765).

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