Electric field effect thermoelectric transport in individual silicon and germanium/silicon nanowires

The electronic properties of Si and Ge/Si nanowires (NW) have attracted considerable attention for applications in next generation field effect transistors (FET).^1–10 Unlike carbon nanotubes, Si based NWs can be synthesized with controlled diameters and doping levels for rational device design. Thermal and thermoelectric transport properties of these NWs are also of interest for potential use in thermoelectric power conversion applications. Thermal transport studies in Si NWs have shown that increasing the surface roughness¹¹ or the enhanced phonon-drag^11,12 can increase thermoelectric efficiency in Si NWs. The doping level of individual NWs can often be adjustable using the electric field effect (EFE) using the gate electrode in a field effect transistor (FET) device configuration. Since electronic properties of the NWs are sensitively dependent on the carrier density, thermoelectric power (TEP) thus can be adjusted by the EFE. For NWs made of narrow gap semiconductors, such PbSe and Sb₂Te₃, the EFE modulated TEP has been measured in the FET device configuration where a large modulation of TEP has been demonstrated electrical control of thermoelectric efficiency.^13–15 Recently, gate-modulated TEP, S, and electric conductance, σ, has also been measured in Ge/Si core-shell heterostructured NWs, where the optimization of the power factor, $σS2$ has been demonstrated employing the EFE.¹⁶ Extending the EFE modulated conductivity and TEP measurements on individual Si NWs in their subthreshold regime will enable us to optimize semiconducting nanostructures for thermoelectric applications. However, the relatively large channel impedance in the Si NW devices, especially near the turn-off regime of the devices, poses the experimental challenge of measuring thermoelectric signal simultaneously with the electrical conduction.

In this paper, we present an investigation of the EFE dependent electronic and the thermoelectric transport properties of both Ge/Si core-shell NWs and Si NWs in the temperature range of 80–300 K. For this study, we first demonstrated the reliability of the EFE by simultaneously measuring both conductivity and TEP using two lock-in amplifiers, operating at two different excitation frequencies. In the individual nanowire FET device setting, we found a large modulation of TEP as a function of applied gate voltages induced by the EFE. Substantially large peak TEP values up to $≳300 μ$V/K are observed in the subthreshold regime of the Si and Ge/Si devices, where the TEP can be experimentally measurable.

The Si NWs, used in this study, were synthesized using the vapor-liquid-solid method (VLS) described in detail elsewhere.^1,4 A typical diameters of the NWs are in the range of 20 ± 5 nm and the axial orientation NWs are in the [110] direction. During the growth, the NWs were doped with boron with a ratio of Si:B 8000:1. The Si NWs were subsequently suspended in ethanol and deposited onto a degenerately doped silicon substrate with 500 nm thermally grown SiO₂. The Si substrate back gate is capacitively coupled to the NW samples in order to modulate their carrier densities with the EFE. Electron beam lithography, metallization (2/40 nm Ti/Pd), and liftoff procedure are used to define the heater and microthermometer structures. The samples are dipped into HF acid for 5 s immediately prior to metallization in order to remove native oxide. Another semiconducting system we employed in this study are core-shell heterostructured Ge/Si NWs. This heterostructured NWs were chosen since they are known to provide highly conductive 1-dimensional hole gas at the core-shell interface.⁷ The details of the synthesis of the core/shell Ge/Si heterostructure NWs, with diameters in the range of 12 ± 2 nm, has been described previously.⁷ The fabrication procedure of the FET-style devices for the TEP measurement was similar to that for the Si NWs, except that the electrodes were made from 50 nm Ni. The thick layer of Ni electrodes are employed to contact the 1-dimensional hole gas by rapid thermal annealing essential for the elimination of a Schottky barrier due to the diffusion of Ni through the Si shell layer.

Conductance and TEP were measured in a vacuum cryostat, with pressure of $∼10−6$ Torr. The technique to simultaneously measure conductance and TEP has been previously used to measure carbon nanotubes,¹⁷ graphene,¹⁸ and nanowires.^14,19 A schematic diagram and a circuit diagram are presented in Figures 1(a) and 1(b), respectively. Since SiO₂ is ∼100 times less thermally conductive than Si, the Joule heat generated by the heater electrode is mostly dissipated into the Si substrate, as seen in the finite element simulation (we used the software package COMSOL) in Figure 1(a). A lateral temperature gradient forms because the device geometry is chosen such that the separation between the heater and the near electrode is on the order of the SiO₂ thickness. Since resistance $R∝T$⁠, where T is the temperature, in metals, the 4-probe electrodes act as microthermometers to measure the applied temperature difference, $ΔT$⁠. In the DC configuration, the thermally induced voltage $ΔVth$ was measured with a voltage amplifier to acquire the TEP, $S=−ΔVthΔT$⁠. The DC technique, however, is quite time consuming since at each gate voltage point the heater has to be swept in the wide range of the bias current to produce the appropriate temperature gradient.

In the AC configuration, shown in Figure 1(b), an AC voltage $Vh(ω1)$ is applied to the heater electrode. The temperature difference formed along the channel will be proportional to the square of that voltage; therefore, the resulting voltage will oscillate at $2ω1$⁠, with a $90°$ phase shift. The TEP is then $S=−2Vth(2ω1)ΔT$⁠, where the $2$ factor comes from the fact that the lock-in amplifier measures root-mean-squared values. For a consistency check, we make sure that the DC and AC configurations produce the same TEP values. The condition of linear response, $ΔT≪T$⁠, is always satisfied during the measurement in order to stay in the linear response regime. The conductance was measured using the standard 2-probe current biasing technique at ω₂. Both signals are measured simultaneously as the carrier density is changed in the NW with applied gate voltage, V_g.

We first discuss the results from highly conductive Ge/Si NWs. A typical room temperature, T = 300 K, gate dependent conductance, and TEP measurement of a Ge/Si NW are shown in Figures 2(a) and 2(b), respectively. A scanning electron microscope (SEM) image of a typical device is shown in the inset of Figure 2(b). Both conductance and TEP are modulated by the applied gate voltage, V_g.

For $Vg<0$⁠, the device exhibits high conduction, where two terminal conductance is in the order of ballistic conduction value $2e2/h$⁠, indicating high quality hole gas conduction.

For $Vg<0$⁠, the device exhibits high conduction, where two terminal resistance is $∼50$ kΩ, well below a typical input impedance of the voltage probe used in this experiment.

As a positive gate voltage is applied, the conductance decreases, and the device turns off. This p-type behavior is expected from the 1D hole gas at the interface of the Ge/Si core/shell heterostructure. For negative gate voltages, the TEP saturates to a constant value $∼120 μ$V/K. As this FET device turns off, the TEP begins to rise with a peak value of $≳350 μ$V/K, depending on the input impedance of the voltage probe employed. Figure 2(b) shows the difference that instrument input impedance makes on measuring TEP when the Fermi level is near or inside the gap of a semiconductor. Near the turn-off regime, the impedance of the device becomes high, and the voltage measurement across the channel becomes challenging. In order to investigate the effect of input impedance to the measured TEP values near the turn-off regime, we employed voltage preamplifiers with different DC impedance Z_DC and AC impedance Z_AC values, ranging from 0.01 GΩ to 1 GΩ. We found that, generally, the resistance of the NW channel R, defined from the 2-terminal conductance as $R=1/G$⁠, is on the same order as the input impedance of the measurement instrument, and the measured values of the TEP become unreliable. It was also found that the measured TEP was independent of the measurement frequency for $w1<100$ Hz.

The measurement of highly conducting Ge/Si NWs provides us a general insight about the gate dependent TEP measurements in NW FET devices. In the degenerate regime, when the Fermi level is far away from a band edge, thermal equilibrium is established quickly on the timescale of the measurement frequency. However, near the band edge, very few carriers participate in transport and the conductance is exponentially suppressed. The TEP rises when the Fermi level moves into the gap; however, the absence of adequate equilibration between the electrodes limits accurate measurement. In order to increase thermoelectric efficiency, both G and TEP have to be increased simultaneously; however, quite often the two parameters, as observed in our NWs, are inversely related.²¹ Similar observation has been reported in recent work of less conductive Ge/Si core-shell NW devices.¹⁶ 

We now turn our attention to the Si NW measurements. Figure 3(a) shows our main result, the gate dependence of the conductance, and TEP of a typical Si NW in the temperature range of 80–300 K. The FET is in the gate voltage region where the TEP becomes saturated for higher negative gate voltages. The height of the Schottky barrier E_SB (see lower inset in Figure 3(b)) that forms between the Si NW and the metal electrode interface is adjusted by the applied gate voltage. In the subthreshold regime, the conductance is drastically decreasing but still finite. In this regime, the mobility of the device is estimated from the transconductance $dG/dVg$ to be 17 cm²/V s from $μ=L2CgdGdVg$⁠, where L is the device length and C_g is the gate capacitance whose value can be estimated by the cylinder-on-plane model.⁷ Typical mobilities of measured samples vary between 0.1 and 20 cm²/V s. The FET will be turned off at positive V_g where the Schottky barriers deplete all available itinerant states in the valence band.

The total TEP in our mesoscopic size device is a contribution of the TEP from the bulk of the NW and from the Schottky barrier. In 1-dimensional systems, due to the poor electrostatic screening effect, the transport contribution from the Schottky barrier can be substantial.¹⁷ At negative gate voltages, the Schottky barrier becomes very thin and contributes negligibly to the TEP, which saturates to a constant value at each temperature. This saturation TEP scales linearly as a function of temperature with a slope of 0.68$μ$V/K², as shown in the upper inset of Figure 3(b), which signifies diffusive thermoelectric generation. In highly doped (⁠$>1018$ cm⁻³) bulk silicon, TEP as a function of temperature is linear, while only lightly doped samples show non-monotonic behavior due to the phonon-drag effects.²³ The TEP is positive, which is consistent with the p-type nature of this material since the sign of the TEP indicates the carrier type.²⁰ The carrier density can be extracted from the temperature dependence of the saturation TEP using the Mott relation^19,22

where k_B is the Boltzmann constant, $m*$ is the effective mass, and n is the carrier density. Using a parabolic dispersion relation with a hole effective mass⁶ of $m*=0.39me$⁠, the carrier density in the Si NWs is calculated to be $n≈1.4×1019$ cm⁻³. This density is within a reasonable agreement with the carrier density estimated from the electrostatic consideration with gate capacitance 19.5 aF/μm estimated from experimental geometry. As the Schottky barrier becomes wider in the subthreshold regime, thermally activated carriers hopping over the barrier contribute more to the overall measured TEP while carriers in the bulk contribute less. The peak values of the TEP at T = 300 K are $∼300 μ$V/K. These values are higher than $220 μ$V/K, measured in previous experiments of similar diameter Si NWs and doping levels in the suspended device geometry,^11,12 however, are lower than values measured in the bulk.²³ 

We have measured the gate dependence of conductance and TEP of individual semiconducting p-type Si and Ge/Si NWs in the temperature range of 80–300 K. High input impedance is essential to measure TEP accurately when the FET is off. We have found peak TEP values of $300 μ$V/K and $350 μ$V/K in Si and Ge/Si NWs, respectively, in the subthreshold regime. The linear temperature dependence of the saturation TEP in Si NWs is used to acquire the dopant density to be $1.4×10−19$ cm⁻³. Controlling the magnitude of the TEP using the EFE is essential in order to incorporate NWs into high efficiency thermoelectric power conversion devices and also for investigation of coherent and incoherent thermoelectric transport in disordered NWs.^24,25

This work was partially supported by the Korean Agency for Defense Development (ADD), under Agreement No. ADD-10-70-07-03. P.K. acknowledge the support from National Science Foundation (NSF) (DMR-1435487).