Vertically grown Ge nanowire Schottky diodes on Si and Ge substrates

Semiconductor nanowires (NWs) grown by either bottom-up epitaxial self-assembly or top-down etching have been studied now for over 20 years for a variety of applications ranging from ultra-scale electronics to nanophotonics and energy conversion.¹ One application of NWs which has not been well studied to date is the growth and fabrication of vertically oriented NW junctions and rectifiers that could be compatible with conventional planar CMOS technology. Such vertical structures could serve as functional interconnects in future three dimensional architectures,² providing a pathway for the continuation of Moore's law as scaling of planar circuits reaches its limit. Nanowires can utilize the vertical dimension to accommodate switching functionality, reducing the area utilized in the x-y plane. Arrays of vertical nanowires can serve as interconnects running between layers of planar circuitry carrying switching and logic functionality. They can also be used as unidirectional switches for phase change memory, photodetectors, selection devices for cross-point memories, bi-directional current flow devices for programmable metallization cells (PMC), and tunnel diodes for generation of microwave signals.

Previous studies of NW diodes have reported their performance as Schottky diodes, p-n junction diodes, tunnel diodes, light emitting diodes (LEDs), and as components of MOSFETs.^3–9 Due to strain relaxation in the lateral direction, heterojunction NWs may accommodate lattice mismatch much easier than planar heterojunctions, to realize for example, vertically standing AlGaN nanowire LEDs on Si substrates grown by molecular beam epitaxy (MBE).³ Tunnel diodes using vertically oriented p-n junction nanowires have been reported,⁸ exhibiting negative resistance with peak to valley current ratios > 4. Vertical NW MOSFETs have been fabricated as well, in which the effective gate length and charge control of channel is improved compared with planar structures.⁷ 

There have been several prior studies of the electrical behavior of NW Schottky diodes. Fermi level pinning at the metal-semiconductor interface of Ni/n-Ge vertical nanowire diodes was previously reported,^10–12 where it was shown that pinning is modulated by implantation of S atoms in the nanowires and laser annealing of the Ni/Ge interface. Non-ideal behavior has been observed in the I–V characteristics NW Schottky diodes compared to planar diodes relative to conventional thermionic emission theory. In previous studies by one of us (S. T. Picraux), Ge NWs were contacted using a scanning probe with a Au/W tip forming a Schottky contact,⁴ and the ideality factor of the NW diodes was found to increase non-linearly with the diameter in the sub 100 nm regime. Kim et al. reported very large ideality factors (17.8) in fits to the I-V data for Al Schottky contacts to a single GaN NWs using the standard thermionic emission model.⁵ In contrast, planar Schottky diodes between Ni and n-type Ge behave nearly ideally, with ideality factors close to unity, and a Schottky barrier height of 0.532 eV.¹³ From these preliminary studies on NW Schottky diodes, there is clearly a large difference in their performance compared to their bulk planar counterparts, which is not well understood at present.

In terms of the non-planer behavior, NW p-n junction diodes have demonstrated forward and reverse bias characteristics similar to planar diodes, but where the conductivity can also be modulated by the electric fields surrounding the diodes.⁶ The feasibility of an integrated circuit consisting of vertically oriented NW devices was demonstrated using Ge NW resistors fabricated on Si substrates with the ability to electrically address individual and multiple elements in vertical array configurations.¹⁴ 

In the present paper, we report on patterned arrays of vertically oriented, in-situ doped, n-type Ge NWs on Si and Ge substrates grown using vapor-liquid-solid (VLS) epitaxial growth and processed into Ni-Ge NW Schottky diodes, with the primary goal of realizing a process for fabricating vertical NW Schottky diodes in lithographically defined locations for the applications mentioned above. Further, we elucidate similarities and differences between the electrical characteristics of VLS grown NW Schottky contacts of various diameters and array sizes, compared with bulk planar ones. We focus on Ge NWs here, as the growth temperature of Ge as opposed to Si NWs is typically much lower, 360–375 °C for the structures grown here, compared to growth temperatures close to 550 °C needed for Si NWs.¹⁵ The lower growth temperature for Ge nanowires is preferable for integration into pre-fabricated planar CMOS circuits prior to interconnect metallization. Ni contacts were chosen as they make a good rectifying contact with n-type Ge.^16,17 We electrically characterized the diodes and then compare the current-voltage characteristics with analytical and numerical simulation of the devices to understand the differences in transport between planar and NW Schottky diodes.

In Sec. II below, we summarize the process for defining patterned Au catalyst seeds for VLS NW growth on Si and Ge substrates, including the results of VLS growth on both Si and Ge substrates. In Sec. III, we discuss the details of the process steps for fabricating vertical Ni/NiGe Schottky diodes. In Sec. IV, we then present current-voltage (I-V) measurements for different diode diameters and array sizes, while Sec. V reports the fit of these measurements with planar thermionic emission theory, including non-idealities, as well as full three-dimensional (3D) numerical Silvaco Atlas simulation of transport in NWs. Section VI then summarizes the results and conclusions from this study.

The fabrication of the Ni-Ge NW Schottky contacts studied here has two primary components: (a) template growth of vertically oriented Si and Ge nanowires with controllable diameters using Au catalyzed VLS self-assembly techniques and (b) the formation of Ni Schottky barrier contacts to the tips of the NWs. The process sequence is largely based on the existing literature on the subject with the addition of the following processes developed during the course of this investigation. First, we developed a process for etching the Ge nanowires using aqueous H₂O₂ solution to eliminate the thin shell of excess dopants near the sidewalls of the NWs. Second, we developed a recipe for encapsulation of the nanowires in spin-on-glass in order to isolate the NWs and make separate contacts to selected arrays of NWs. We found that this process was much more successful compared to using CVD SiO₂ for electrical insulation and mechanical polishing to expose their tips for contacting, which resulted in severe damage to the NWs. We also designed a new process for dry etching the excess SOG covering the tips of the nanowires, left after spin-coating, to make contacts to the devices at the top. The layout for the NWs is shown in Fig. 1(a), which was designed to perform current-voltage measurements on different diameter and numbers of NWs, ranging from single NW diodes to arrays of 40, 160, 240, and 400 devices. Four different diameters of nanowires are included in the layout of Fig. 1(a), d = 40, 60, 80, and 100 nm.

Arrays of vertical Ge NWs were fabricated on both Ge and Si substrates using VLS growth from Au metal catalyst patterns (see Fig. 1(b)). The metal catalysts defined by patterning PMMA using a JEOL JBX-6000F S/E electron beam lithography (EBL) system on Sb-doped n-type Si (111) and n-type Ge (111) substrates with similar resistivities of 0.01–0.02 Ω cm. Square windows with side dimensions of 40, 60, 80, and 100 nm were opened in the PMMA followed by thermal evaporation of an Au film and subsequent liftoff in acetone to form the growth catalyst arrays, as shown in Fig. 1(b). For growth on Si substrates, it was necessary to further pattern the window with an underlying silicon nitride mask layer to confine the catalyst laterally and prevent Au surface migration during NW growth. This process largely eliminated the horizontal diffusion, but also led to reduced nucleation yield for Ge NW growth on Si. We found an increased nucleation yield using the silicon nitride template when we changed the catalyst from pure Au to an Au-Ge alloy (88–12% wt.).

Nanowire growth was performed using the VLS growth technique, details of which are described elsewhere.¹⁸ Previous Ge NW growth studies by VLS on silicon substrates have primarily been in the context of lateral dispersed NW device structures.^19–22 Typical NW lengths for these growth times used were between 500 and 1000 nm long, with diameters ranging from 60 to 120 nm depending on the dimensions of the window region, and with a diameter approximately 20 nm larger at the base than the lithographically defined Au seed catalyst area, and with some tapering as seen in Fig. 1(d).

For Ge NW growth on Si substrates using the silicon nitride templates to confine the Au seeds, the nucleation of NW growth from the Au seed windows was low (<10%), with primarily non-vertical growth along the three equivalent inclined ⟨111⟩ orientations, as seen in Fig. 1(c). As mentioned above, we found much higher nucleation yields by changing the catalyst metal from pure Au to a Au-Ge alloy (88–12% wt.); however, inclined NW growth remained a problem. The inclined NWs thus result in a distribution of the NW tip locations around the EBL-patterned seed positions, making precise top contact positioning to the NWs challenging in the context of CMOS process integration

In contrast, for Ge (111) substrates, highly vertical n-type Ge nanowires were obtained with over 90% vertical NWs. No silicon nitride template was required on the Ge substrates as surface diffusion of Au was minimal, and pure Au seeds were employed. As can be observed in Fig. 1(d), some tapering is evident along the length of the NWs, here approximately 1 μm long. The difference observed between the diameter of the nanowire at the tip and at the middle is on the order of 8 nm, with the average diameter of the nanowires approximately 20 nm more than expected from the size of the Au catalyst particles, due to the increase in volume upon Ge alloying, and also indicating some vapor-solid Ge growth on the NW sidewalls. The Ge sidewall deposition with in situ n-type doping is enhanced by the phosphine, which creates a highly doped shell around the core of the device.²³ Our measured I-V characteristics support this conclusion, with Ohmic rather than rectifying behavior measured in the as-grown wires due to the heavily doped side-wall regions forming a shunt path along the circumference of the nanowire. We therefore included an additional process step to etch away the highly doped regions from the nanowire sidewalls. First, the Au catalyst at the tip of the nanowires was removed using a 9:1 solution of Transene TFA and hydrochloric acid as described elsewhere.²⁴ The sidewalls of the Ge nanowires were then controllably etched using a 0.5% aqueous solution of H₂O₂. This concentration gives an etch rate of approximately 0.5 nm/s reduction in the diameter of the nanowire. Surface tension, which can lead to breakage of the NWs at the conclusion of wet etching, was prevented by immersing the NWs into isopropanol (IPA) immediately after treatment with the aqueous H₂O₂ solution. The surface tension of IPA is lower than water such that it evaporates without damaging the NWs. Table I summarizes the diameters measured at the middle of the nanowires along their length in SEM images taken before and after the etching.

To fabricate Schottky diodes from the vertical NWs, we explored two approaches for dielectric encapsulation and planarization: (1) Plasma Enhanced Chemical Vapor Deposition (PECVD) of silicon dioxide followed by chemical mechanical polishing (CMP); and (2) spin-on-glass (SOG), which is self planarizing for nanoscale structures. For the first approach, we used a remote plasma system to deposit the oxide, which resulted in conformal deposition and the formation of hemispherical “bumps” at the tips of the NWs (see the SEM image in Fig. 2(a)). However, during the initial stages of CMP the “bump” structures tend to break off due to the shear forces rather than being polished in a planar way. This created deep (∼500 nm) depressions at the tips of the NWs and, in most cases, broke off the nanowire as shown in Fig. 2(b) (right) where a large void remains in the oxide layer where the nanowire was located.

The second approach using SOG proved to be more successful and straightforward to implement. Methylsilsesquioxane based Filmtronics 500F SOG was used for this purpose since it has low shrinkage on curing (∼2%) and has a high resistance to cracking. Low shrinkage prevents the NWs from being bent or broken, whereas resistance to cracking provides a uniform layer of oxide without any voids. Basically, the SOG was spun on at 3250 RPM, cured on a hot plate, and then loaded into a quartz furnace with nitrogen flow, and ramp up to 430 °C for 1 h. In order to ensure that the tip of the Ge NW was not covered with oxide, a 30 s etch-back was performed by reactive ion etching (RIE) in a CHF₃ and argon plasma. Approximately 50 nm SOG was etched from the sample during the etch-back exposing the tips of the Ge NWs for subsequent metal contact. The SEM images in Figs. 2(c) and 2(d) show the NW tips after spin coating the SOG and the RIE etch-back.

Once the nanowires were encapsulated and their tips were visible above the oxide layer, we used electron beam lithography (EBL) to pattern the metal contacts as illustrated earlier in Fig. 1(a). Nickel was deposited by DC magnetron sputtering to a thickness of 80 nm and lifted off by immersing the sample under acetone. The nickel contacts were annealed in two steps of 270 °C and 330 °C for 100 s each in a nitrogen ambient to form nickel germanide at the tips of the nanowires. The germanide is responsible for creating a potential barrier at the Ni-Ge interface and provides rectifying behavior.

Initial I-V measurements were performed on the Ni-Ge NW Schottky diodes without the H₂O₂ sidewall etch, as shown in Fig. 3(a), which appear nearly Ohmic. As mentioned earlier, we attributed this Ohmic behavior to the presence of a heavily doped layer around the circumference of the NWs, to which the Ni forms a tunnel junction Ohmic contact. To confirm this hypothesis, the H₂O₂ sidewall etch was employed and a second set of samples processed resulting in the diode like I-V characteristics shown in Fig. 3(b) for various array sizes of the 80 nm diameter NWs. Other NW diameters exhibited similar behavior. The number of NWs indicated in Fig. 3(b) is taken directly from the number visible in SEM images of the devices.

The 80 nm NW array with 20 nanowires in Fig. 3(b) has a current which is significantly smaller than the rest of the arrays, much smaller than the difference based on scaling of the number of nanowires visible from SEM micrographs. It is most likely that the number of conducting NWs is less than the number of visible ones due to contact issues.

In order to understand the electrical characteristics shown in Fig. 3(b), we fit the measured I-V characteristics of a variety of samples using thermionic emission theory. The standard expression for thermionic emission current in an ideal planar Schottky diode is given by²⁵ 

where A* is the Richardson constant, T is the absolute temperature, k is the Boltzmann constant, $ϕ$_B is the Schottky barrier height, V is the applied bias, and n is the ideality factor, which is unity in the ideal case.

Table II shows the parameters extracted by a least squares fit to the I-V characteristics for various NW diameters and arrays, assuming thermionic emission theory as described by Eq. (1), and including the effect of series resistance as well. As can be seen from Table II, the extracted Schottky barrier height varies between approximately 0.3 and 0.4 eV, which is substantially lower than the measured value in planar structures of 0.532 eV.¹³ In addition, the ideality factors extracted are close to 2, rather than 1, suggesting deviations from ideal thermionic emission behavior, which may explain the relatively low barrier heights extracted as well.

In terms of possible reasons for deviations from ideal thermionic field emission behavior, the first and most obvious cause of non-ideality is due to the non-uniform doping concentration along the radius of the wire, with heavier doping expected near the surface of the NWs compared to the core of the device.^26,27 The simplest way of modeling a highly conducting layer on the surface is with a shunt resistance (R_Sh) in parallel to the ideal diode. Including both series resistance (R_s) and shunt resistance (R_Sh), Eq. (1) is modified as follows:²⁸ 

where J₀ = $A*T2e−qϕBkT$ is the reverse bias saturation current from Eq. (1) above, and A is the cross-sectional area of the NW diode. In order to ascertain the potential effect of non-uniform doping along the surface of the nanowire on the ideality factor, the relation between R_Sh and n was investigated. A least squares fitting algorithm was again used to extract the values of J₀, R_S, R_Sh, and n in Eq. (2) using the measured current versus voltage. R_Sh is then varied manually, and the values of J₀, R_S, and n are extracted for this fixed value of R_Sh, as shown in Table III. The root mean square error of the fit is shown as well, which gives a qualitative estimate of how well a linear shunt resistance can account for deviations from ideal diode behavior.

Figure 4 shows the fitted and measured current for arrays containing 20 and 329 nanowire diodes to illustrate graphically how the rms error between the two increases as the ideality factor is forced to unity by reducing R_Sh. The summary presented in Table III shows that as the value of the shunt resistance is reduced, the ideality factor approaches unity, although the rms error increases as the quality of fit is deteriorated. This behavior at least qualitatively suggests that non-ideal behavior could be a result of a parasitic shunt path along the surface of the nanowire, although this only provides a partial explanation, as Fig. 4 shows that the fit becomes worse, particularly for the 329 wire case, as the shunt resistance is manually reduced. We also note that the value of R_Sh used to fit the arrays varies orders of magnitude between arrays, indicating that the behavior is more complicated than a simple linear shunt resistance.

Another possible source of a shunt path besides one due to doping inhomogeneities is the possibility that impurity charges due to the SOG process (fixed and mobile) near the surface of the NWs may induce surface inversion or at least high concentration at the surface. All of these explanations basically arise from the fact that the geometry of a NW Schottky diode is fundamentally different than a planar one. In the NW wire case, current flow can be highly nonuniform along the cross section of the NW. Second, the electric field due to voltage applied at the top contact of the nanowire diodes will have a tendency to directly modulate the concentration of charge carriers inside the device rather than through the Schottky barrier as the ideal thermionic emission model assumes.

In order to understand the role of geometry as well as trap and charge related effects on the surface of the NWs, we have used three-dimensional (3D) numerical simulation of NW transport based on the drift diffusion model using the Silvaco Atlas simulator. The device domain simulated is illustrated in Fig. 5, where a single Ge NW is simulated, assuming that the current voltage characteristics of individual NWs are independent of the other NWs in a given array. The top Ni contact is modeled as a Schottky contact with a diameter of 2 μm, while the NW is assumed to be cylindrical, with a diameter of 80 nm.

To simulate the non-idealities of the diode, we include acceptor-type traps on the Ge-SiO₂ interface. The traps are assumed to be mono-energetic with energy level 0.4 eV below the conduction band minimum. The acceptor-type trap density was 6 × 10¹⁰cm⁻². The capture cross-section was assumed to be 10⁻¹⁵ cm². A positive surface charge was also added to the Ge-SiO₂ surface with a density of 4 × 10⁹cm⁻², which results in accumulation of electrons on the surface of the NW which act in some sense like a shunt path. Figure 6 shows the comparison between the simulated and measured values, which is excellent. To compare to the 329 NW array, the output current of the Silvaco simulation was multiplied by 329, respectively. Simulations without the presence of traps and/or fixed surface charge gave more ideal behavior, with ideality factors close to unity, and a poor fit to the experimental data. Hence, the overall behavior of the NW Schottky diodes appears to be dominated by 3D effects associated with surface charge and acceptors, and the non-uniform field distribution along the wire length. A more detailed investigation of such 3D effects will be the subject of a future publication.

In this work, a process to integrate vertical Ge NWs into planar CMOS circuits has been demonstrated by growing NWs at lithographically defined locations of controlled diameter on Si and Ge substrates using VLS growth, and contacting to them from the top. Germanium NW growth on Si is largely non-vertical, while on Ge substrates, it is possible to grow vertically oriented, n-type doped Ge NWs at precise locations defined by electron beam lithography with high yield. As-grown n-type Ge nanowires appear to have a highly doped shell near the surface due to the vapor-phase incorporation of source and dopant atoms from the sidewalls, which results in Ohmic rather than Schottky behavior for the Ni contacts. This shell was removed by dilute H₂O₂ etching, so that the diameter is reduced to the edge length of the Au catalyst particles used to nucleate the nanowires. Etched nanowires with Ni/ nickel germanide contacts show rectifying behavior with a barrier height between 0.3 and 0.4 eV and ideality factors close to 2 when fit with the standard thermionic emission model. The ideality factor is reduced by the inclusion of shunt resistance attributed to a high concentration of carriers on the sidewalls of the NWs. However, a simple linear shunt resistance is insufficient to obtain a good fit overall, and full 3D numerical simulations show that surface effects on the diode to fixed charge and acceptor states can provide a good fit to the overall I-V characteristics, indicating that NW transport is dominated by 3D surface effects along the diode sidewalls.

The authors would like to acknowledge support for this work through the National Science Foundation through NSF Award No. 100133. This work was performed, in part, at the Center for Integrated Nanotechnologies, a U.S. Department of Energy, Office of Science User Facility at Los Alamos National Laboratory (Contract No. DE-AC52-06NA25396).