In order to gain further insight into the details of charge transport in organic semiconductor devices it is necessary to characterize the density of trap states at the semiconductor∕gate dielectric interface. Here we use the technique of gate bias stress to quantitatively determine the interface trap density in rubrene single-crystal field-effect transistors with two different types of interfaces. A reversible and reproducible shift of the IV characteristics is observed upon both negative and positive gate bias stress, whose physical origin is identified as charge trapping and detrapping at the crystal∕SiO2 insulator interface. We can thus quantify the density of interface traps that are alternately filled and emptied on a time scale of 1h in the energy range defined by the applied bias stress. For a typical rubrene∕SiO2 interface we extract a density of 2×1012cm2 at a stress bias of ±50V, corresponding to a volume density of 1019(cm3eV). An octadecyltrichlorosilane treatment of the SiO2 dielectric surface reduced this charge density by more than a factor of 2. The bulk trap density derived from space-charge-limited current measurements is typically three orders of magnitude lower, highlighting the dominant role in charge trapping played by the crystal∕dielectric interface.

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The difference between bulk and surface is also apparent if we choose a different way of comparing the two. The best rubrene single crystal shows a total volume trap density of 1015cm3, which corresponds to a density of 1010trapscm2, two orders of magnitude lower than the extracted interface trap density.

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