Wave-mechanical calculations of leakage current through stacked dielectrics for nanotransistor metal-oxide-semiconductor design

Quantum calculations of leakage current through ultrathin dielectric heterostructures are used to propose design criteria for the next generation of metal-oxide-semiconductor devices in a deep submicron technology. By using as input parameters both the dielectric constant and the barrier height of different dielectrics, including at first stage $SiO2,$ $Si3N4,$ $TiO2,$ and $Ta2O5,$ but also such emerging materials as $HfO2$ and $ZrO2,$ we show that, depending on the voltage range investigated, the hierarchy between those dielectrics is not simply given by the increase of their permittivity. Deeper considerations based on resonant tunneling mechanisms, of prime importance when dielectric heterostructures are used for fabrication purposes, must be taken into account especially for the future low-consumption nanotransistors with operating voltages below 1 V.