Dependence of transistor characteristics on the grain-boundary location in polycrystalline silicon (poly-Si) thin-film transistors (TFTs) has been analyzed using device simulation. In the linear region, degradation is similar wherever the grain boundary is located. On the other hand, in the saturation region, degradation is less when the grain boundary is in the pinch-off region near the drain edge and degradation is similar when the grain boundary is elsewhere. Although this dependence is similar to the dependence on the trap location in single-crystal silicon transistors, the mechanism is different. This dependence in poly-Si TFTs is because the coulombic potential barrier caused by the grain boundary is lowered in the high electric field in the pinch-off region. This is a kind of Poole–Frenkel effect.

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