Peripheral current analysis of silicon $p–n$ junction and gated diodes Available to Purchase

The peripheral reverse current $Ip$ in silicon $p–n$ junctions sets the leakage and standby power limits in modern integrated circuits. In order to study its origin more in depth, a detailed analysis of the reverse current through a gated diode is developed here. In particular, it is shown that the study of the reverse current component associated with the thick field oxide under depletion and inversion provides a sensitive tool. In addition, combining the gate bias dependence with the temperature variation of the reverse gated diode current allows us to identify its different components, namely, the diffusion $JpDIF,$ the depletion region generation $JpGENblk,$ and the surface generation current density $JpGENsrf.$ Based on this analysis, it is demonstrated that the peripheral diffusion current shows a remarkable increase with gate bias $VG,$ while for standard diodes an increase with the reverse voltage $VR$ is revealed. This bias dependence has to be taken into account when studying the activation energy of the diffusion and generation parts of the peripheral current. It is finally demonstrated that the proposed gated-diode analysis of the peripheral diode current is markedly more sensitive than analysis of the standard $p–n$ junctions with a large perimeter.