This paper describes a new approach for modeling bias-temperature instability (BTI) in nanoscale transistors. The model uses non-iterative surface potential solvers enhanced with dynamic defect potential equations to enable accurate, physics-based circuit level simulations that incorporate BTI effects. Defect maps constructed from experimental data reported on high-k-metal-gate bulk complementary metal-oxide-semiconductor devices are used to parameterize the defect potential equation. By implementing the enhanced surface potential model in Verilog-A, both DC and AC BTI aging effects in combinational circuits are simulated and the results compared conventional threshold voltage shift methods for BTI modeling.

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