We compute the contact resistances Rc in trigate and FinFET devices with widths and heights in the 4–24 nm range using a Non-Equilibrium Green's Functions approach. Electron-phonon, surface roughness, and Coulomb scattering are taken into account. We show that Rc represents a significant part of the total resistance of devices with sub-30 nm gate lengths. The analysis of the quasi-Fermi level profile reveals that the spacers between the heavily doped source/drain and the gate are major contributors to the contact resistance. The conductance is indeed limited by the poor electrostatic control over the carrier density under the spacers. We then disentangle the ballistic and diffusive components of Rc and analyze the impact of different design parameters (cross section and doping profile in the contacts) on the electrical performances of the devices. The contact resistance and variability rapidly increase when the cross sectional area of the channel goes below ≃50 nm2. We also highlight the role of the charges trapped at the interface between silicon and the spacer material.
References
The probability to find a dopant at a given point of the source is proportional to the background dopant concentration Nback shown in Fig. 2. A distribution of point charges Npoint is picked randomly and mixed with Nback near the edge z = zmin of the simulation box: N = α(z)Nback + [1 – α(z)]Npoint, where , with zmix = zmin + 4 nm and λmix = 0.66 nm.
can be slightly different from Vt defined in Section II C, as the former is based on a density criterion, and the latter on a current criterion.
The planar (001) FDSOI device used for comparison in Fig. 10 is a 8 nm thick Si film on a 25 nm thick BOX with the same gate stack and surface roughness parameters as the trigate devices (namely, Λ = 1.5 nm and Δ = 0.25 nm on the bottom interface with the BOX, and Λ = 1.5 nm and Δ = 0.35 nm on the top interface with the gate stack). The planar (110) FDSOI device is the same, but with Λ = 2.0 nm and Δ = 0.45 nm on both top and bottom interfaces. The planar (110) double-gate device is, likewise, a symmetric structure with a 8 nm thick film, and Λ = 2.0 nm, Δ = 0.45 nm on both interfaces.
