Correlation between stress-induced leakage current and dielectric degradation in ultra-porous SiOCH low-k materials

Stress-Induced Leakage Current (SILC) behavior during the dielectric degradation of ultra-porous SiOCH low-k materials was investigated. Under high voltage stress, SILC increases to a critical value before final hard breakdown. This SILC increase rate is mainly driven by the injected charges and is negligibly influenced by temperature and voltage. SILC is found to be transient and shows a t⁻¹ relaxation behavior, where t is the storage time at low voltages. This t⁻¹ transient behavior, described by the tunneling front model, is caused by both electron charging of neutral defects in the dielectric close to the cathode interface and discharging of donor defects close to the anode interface. These defects have a uniform density distribution within the probed depth range, which is confirmed by the observed flat band voltage shift results collected during the low voltage storage. By applying an additional discharging step after the low voltage storage, the trap energies and spatial distributions are derived. In a highly degraded low-k dielectric, the majority of defects have a trap depth between 3.4 eV and 3.6 eV and a density level of 1 × 10¹⁸eV⁻¹cm⁻³. The relation between the defect density N and the total amount of the injected charges Q is measured to be sub-linear, N ∼ Q^0.45±0.07. The physical nature of these stress-induced defects is suggested to be caused by the degradation of the Si-O based skeleton in the low-k dielectric.