Single transistor latch phenomenon in junctionless transistors

In this work, we report on the single transistor latch phenomenon in junctionless transistors. In the latch condition, the device is unable to turn-off despite a reduction in gate bias. It is shown that impact ionization induced latch condition can occur due to an increase in drain bias, silicon film thickness, gate oxide thickness, and doping concentration. The latch phenomenon is explained in terms of generation–recombination rates, electrostatic potential, electric field distribution and product of current density and electric field (J·E). As latch condition is undesirable for dynamic memory applications, the work highlights the significance of (J·E) as a performance metric to avoid the junctionless transistor being driven into the latch mode.