We report on the threshold voltage modeling of ultra-thin (1 nm–5 nm) silicon body double-gate (DG) MOSFETs using self-consistent Poisson-Schrodinger solver (SCHRED). We define the threshold voltage (Vth) of symmetric DG MOSFETs as the gate voltage at which the center potential () saturates to , and analyze the effects of oxide thickness (tox) and substrate doping (NA) variations on Vth. The validity of this definition is demonstrated by comparing the results with the charge transition (from weak to strong inversion) based model using SCHRED simulations. In addition, it is also shown that the proposed definition, electrically corresponds to a condition where the inversion layer capacitance () is equal to the oxide capacitance () across a wide-range of substrate doping densities. A capacitance based analytical model based on the criteria is proposed to compute , while accounting for band-gap widening. This is validated through comparisons with the Poisson-Schrodinger solution. Further, we show that at the threshold voltage condition, the electron distribution (n(x)) along the depth (“x”) of the silicon film makes a transition from a strong single peak at the center of the silicon film to the onset of a symmetric double-peak away from the center of the silicon film.
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15 July 2012
Research Article|
July 23 2012
Threshold voltage modeling under size quantization for ultra-thin silicon double-gate metal-oxide-semiconductor field-effect transistor
Aditya Sankar Medury;
Aditya Sankar Medury
a)
Centre for Nano Science and Engineering, Department of Electrical Communication Engineering
, Indian Institute of Science, Bangalore 560012, India
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K. N. Bhat;
K. N. Bhat
b)
Centre for Nano Science and Engineering, Department of Electrical Communication Engineering
, Indian Institute of Science, Bangalore 560012, India
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Navakanta Bhat
Navakanta Bhat
c)
Centre for Nano Science and Engineering, Department of Electrical Communication Engineering
, Indian Institute of Science, Bangalore 560012, India
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a)
Electronic mail: aditya.medury@ece.iisc.ernet.in.
b)
Electronic mail: knbhat@gmail.com.
c)
Electronic mail: navakant@ece.iisc.ernet.in.
J. Appl. Phys. 112, 024513 (2012)
Article history
Received:
May 02 2012
Accepted:
June 22 2012
Citation
Aditya Sankar Medury, K. N. Bhat, Navakanta Bhat; Threshold voltage modeling under size quantization for ultra-thin silicon double-gate metal-oxide-semiconductor field-effect transistor. J. Appl. Phys. 15 July 2012; 112 (2): 024513. https://doi.org/10.1063/1.4737779
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