Compact low-loss delay lines using a low-resistivity silicon substrate are designed and investigated in this paper. The studied lines have metal-insulator-semiconductor (MIS) substrate profiles. Substrate parameters such as layer thickness and resistivity are chosen in a way to allow for low-loss signal propagation in the slow-wave region. Subsequently, meander MIS microstrip lines are designed and their layout parameters are optimized to maximize the delay while maintaining the component area small.
REFERENCES
1.
J. U.
Knickerbocker
, P. S.
Andry
, L. P.
Buchwalter
, A.
Deutsch
, R. R.
Horton
, K. A.
Jenkins
, Y. H.
Kwark
, G.
McVicker
, C. S.
Patel
, R. J.
Polastre
, C.
Schuster
, A.
Sharma
, S. M.
Sri-Jayantha
, C. W.
Surovic
, C. K.
Tsang
, B. C.
Webb
, S. L.
Wright
, S. R.
McKnight
, E. J.
Sprogis
, and B.
Dang
, IBM J. Res. Dev.
49
, 725
(2005
).2.
R. R.
Tummala
, M.
Swaminathan
, M. M.
Tentzeris
, J.
Laskar
, G. K.
Chang
, S.
Sitaraman
, D.
Keezer
, D.
Guidotti
, Z.
Huang
, K.
Lim
, L.
Wan
, S. K.
Bhattacharya
, V.
Sundaram
, F.
Liu
, and P. M.
Raj
, IEEE Trans. Adv. Packag.
27
, 250
(2004
).3.
B.
Analui
and A.
Hajimiri
, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference
, 2003
(unpublished), p. 107
.4.
5.
A.
Khajooeizadeh
and R.
Abhari
, Proceedings of the Electrical Performance of Electronic Packaging (EPEP06)
, 2006
(unpublished), pp. 141
–144
.6.
Y.
Eo
and W. R.
Eisendstadt
, IEEE Trans. Compon., Hybrids, Manuf. Technol.
16
, 555
(1993
).7.
© 2008 American Institute of Physics.
2008
American Institute of Physics
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