We report the fabrication and characterization of gallium nitride (GaN) nanowire nonvolatile memory field-effect transistors (FETs). The memory device was implemented using a top-gate GaN nanowire FET with an oxide layer as a storage node. A thick silicon dioxide layer was embedded between the top metal gate and the nanowires, which was deposited using plasma enhanced chemical vapor deposition. Charges were stored in and released from the oxide layer by applying negative and positive gate biases, respectively. It is suggested that charge transport at the gate edge is responsible for the write and erase mechanisms. The locally enhanced electric field at the gate edge induces Fowler-Nordheim tunneling from the metal gate, while the much lower field near the interface between the oxide and the nanowire channel suppresses charge transport.
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15 July 2006
Research Article|
July 20 2006
Gallium nitride nanowire nonvolatile memory device
Ho-Young Cha;
School of Electrical and Computer Engineering,
Cornell University
, Ithaca, New York 14853
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Huaqiang Wu;
Huaqiang Wu
School of Electrical and Computer Engineering,
Cornell University
, Ithaca, New York 14853
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Soodoo Chae;
School of Electrical and Computer Engineering,
Cornell University
, Ithaca, New York 14853
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Michael G. Spencer
Michael G. Spencer
School of Electrical and Computer Engineering,
Cornell University
, Ithaca, New York 14853
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a)
Author to whom correspondence should be addressed; also at Micro & Nano Structures Technologies, GE Global Research, Niskayuna, NY 12309; electronic mail: [email protected]
b)
Also at Semiconductor R&D Center, Memory Business, Samsung Electronics Co. Ltd., Kiheung, Korea.
J. Appl. Phys. 100, 024307 (2006)
Article history
Received:
November 29 2005
Accepted:
May 17 2006
Citation
Ho-Young Cha, Huaqiang Wu, Soodoo Chae, Michael G. Spencer; Gallium nitride nanowire nonvolatile memory device. J. Appl. Phys. 15 July 2006; 100 (2): 024307. https://doi.org/10.1063/1.2216488
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