Experimental dc and small-signal ac drain-source characteristics are compared for power silicon carbide (SiC) metal-semiconductor field-effect transistors (MESFETs) fabricated on vanadium-compensated semi-insulating substrates, with and without a low-doped -type buffer layer. Device simulation is performed for the same device structures and simulated current distributions are analyzed together with the experimental data. MESFET transient output characteristics are found to be similar and controlled by carrier trapping in the semi-insulating substrate in both types of the devices at large gate voltages. The trapping was correlated with deep vanadium acceptors by gate-source and drain-source admittance spectroscopies, and gate-source deep level transient spectroscopy in the devices without the buffer, however, neither spectroscopic technique revealed any trap signatures in the devices with the buffer. Measurements of device output characteristics at different temperatures allowed confirming indirectly that trapping takes place at the vanadium acceptors in devices with the buffer similarly to devices without the buffer. Simulations confirm that injection of channel current into the substrate takes place in both types of the MESFETs at large gate voltages.
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It is interesting to note that Arrhenius plots corresponding to DLTS measurements are shifted compared to the plots corresponding to admittance spectroscopy measurements, meaning that the effective impurity ionization time constant is different in these two cases. Indeed, these two measurement techniques employ different impurity excitations; DLTS is a nonlinear nonequilibrium technique, while under admittance spectroscopy excitation the junction is in a quasiequilibrium state. The effective impurity time constants, which are an average of the corresponding local impurity time constants over the junction space charge region, are different in these two cases.
