CMOS on-chip thermometry at deep cryogenic temperatures

Heat is a common by-product of information-processing technologies.¹ Inefficiencies in the information conversion process have led to power dissipation densities approaching those inside a nuclear reactor core, compromising the chip integrity due to the elevated temperatures and as a result steering the development of modern computing technologies.^2,3 Quantum information processing technologies, although theoretically dissipationless, are also subject to these power dissipation challenges, particularly taking into account that useful quantum computers will require large numbers of qubits operating dynamically at microwave frequencies.^4–7 Moreover, the “classical” digital and analog electronics that are used for the control, addressing, and readout of quantum processors dissipate power like any conventional circuit. The majority of leading quantum processor platforms demonstrate optimum behavior at deep cryogenic temperatures (0.01–4 K), including superconducting,^8,9 spin,^10,11 trapped ion,^12,13 and photonic¹⁴ qubits, and hence, the goal of more tightly integrating the control electronics with quantum processors has motivated developing cryogenic integrated circuits (ICs).^15–18 

At these deep cryogenic temperatures, cooling power is orders of magnitude smaller,¹⁹ while the thermal conductivity of silicon and silicon oxide substantially reduce when compared to room temperature.²⁰ Therefore, cryogenic ICs require power management solutions and on-chip thermometry methods capable of monitoring hotspots across the chip operating at temperatures down to tens of millikelvin (mK).

A number of on-chip thermometry techniques have been adopted across the semiconductor industry. Silicon bandgap temperature sensing utilizes the temperature dependence of the voltage across a P-N junction in a bipolar junction transistor (BJT) at a given applied current—this is typically used in the $T = 30 − 500$ K temperature range; however, with a combination of advanced diode design and low bias current, improved sensitivity for temperatures approaching 1.5 K has been demonstrated.^21–24 Local thermal monitoring can also help determine the optimal chip biasing conditions at different temperatures. Silicided polycrystalline silicon (polysilicon) structures are also used as on-chip temperature sensors based on their temperature coefficient of resistance (TCR), which can be constant down to 50 K, but vanishes around 30 K²⁵ (depending on the silicide material). As silicided polysilicon is also often used in the gate stack of complementary metal-oxide-semiconductor (CMOS) processes, this allows for temperature measurement directly above a field effect transistor (FET) in a technique known as gate resistance thermometry (GRT).²⁶ This high degree of localization is especially important in ultra-thin-body (UTB) technologies such as silicon-on-insulator (SOI) and FinFETs, where oxide barriers below and/or on the sides of the UTB trap heat within the channel. GRT has been used to show that the temperature of a current-carrying transistor can be more than 10 K higher than that of other transistors on the same chip.²⁷ 

Here, we investigate four solutions for on-chip thermometry for CMOS ICs, which can be operated down to the mK temperature range relevant for many quantum technologies. We explore to what extent existing approaches can be adapted to operate in such conditions, in addition to studying new opportunities for thermometry that emerge at these low temperatures. In particular, we study how diode thermometry (DT) based on silicon P-N junctions and GRT perform even at temperatures below 1 K, well outside of their usual operating ranges, and we identify a method of superconducting phase transition thermometry (SPTT) based on the critical current of the superconducting thin films that are present as part of the CMOS process. Each of the above methods provides a secondary thermometer that requires calibration. We also present a primary method, quantum dot thermometry (QDT), based on tunneling conductance measurements through discrete energy levels of a quantum dot formed using the CMOS process. We first introduce the four different thermometry methods in Sec. II. Next, we present their operating principle and calibration procedure in Sec. III followed by a comparative benchmark in terms of sensitivity in Sec. IV. Finally, we utilize the four methods to measure excess on-chip heating in Sec. V and discuss the results in Sec. VI.

We first present the devices utilized for on-chip thermometry as well as describe the measurement setup [see Fig. 1(a)]. All devices are contained within a 3 × 3 mm² chip fabricated using a UTB SOI process from an industrial foundry. Most devices are placed in arrays, with each individual device addressable using on-chip multiplexing. We power up the chip using 0.8 and 1.8 V supplies resulting in static power dissipation during operation. We bond the chip to a printed circuit board (PCB) that sits inside a sample puck using silicon-doped aluminum bondwires. The puck is physically connected to the mixing chamber (MXC) of a dilution refrigerator with a base temperature of 20 mK. At the MXC stage, two thermometers are placed approximately 40 cm from the sample: a BlueFors ruthenium oxide and a PT100 platinum. These thermometers measure the MXC temperature (⁠ $T MXC )$ and can be used for temperature calibration (see Sec. VII A), but as we discuss later, the accuracy of the MXC thermometers to chip temperature is compromised by the physical separation, highlighting the need for on-chip temperature readings.

We start with silicon vertical diode structures, specifically the two varieties PNP (top) and NPN (bottom) shown in Fig. 1(b). Both structures use shallow trench isolation (STI) to define the junction. The PNP diode is forward-biased by applying a positive voltage to a highly doped P-type contact region relative to the voltage of the N-well directly beneath it, whereas the NPN structure is designed to operate with the opposite bias configuration. We use a constant current to forward-bias the diode, and measure the voltage between contacts 1 and 2 as a function of temperature, $V Diode ( T )$⁠. Unless otherwise stated, we use the NPN diode in the rest of the article.

Next, in Fig. 1(c), we show the layered structure of a polysilicon resistor commonly used in CMOS processes due to the stability of its resistance value at high temperatures. This example consists of a silicided highly doped N-type polysilicon layer on top of a thin adhesion layer of superconducting thin film on SiO₂. As discussed later, the superconducting layer transitions at a critical temperature $T C ≈ 1.2$ K. We probe the superconducting nature of the film using a 4-point measurement, enabling investigation of the dependence on temperature of the critical current, $I C ( T )$⁠.

A layered structure similar to the polysilicon resistor also forms part of the gate stack of an FET (length, L = 150 nm, and width, W = 2 μm) as seen in Fig. 1(d). We extract the temperature-dependent resistance of the gate using a 4-point measurement. For thermometry, we use the normal-state resistance $R gate ( T )$ above $T C$ and the critical current of the superconducting thin film below. This method provides the most local temperature reading of the corresponding FET.

Finally, we consider the FET in Fig. 1(e). Due to its small dimensions (L = 40 and W = 80 nm), the transistor can be utilized to trap individual electrons in an electrostatically defined quantum dot (QD) formed in the silicon channel directly under the gate electrode.^28,29 When operated at deep cryogenic temperatures near threshold, the silicon below the gate spacers is highly resistive due to the gradual drop of doping density from the Ohmic to the channel, effectively forming tunnel barriers between the source/drain reservoirs and the QD.³⁰ The line shape of the drain-source current vs gate-source voltage can be utilized as a local temperature sensor.^31,32

We now describe the calibration sequence for the different thermometers. We first calibrate DT to the MXC since the diodes can be measured without powering the auxiliary circuitry, minimizing the on-chip static power dissipation and, hence, allowing DT to closely track the MXC temperature down to 20 mK (see the calibration protocol in Sec. VII A). The remaining sensors are all measured through multiplexers, which require powering the additional circuitry leading to a minimum temperature of $T on ≈ 600$ mK. This figure does not represent a hard physical lower limit but is specific to the auxiliary circuit used here. Therefore, using $T MXC$ to directly calibrate the remaining sensors may lead to inaccurate readings. To increase the accuracy in the calibration, we use the diode to calibrate the remaining secondary thermometers, SPTT and GRT. Finally, QDT can be self-calibrated.

Next, we describe in detail the operation principle of all four different sensors.

Figure 2(a) shows an example of a PNP diode IV curve measured at $T MXC = 20$ mK, showing a typical exponential dependence of the current (⁠ $I Diode$⁠) with applied voltage across the junction (⁠ $V Diode$⁠). The threshold voltage of the junction is temperature-dependent, which effectively results in a change in $V Diode$ as the temperature is changed. Figure 2(b) shows this temperature dependence for a bias current $I Diode = 1$ nA. We select this low bias current as it minimizes self-heating while maintaining the precision of the measurement (⁠ $σ V / V Diode$⁠, where σ_V is the standard deviation) below 0.02% from 20 mK to room temperature, see bottom of Fig. 2(b). We note that significant temperature sensitivity is maintained down to 100 mK, outside the specified operating range of any commercial silicon diode thermometers.^22,23 This result may be due to the comparatively lower $I Diode$ used in this experiment or other factors such as doping concentrations and geometry. We calibrate the DT response to a weighted combination of the readings from the MXC ruthenium oxide and the platinum thermometer assuming perfect thermalization (see Sec. VII A).

Here, we use the critical temperature $T C$⁠, the critical current at zero temperature $I C ( 0 )$⁠, and the exponent i as fitting parameters. We find $I C ( 0 )$ = 7.95 ± 0.06 μA, $T C ( 0 )$ = 1.21 ± 0.01 K, and i = 0.44 ± 0.02. The form of $I C ( T )$ means it is most sensitive to T as it approaches $T C$ and by applying an out-of-plane magnetic field, the sensor's point of maximum sensitivity can be tuned (see Sec. VII B). We calibrate $I C$ to the diode temperature, making the SPTT a secondary thermometer. We also note that we use the SPTT in a complementary way to standard SPTT, where the sharp slope of the R − T curve at the superconducting-normal transition is used for sensitive thermometry over a narrow range of temperatures.³⁶ Finally, in the bottom panel, we show the precision as a function of $T DT$ which varies from 0.1% to 4% as the temperature approaches $T C$⁠.

We measure the resistance across the silicided gate structure of an FET by performing a 4-point IV measurement and using linear regression to fit the data as shown in Fig. 2(e). The resistance decreases with temperature as shown in Fig. 2(f), which is the expected result for a metal.¹⁹ The TCR is constant down to 50 K and then goes to zero at 30 K below which the resistance does not change. However, the layer of superconducting thin film transitions at $T C$ which is shown by a sharp drop in resistance below 1.2 K (the residual resistance is due to the metal-silicide contact which is part of the 4-wire measurement for the FET gate). The diamond points denote the normal resistance for a bias current above $I C$⁠, demonstrating that this is a superconducting transition rather than a normal resistivity change of the material. We calibrate the thermometer to the diode, making GRT a secondary thermometer. We note the precision in the resistance measurement $σ R / R$ is of the order of 0.01% in the normal state and deteriorates to approximately 1% in the superconducting region.

We first discuss the sensitivity of DT. The low-current-bias diode (⁠ $I Diode = 1$ nA, light blue trace) shows a sensitivity O(1 mK/ $Hz$⁠) from room temperature down to 300 mK before deteriorating due to self-heating of the sensor. However, a substantial sensitivity remains even down to the lowest measured temperatures. For comparison, we show a high-current-bias result (industry-standard current of $I Diode = 10$ μA, dark green trace) where the sensitivity start to deteriorate below 15 K. For the other measurement techniques, the chip needs to be powered on, setting a lower bound on the temperature that can be measured at $T on ≈ 600$ mK (black dashed line).

Next, we discuss the SPTT sensitivity for both the standalone polysilicon resistor (SPTT resistor) and the FET gate material (SPTT gate), below $T C$ (red dashed line). Just below $T C$⁠, the sensitivity presents a minimum due to the sharp derivative of $I C$ near $T C$⁠. However, as the temperature is reduced, the high error in the determination of the critical current close to $T C$ and the reduced derivative results in a local maximum. As the temperature is reduced further, σ_I is reduced and the sensitivity improves reaching an optimal sensitivity point. Finally, as the temperature lowers well below $T C$⁠, the sensitivity deteriorates due to the flattening of the $I C − T$ dependence. For temperatures below $T on$⁠, we use the fit to the modified Bardeen formula to extend the expected sensitivity which we indicate by the dashed extensions of the data. The sensitivity of SPTT in the FET gate material is generally worse than that of that of the standalone polysilicon resistor due to its lower resistance (due to the physical dimensions) and inclusion of contact resistances in its 4-wire measurements increasing the error in detection of the switching current transition. We also include the sensitivity of the normal-state resistances of each device, i.e., GRT gate and GRT resistor (regular resistance thermometry in the case of the standalone polysilicon resistor). Above 50 K, the sensitivity is stable at O(0.1 K/ $Hz$⁠) and deteriorates sharply below due to the saturation of the resistance by scattering crystal lattice imperfections.¹⁹ The sensitivity dependence with temperature is similar for both the polysilicon resistor (dark brown trace) and the FET gate material (cream-colored trace).

Finally, we discuss QDT. We note that since QDT is a primary thermometry technique, the observable is temperature, and hence, Eq. (3) reduces to $δ T = σ T / BW$⁠. The sensitivity is, therefore, determined by the standard deviation for a given measurement bandwidth. At high temperatures, $T ≳ 6$ K, the sensor's sensitivity is limited by the standard deviation of the measurement. Particularly, when the Fermi width approaches the applied source-drain bias (⁠ $3.5 k B T ≈ e V ds$⁠), the current passing through the device decreases, reducing the precision as well as the accuracy of the measurement. At intermediate temperatures (⁠ $1.5 − 6$ K), the sensor presents its region of optimal sensitivity O(1 K/ $Hz$⁠). At even lower temperatures, the sensitivity is limited by a combination of the elevated $T on$ and charge noise in the device. Furthermore, we must note that below 1.5 K, the sensor accuracy deteriorates, as described in Sec. III. The comparatively poor sensitivity of QDT with respect to the other methods is a consequence of the low bandwidth of the measurement (common to primary thermometers that require a functional fit to extract temperature^42–44) needing to acquire a full IV trace with relatively small currents (tens of picoamperes).

Having discussed the operation principles and benchmarked the sensitivity of the four different methods, we present a summary of the different specifications in Table I. Overall, we find that DT provides the most sensitive and wide-ranging method for on-chip thermometry, particularly when biased using a low current (1 nA). One of the reasons for this superior sensitivity is the high measurement bandwidth as only a single data point is utilized to extract the temperature reading. Bandwidth is reduced for other thermometry methods that require a series of data points to be acquired for valid fit of the data; this is particularly intensive for SPTT and QDT, both of which require a very fine step size in their IV curves to extract a precise temperature reading. With regard to the temperature range of operation, the physical mechanism for DT is robust in the range of temperatures studied. On the other hand, SPTT and QDT are limited in range due to the physical nature of their mechanisms. The normal-superconducting transition of the superconducting thin film, with a critical temperature of $T C ≈ 1.2$ K, sets an upper limit for the SPTT while the Coulomb blockade effect does so for the QDT. In the case of QDT, the elevated charge noise is a limiting factor at the low-temperature end. This limitation is not an intrinsic effect to QDT but rather to the particular technology of the sample. In the case of GRT, in its resistive form, a low-temperature limit exists (⁠ $∼ 30$ K) due to impurity scattering. Additionally, we compare the maximum self-heating, characterized here by the planar power density at the operation point of maximum dissipation in the temperature range of the sensor (see Sec. VII A). We find that DT, SPTT, and QDT present relatively low self-heating compared to GRT making them more suitable for low temperature thermometry as it was the case in this demonstration. Interestingly, DT performs best showing even lower self-heating than QDT despite the low power dissipation of the latter. In QDT, the power is highly concentrated at the location of the QD whereas the diode has a better surface power distribution. Finally, we note that although QDT presents an inferior sensitivity to DT (and SPTT below $T C$⁠), its primary nature allows for self-calibration without the need of a separate thermometer.

Having calibrated the different thermometers and described their specifications, we now measure locally the effects of on-chip power dissipation. To heat up the chip, rather than using the MXC heaters, we utilize on-chip diodes and FETs located at different distances from the actual thermometers (see Fig. 9 in Sec. VII F).

We first present local heating measurements using DT [see Fig. 4(a)]. We heat the calibrated NPN diode thermometer by driving a current through two other diodes located at distances of 60 and 240 μm. We observe a sublinear increase in the diode temperature with heater power, P, and a more pronounced increase for the 60 μm case, as expected. We observe a similar sublinear temperature increase with power for the SPTT, GRT, and QDT as we shall discuss later [Figs. 4(b) and 4(d)]. Additionally, in Fig. 4(a), we plot the MXC temperature at each power level (black dots) and plot it along with the on-chip temperature demonstrating the disparity between the two readings and underlining the need for on-chip thermometry. In this example, $T DT$ reaches a temperature higher than 1.8 K for the 60 μm case, whereas monitoring only the MXC (which remains below 50 mK throughout) would provide no indication of such on-chip temperature rise.

The term including the proportionality constant α represents the joint effects of the varying metal thermal conductivity and MXC cooling power with temperature. Overall, the term presents a square root dependence of the sensor temperature with applied power. On the other hand, the terms preceded by the fitting constants $β h$ and $β s$ represent, respectively, the effect of the heater power and the background power on the sensor temperature via the insulating materials. In this case, a fourth root dependence is observed.

We now look more closely at SPTT. A PNP heater diode is approximately 2.2 mm from the polysilicon resistor structure, allowing a similar experiment to be conducted using the critical current of the superconducting structure across different power levels as shown in Fig. 4(b). This method can only be used while the chip is powered up, and hence, the temperature range is limited to values between $T on$ and $T C$⁠. A fit to Eq. (5) reveals an $α SPTT = 130 ± 20$ K W^−1/2 and $T 0 SPTT = 597 ± 13$ mK, the latter in close agreement with $T on$⁠.

When performing GRT, the FET remains fully operational and, given the close distance from the channel of just a few nanometers, the experiment can effectively be considered a self-heating test. To vary the power dissipated in the channel, we sweep $V ds$ at fixed $V gs$⁠. For small power dissipation, we use the superconductivity of the gate stack, effectively an SPTT measurement which for the purpose of differentiation we refer to as superconducting GRT (SGRT). We show the resulting points below 1.2 K in Fig. 4(c). From the fit, we find $α SGRT = ( 7.2 ± 1.5 ) × 10 3$ K W^−1/2, and $T 0 SGRT = 583 ± 12$ mK due to on-chip power dissipation of the auxiliary circuitry, as discussed above. For higher powers, the gate temperature increases to the point where the normal resistance of the silicide layer becomes temperature-sensitive, as shown in the points above 30 K. Here, we find $α GRT = ( 2.46 ± 0.02 ) × 10 3$ K W^−1/2 and $T 0 GRT = 25.7 ± 1.3$ K. The lower α, compared to that of the superconducting layer, is at least partially a consequence of the larger separation between the silicide layer and the channel. The extracted $T 0 GRT$ is within the range in which TCR tends to zero. The technique shows sensitivity to the most extreme levels of on-chip heating allowing self-heating characterization across 6 orders of magnitude in dissipated power with a dead zone in between. More particularly, we see that the FET gate temperature exceeds 1 K with just a few tens of nanowatts and reaches nearly 100 K with 1 mW of power dissipation.

Finally, we discuss QDT. To heat up the QDT, we use another identical FET placed parallel to the QDT at an edge-to-edge distance between channels of 100 nm. We drive a current through the FET by using a constant $V gs$ and variable $V ds$ resulting in a static power dissipation of up to 1 μW. Again, we observe a sublinear increase in temperature as a function of power well-modeled by Eq. (5). We find $α QDT = ( 8 ± 2 ) × 10 3$ K W^−1/2 indicating a higher degree of sensitivity to power dissipation than SGRT despite the higher locality of the latter. The reason for the larger α could be associated with the larger power density produced in the FET channel heating the QD (recall $W × L = 80 × 40$ nm) than in the FET used in the GRT experiments (⁠ $W × L = 2000 × 150$ nm).

Overall, the measurements presented in this section demonstrate the capability of the four different sensors to measure local excess heating well above the temperatures detected by the thermometers at the MXC. These results highlight the major importance of on-chip thermometry when assessing local temperature hotspots since they provide a much more accurate reading of the true chip thermal environment and shed light on the cooling mechanisms playing a role.

The performance of solid-state quantum computers and cryo-electronics microcircuits is closely linked to the temperature of their environment. Understanding, hence, what the local temperature is in dynamically operated circuits and architectures is of primary importance. Here, we have introduced and benchmarked four different methods for local on-chip thermometry native to CMOS technology such as they could be seemingly integrated in scaled-up circuits. We find that DT, particularly when biased with a low current (1 nA) is the most sensitive method when compared to GRT, SPTT, and QDT for the whole temperature range studied (20 mK–300 K). Particularly, the low current bias technique enables sensitive thermometry well below 1.5 K, the common lower limit for commercial cryogenic diode thermometers. We envision that the sensitivity of the DT technique could be improved further by operating the sensor in conjunction with fast readout techniques.⁴⁷ Such an approach could surpass state-of-the-art thermal sensitivity figures^48,49 while remaining compatible with industry-standard fabrication processes and may enable the study of thermal dynamics at deep cryogenic temperatures in the microsecond timescale.

Apart from the diodes, all the structures used in this study required powering up the additional digital and analog circuitry to enable access through the cryogenic multiplexers. The power used by the support circuitry consumes 4.3 μW and raises the on-chip temperature above that of the MXC temperature. To extract the base chip temperature when the support electronics were active, $T on$⁠, we used DT.

In discussing Fig. 2(b), we described the calibration procedure of the DT to the MXC thermometer which we now use to calibrate $T on$⁠. Specifically, we use the diode at 1 nA forward bias current and measure the temperature, $T DT$ as a function of $T MXC$ (see Fig. 5). We fit $T DT = T MXC 2 + T on 2$ and extract $T on$ = 631 ± 24 mK. We conclude that the static power dissipation raises the chip temperature above the reading of the MXC thermometers highlighting the necessity of placing thermometers on chip. We make the assumption that the diode is perfectly thermalized to the MXC when the chip is powered off and that all on-chip thermometer structures are at the same temperature when the digital and auxiliary circuitry is powered up and no other heat sources are applied. Each of the on-chip thermometer structures is a similar distance from the digital circuitry at the center of the chip where the majority of the power is dissipated when the chip is powered, but the distribution of devices and auxiliary circuitry across the chip still leads to some level of error. Nevertheless, it provides a much more accurate picture of the chip temperature than direct readings from the MXC thermometer. A more advanced version may benefit from creating an array of thermometers to extract a thermal image of the powered-on chip.

We briefly dwell on the assumption of perfect thermalization of the diode to the MXC when the rest of the chip is powered off. The ∼1 nW being dissipated in the diode results in some level of self-heating. The method is still useful, as the goal of a thermometer is often not to actually measure its own temperature but rather to provide an estimate of the temperature of its immediate surroundings based on the effect to its own temperature, for which the assumptions still hold well enough down to ∼100 mK given the finite sensitivity of the sensor (i.e., the real assumption is that the region surrounding the diode is well thermalized to the MXC). With this understanding, we estimate the actual diode temperature due to self-heating with the MXC at base temperature. The data from the inset of Fig. 2(b) is reproduced in Fig. 6 for this purpose. Assuming the voltage deviation from the linear behavior at the low-temperature end of this plot is due to diode self-heating, a linear regression can be applied to the data in the ∼0.75–1+ K region (in which the diode appears to be thermalized and follow the theoretical behavior) to describe the diode voltage vs diode temperature. The temperature at which the observed diode voltage at MXC base temperature intersects the linear regression is the minimum diode temperature due to self-heating; in this case, the estimated value is ∼400 mK.

Without excellent models of cryogenic material properties and very detailed knowledge of the device structure (often not possible with commercial foundry processes), one cannot exactly quantify the self-heating in the material in which power is dissipated for most of the other discussed techniques. We suggest a figure of merit for comparing relative self-heating among the techniques: the planar power density (see Table I). Even for SPTT where no power dissipation takes place in the sensitive material, there is still a small amount of heating in the normal materials in the structure as noted in the table. Additionally, heating within contacts and routing very near the devices contributes to the actual device temperature.

These equations can be combined to fit critical current data across a wide range of temperatures and magnetic fields. The equations use as fitting parameters: the critical out-of-plane magnetic field at zero temperature $B C ⊥ ( T = 0 )$⁠; the critical current and temperature at zero magnetic field, $I C ( B ⊥ = 0 )$ and $T C ( B ⊥ = 0 )$⁠; and B₀ which is a macroscopic materials parameter based on a Kim-Type fit.⁵⁰ Based on the equations, we see that an increase in the out-of-plane magnetic field leads to a decrease in the critical current and the critical temperature. This decrease in critical temperature shifts the region of optimal sensitivity of the technique to lower temperatures, showing how the optimal sensitivity of the SPTT can be tuned using external magnetic fields.

In Sec. IV, we use the bandwidth-normalized sensitivity to benchmark the different thermometers. This ensures that the link between standard deviation of the measurement and integration time is taken into account. Here, we describe the details of the measurement bandwidth of each method used to quantify the sensitivity.

For DT, we use an integration time of 20 ms per point resulting in a measurement bandwidth of 50 Hz. For SPTT and GRT (and resistance measurements in general), we use 20 ms integration time for each point and take a 5 ms settling time between points. The bandwidth for these techniques is, therefore, $B W = 1 N * 25 ms$⁠, where N is the number of points (9 for resistance measurements and variable for critical current measurements depending on step size and critical current magnitude). The determination of the resistance measurements from a set of points rather than single point measurements ensures that temperature variations in the chip leakage currents do not affect the resistance reading. Finally, for the Coulomb blockade measurements the bandwidth is 0.1 Hz, as each peak trace acquisition takes 10 s before it is then fit to extract the temperature.

The variability-based precision figure plotted in Fig. 3 indicates the amount of information conveyed by a single iteration of a measurement procedure. A smaller precision means that a single measurement conveys more information (lower uncertainty of the center value of the distribution that would be obtained from multiple measurements). This is different from measurement accuracy for which an exact knowledge of the true value to be measured is needed.

We explore the different contributions to precision for the different sensors. For DT, the suspected primary contributors are current source inaccuracy (0.035% + 600 pA), current source noise (∼5 pA p-p 0.1–10 Hz), voltage measurement inaccuracy (0.012% + 300 μV), and additional noise from stray EM signals picked up by cabling or otherwise coupled to the system. Similar sources of error apply to the other measurement techniques, but additional factors dominate in those cases. For GRT, a source-measure unit (SMU) was used in 4-wire voltage-source current-measure mode. However, the inline resistances on the source and measurement lines are beyond the rated maximum values of the instrument for 4-wire mode, meaning instrument datasheet accuracy values are no longer valid and are likely significantly degraded, specifically regarding the applied voltage at the actual device terminals. This is suspected to be the leading factor limiting precision for GRT.

For SPTT, the observed variation of the switching current as shown across ten iterations of measurements in Fig. 7 is of significantly larger magnitude than expected instrument inaccuracies, implying the inherent stochastic nature of the device switching current is a leading source of inaccuracy. Additionally, since SPTT relies on detecting a hysteretic transition, it is more sensitive to noise-induced current spikes which may also play a significant role. As for QDT, the primary precision-limiting factor is charge noise. It is the same physical mechanism that limits the low end of the temperature range to ∼1 K. In this context, this manifests itself in fluctuations from trace to trace which cause the fitting function to give a spread of values. In our measurements, we take 20 traces and use the standard deviation of these values as the precision in our measurements.

To calibrate the QDT sensor, we need to accurately estimate the gate lever arm $α g$⁠. This factor translates the applied gate voltage to an energy scale of the QD. We obtain $α g$ from the width of the Coulomb oscillation in gate voltage $( Δ V g )$ at a fixed $V ds$ of 2 mV. The width in gate voltage is accurately fit using the Fermi-based current formula in Eq. (2) leading to $α g = V ds / Δ V g = 0.91 ± 0.15$⁠.

In the top panel of Fig. 8, we plot the uncalibrated (black dots) and calibrated measurements (mustard dots). The ratio between the points is given by the constant $α g$⁠. Furthermore, in the bottom panel, we calculate the fractional accuracy of the calibrated data defined as $( T cal − T MXC ) / T MXC$⁠. At the lowest temperature, the sensor reading deviates from the MXC reading due to charge noise. Above ∼7 K, the accuracy starts to increase again as the level-splitting in the QD becomes smaller than the thermal energy.

On the left-hand side of Fig. 9, we show an optical image of the chip used for these experiment. The chip is bonded to an FR4 PCB using Al:Si (1%) bondwires. To the right, we show a diagram indicating the approximate location of the different thermometers and heaters.

The devices used for GRT, SPTT, and QDT are accessed via on-chip multiplexers as shown in the schematic in Fig. 10(a). To access a single device under test (DUT), the registers containing the row_en and col_en information are written such that each has only a single bit high, enabling access to the device at the corresponding x-y position in the layout in Fig. 10(b).

Several metal contact points occur along the path represented by $R m$⁠, namely, mixing chamber plate to puck head, puck head to puck rails, and puck rails to PCB. The thermal resistance of the contact points is complex to model, as their thermal conductivities likely scale with temperature raised to the power of some unknown value in the range 0.75–2.5.⁵² For simplicity, we ignore the thermal contact resistance in this model and note that all contact points are Au-plated and were fastened as tightly and with as much surface area as possible to minimize the effects of thermal contact resistance in measurements. As we see in Fig. 4(a), this approximation does not hinder the quality of the fit.

Additionally, in Fig. 11(b), we plot the diode temperature vs heater power for different thermometer-heater separations. We fit the data to Eq. (12), considering $P s → 0$ W, to extract the thermal coefficients α and $β h$ and plot them in Fig. 11(c). We see a decay of the values as d is increased consistent with the reduced heat transfer efficiency at larger distances.

Finally, in Fig. 12, we show a comparison of quality of the fits to the heating data using the advanced model, including the effect of the insulating materials [Eq. (4)], and the simplified model [Eq. (5)]; see panels (a)–(h), respectively. In Table II, we compare the quality of the fits through $χ 2$⁠. We observe that the diode data benefits from including the contribution of the insulating materials, whereas for the rest of the thermometers (SPTT, GRT, and QDT) can be well fit by the square root dependence.

Figure 13 gives a more detailed diagram of the measurement setup used for the experiments described in Sec. II. Digital control equipment, power supplies, and low-noise SMUs are all connected to a breakout box that is connected to the top of a Bluefors XLD dilution refrigerator through shielded cables. These signals are then carried by PhBr twisted pairs to the MXC of the dilution refrigerator. At each temperature stage, the twisted pairs are thermalized and furthermore at the MXC stage the signals pass through a set of QDevil RC and RF filters before reaching the PCB and sample. We performed conventional thermometry and heating using a Bluefors temperature control unit combined with Bluefors ruthenium oxide and platinum thermometers and a heater, respectively, all attached to the MXC plate. The DC lines used for conventional thermometry are the same as those described above for the experimental setups. We glue the sample to a PCB (FR4, 0.8 mm thick, Au-plated Cu) using silver paste. We use two different PCB designs with nominally identical properties (see Fig. 13). The device is bonded to the PCB using 25 μm diameter Al:Si bondwire and the PCB is screwed onto a Au-plated copper bracket inside a sample puck that attaches to the bottom of the MXC plate.

All authors acknowledge Jonathan Warren and James Kirkman of Quantum Motion for their technical support during this work. T.H.S. acknowledges the Engineering and Physical Sciences Research Council (EPSRC) through the Centre for Doctoral Training in Delivering Quantum Technologies (Grant No. EP/S021582/1). M.F.G.Z. acknowledges a UKRI Future Leaders Fellowship (Grant No. MR/V023284/1).

Yes, the authors declare a relevant patent application: European Patent Application No. 23157647.1.

Grayson M. Noah, Thomas H. Swift, and Mathieu de Kruijf contributed equally to this work.

Grayson M. Noah: Formal analysis (equal); Investigation (equal); Validation (equal); Writing – original draft (equal); Writing – review & editing (equal). Thomas Hugh Swift: Formal analysis (equal); Investigation (equal); Writing – original draft (equal); Writing – review & editing (equal). Mathieu De Kruijf: Formal analysis (equal); Investigation (equal); Writing – original draft (equal); Writing – review & editing (equal). Alberto Gomez-Saiz: Methodology (equal); Writing – review & editing (equal). John J. L. Morton: Conceptualization (equal); Writing – review & editing (equal). Miguel Fernando Gonzalez-Zalba: Conceptualization (equal); Formal analysis (equal); Investigation (equal); Supervision (equal); Writing – review & editing (equal).

The data that support the plots within this paper and other findings of this study are available from the corresponding author upon reasonable request.