Synaptic transistors, which emulate the behavior of biological synapses, play a vital role in information processing and storage in neuromorphic systems. However, the occurrence of excessive current spikes during the updating of synaptic weight poses challenges to the stability, accuracy, and power consumption of synaptic transistors. In this work, we experimentally investigate the main factors for the generation of current spikes in the three-terminal synaptic transistors that use LiCoO2 (LCO), a mixed ionic-electronic conductor, as the channel layer. Kelvin probe force microscopy and impedance testing results reveal that ion migration and adsorption at the drain–source-channel interface cause the current spikes that compromise the device's performance. By controlling the crystal orientation of the LCO channel layer to impede the in-plane migration of lithium ions, we show that the LCO channel layer with the (104) preferred orientation can effectively suppress both the peak current and power consumption in the synaptic transistors. Our study provides a unique insight into controlling the crystallographic orientation for the design of high-speed, high-robustness, and low-power consumption nano-memristor devices.

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