Ferroelectric field effect transistors (FeFETs) have attracted attention as next-generation devices as they can serve as a synaptic device for neuromorphic implementation and a one-transistor (1T) for achieving high integration. Since the discovery of hafnium–zirconium oxide (HZO) with high ferroelectricity (even at a thickness of several nanometers) that can be fabricated by a complementary metal–oxide–semiconductor-compatible process, FeFETs have emerged as devices with great potential. In this article, the basic principles of the FeFET and the design strategies for state-of-the-art FeFETs will be discussed. FeFETs using Pb(ZrxTi1−x)O3, polyvinylidene fluoride, HZO, and two-dimensional materials are emphasized. FeFETs, ferroelectric semiconductor field effect transistors, and metal–ferroelectric–insulator–semiconductor structures to which those materials can be applied are introduced, and their exotic performances are investigated. Finally, the limitations of these devices’ current performance and the potential of these materials are presented.

The demand for machine learning and deep learning has increased as artificial intelligence (AI) technology is used throughout society. Due to this trend, there is a need for a device that has both the fast operating speed of the dynamic random access memory (DRAM) and the nonvolatile characteristics of the NAND flash memory.1,2 Accordingly, attempts have been made to break away from the existing von Neumann computer architecture, where the storage space and the computational processing space are separated.3–5 In response to these demands, ferroelectric field effect transistors (FeFETs) have received attention for next-generation FET devices because of fast operation speed, low power requirements, and non-destructive read capability as a memory device. FeFETs that exhibit the characteristics of nonvolatile memory (NVM) and synaptic devices are an essential element for implementing high-integration circuits and neuromorphic computing.6,7 The 1T structure using the FeFET, which can serve as both a switch and memory, was first proposed in 1995, as illustrated in Fig. 1, as the MEM transistor.8,9 This 1T structure allows the circuit to achieve higher density in a situation where the limit of integration degree is reached.10 Furthermore, a multi-level current flows between the source and the drain (Isd), and a synaptic weight (SW) can be formed by controlling the gate voltage pulse of the FeFET. It plays a critical role in neuromorphic computing [Figs. 1(e) and 1(f)].11 Since Valasek et al. discovered the ferroelectricity of Rochelle salt in 1920, Moll and Tarui first proposed the concept of the FeFET using triglycine sulfate (TGS) in 1963.12,13 After that, FeFETs using various ferroelectric materials have been manufactured, and this has shown better low power driving and faster read/write speed than DRAM, static RAM (SRAM), and flash memory. However, compared to the resistive RAM (RRAM) and phase-change memory (PRAM), the retention and endurance capabilities are lower, limiting application and utilization as devices.14 However, in recent years, FeFETs using HfO2 doped with ZrO2 as ferroelectric insulator layers have provided solutions to the polarization effect,15–17 charge injection, and leakage current (in the form of La-doped Hf0.5Zr0.5O2)18 caused by the conventional low film thickness, and research on the FeFET is being actively conducted once again.14,18 (Table I).

FIG. 1.

Ferroelectric materials for the FeFET. (a) Hf0.5Zr0.5O2. Reproduced with permission from Park et al., J. Mater. Chem. 5, 4677 (2017). Copyright 2017 The Royal Society of Chemistry. (b) PVDF. Reproduced with permission from Chen et al., Adv. Electron. Mater. 3, 1600460 (2017). Copyright 2017 WILEY-VCH Verlag GmbH & Co. KGaA. (c) Pb(ZrxTi1−x)O3. FeFET applications. (d) MEM transistor capable of programming and erasing. (e) Synaptic transistor. Reproduced with permission from Chen et al., Adv. Electron. Mater. 6, 2000057 (2020). Copyright 2020 Weinheim, WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim. (f) Realization of neuromorphic behavior through low power and high mobility. Reproduced with permission from Lee et al., Nat. Commun. 11, 2753 (2020). Copyright 2020 the Author(s) 2020, licensed under a Creative Commons Attribution 4.0 International License. Other structures using ferroelectric semiconductors. (g) Ferroelectric semiconductor-field effect transistor (FeS-FET). (h) FET using the ferroelectric semiconductor and insulator.

FIG. 1.

Ferroelectric materials for the FeFET. (a) Hf0.5Zr0.5O2. Reproduced with permission from Park et al., J. Mater. Chem. 5, 4677 (2017). Copyright 2017 The Royal Society of Chemistry. (b) PVDF. Reproduced with permission from Chen et al., Adv. Electron. Mater. 3, 1600460 (2017). Copyright 2017 WILEY-VCH Verlag GmbH & Co. KGaA. (c) Pb(ZrxTi1−x)O3. FeFET applications. (d) MEM transistor capable of programming and erasing. (e) Synaptic transistor. Reproduced with permission from Chen et al., Adv. Electron. Mater. 6, 2000057 (2020). Copyright 2020 Weinheim, WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim. (f) Realization of neuromorphic behavior through low power and high mobility. Reproduced with permission from Lee et al., Nat. Commun. 11, 2753 (2020). Copyright 2020 the Author(s) 2020, licensed under a Creative Commons Attribution 4.0 International License. Other structures using ferroelectric semiconductors. (g) Ferroelectric semiconductor-field effect transistor (FeS-FET). (h) FET using the ferroelectric semiconductor and insulator.

Close modal
TABLE I.

Comparison of FeFET’s feature according to the ferroelectric insulator (Pb(ZrxTi1-x)O3, PVDF, P(VDF-TrFE), HfO2-based ferroelectric) and the 2D ferroelectric semiconductor.

Pb(ZrXTi1-X)O3PVDF, P(VDF-TrFE)HfO2-based ferroelectric2D ferroelectric (α-In2Se3. SnS)
Layer Insulator62,64 Insulator40  Insulator41,127 Semiconductor30,140 
Thickness (nm) 10–340149  200∼69  ∼10149  Two-dimensional 
Deposition method Solution process52–58 (sol–gel process and wet chemical method) Solution process83–87 (spray, inkjet printing, and roll to roll print) ALD29,41,127 Transfer30,140 
Coercive field Ec (MV/cm) 0.1150  0.5150  0.8–2150  200 kV/cm (α-In2Se3)151  
20 kV/cm (SnS)140  
Polarization 2Pr (μC/cm230–60150  ∼10150  30–60150  0.92 (α-In2Se3)152   
∼17.5 (SnS)140  
Dielectric constant (εF∼200149  ∼12153  ∼30149  ∼100 (simple oxide)31   
200∼ (perovskite)31  
Gate voltage range (V) ±2062  ±6062,69 ±329,41,127 Depending on the  
insulator 
Advantage Easy synthesis52–58 and high polarization154  Easy synthesis83–87 and flexibility87  High industrial applicability,122 high polarization,29 and thin thickness29  High retention30 and low charge trapping30  
Disadvantage Bulk scale layer,59–61 environmental issues,48,50 and low bandgap27,28,104–107 Thermal stability,62 high power operation,62,69 and low polarization150  High intrinsic defect46  Low polarization155 and low industrial applicability147  
Pb(ZrXTi1-X)O3PVDF, P(VDF-TrFE)HfO2-based ferroelectric2D ferroelectric (α-In2Se3. SnS)
Layer Insulator62,64 Insulator40  Insulator41,127 Semiconductor30,140 
Thickness (nm) 10–340149  200∼69  ∼10149  Two-dimensional 
Deposition method Solution process52–58 (sol–gel process and wet chemical method) Solution process83–87 (spray, inkjet printing, and roll to roll print) ALD29,41,127 Transfer30,140 
Coercive field Ec (MV/cm) 0.1150  0.5150  0.8–2150  200 kV/cm (α-In2Se3)151  
20 kV/cm (SnS)140  
Polarization 2Pr (μC/cm230–60150  ∼10150  30–60150  0.92 (α-In2Se3)152   
∼17.5 (SnS)140  
Dielectric constant (εF∼200149  ∼12153  ∼30149  ∼100 (simple oxide)31   
200∼ (perovskite)31  
Gate voltage range (V) ±2062  ±6062,69 ±329,41,127 Depending on the  
insulator 
Advantage Easy synthesis52–58 and high polarization154  Easy synthesis83–87 and flexibility87  High industrial applicability,122 high polarization,29 and thin thickness29  High retention30 and low charge trapping30  
Disadvantage Bulk scale layer,59–61 environmental issues,48,50 and low bandgap27,28,104–107 Thermal stability,62 high power operation,62,69 and low polarization150  High intrinsic defect46  Low polarization155 and low industrial applicability147  

In general, the ferroelectric properties of a material originate from its non-centrosymmetric structure. The polarization phenomenon of representative ferroelectric materials such as Pb(ZrxTi1−x)O3 (PZT), polyvinylidene fluoride (PVDF), and hafnium–zirconium oxide (HZO) is due to the displacement of constituent atoms in the structure. The polarization direction is determined according to the position of the displaced atoms, and its degree varies depending on the specific phase state or external conditions of the material. PZT is a solid solution composed of Zr/Ti elements satisfying the morphotropic phase boundary (MPB) condition and has ferroelectric properties due to the displacement of Zr and Ti elements within the perovskite structure [Fig. 1(c)].19–22 PVDF maintains polarization due to the potential difference between H and F ions on a lattice structure in which molecules with dipoles are arranged in parallel in one direction [Fig. 1(b)].23–26 HZO is affected by the doping concentration of Zr, the tensile strength due to the lattice mismatch of neighboring substrates or electrodes, and the thickness of the film. The displacement changes its polarization value in the lattice of oxygen atoms [Fig. 1(a)].27–29 

The previously mentioned ferroelectric material has been mainly used as an insulator layer in FETs. Recently, a ferroelectric semiconductor-field effect transistor (FeS-FET) using a ferroelectric material as a semiconductor layer has been developed. Unlike conventional FeFETs, there is a mobile charge screening the depolarization field since polarization occurs in the semiconductor. Thus, polarization is maintained for a more extended period, thereby enhancing the retention and endurance of the device.30 FeS-FETs can use two-dimensional (2D) materials (e.g., In2Se3 and SnS) as a channel layer, and 2D materials have ferroelectric characteristics in a specific direction (in-plane or out-of-plane) depending on the orientation of the structure and the types of atoms. Circuits with a higher degree of integration can be made using 2D materials in the desired direction [Fig. 1(g)].31 Furthermore, if ferroelectric layers are introduced as both the insulator layer and the semiconductor layer, a Fe2-FET-type device can be made with a large remnant polarization (Pr) value and a small coercive voltage (Vc), having almost no hysteresis [Fig. 1(h)].30 

In general, FET performance evaluation, the on/off ratio, subthreshold swing (SS), the threshold voltage (Vth), transconductance (Gm), trap density (Nit), and field-effect mobility (μe, μh) are obtained by measuring the output curve and the transfer curve.32,33 However, in FeFETs, additional analyses of memory function and synaptic properties must be performed. Memory window (MW), retention, and endurance should be measured to verify the memory function of FeFETs.7,34–39 To verify the synaptic character of the device, changes in the SW for each condition through postsynaptic current (PSC) measurements of long-term plasticity (LTP), short-term plasticity (STP), paired-pulse ratio (PPR), spike rate-dependent plasticity (SRDP), spike duration time-dependent plasticity (SDDP), and spike number-dependent plasticity (SNDP) should be conducted.4,40,41

This article mainly discusses the characteristics of FeFETs using PZT, PVDF, HZO, and 2D materials. We will also explain why each material has ferroelectric properties and measure them to determine basic properties such as Pr, saturation polarization (Ps), and Vc. The research trends for the latest FeFETs will be reviewed for flexible devices, memory devices, and synapse devices, and the challenges that FeFETs must overcome in the future will be presented.

The principle of channel formation in the FeFET semiconductor is the same as that of a general FET. In an n-type semiconductor, energy band bending occurs between the insulator layer and the semiconductor layer due to the electric field when a positive voltage is applied to the gate. Due to this energy band bending, the conduction band edge (EC) is bent below the n-type semiconductor Fermi level (EF), resulting in the formation of mobile electrons. Otherwise, when a negative voltage is applied to the gate of the p-channel FET, the valence band edge (EV) bends above EF. This results in a channel composed of holes in this semiconductor layer, and current flows through this channel. The difference between the FeFET and conventional FETs is that FeFETs have ferroelectric materials as a dielectric layer [Fig. 2(a)] or a semiconductor layer [Fig. 2(b)]. The ferroelectric material of the FeFET maintains the channel state through Pr although the gate voltage (Vg) is not applied. In Figs. 2(e) and 2(f), unlike a conventional FET in which the channel disappears when the gate voltage is changed from positive Vg to 0 V, the band diagram shows that a channel is formed in the FeFET due to the up polarization of the ferroelectric insulator. When the polarization direction of the ferroelectric insulator becomes opposite completely by negative Vg, which is enough to induce polarization switching in the ferroelectric layer, the channel disappears [Fig. 2(g)]. This causes hysteresis in the transfer curve depending on the sweep direction of the gate bias. Ferroelectric materials with a high Pr or low coercive field (Ec) are advantageous for driving FeFETs where spontaneous ferroelectric polarization creates accumulated/depleted regions for carriers.42–45 In the FeS-FET, the ferroelectric polarization in the n-type semiconductor causes the channel formation even at Vg = 0 V [Fig. 2(h)].

FIG. 2.

Schematic of the Fe-FET using ferroelectric as the (a) insulator and (b) semiconductor layer. Polarization of the (c) insulator and (d) semiconductor ferroelectric layer. Energy band diagrams for the ferroelectric insulator/n-type semiconductor depending on the gate bias: (e) Vg > 0 V, (f) Vg = 0 V, and (g) Vg < 0 V. (h) Channel formation in a ferroelectric n-type semiconductor.

FIG. 2.

Schematic of the Fe-FET using ferroelectric as the (a) insulator and (b) semiconductor layer. Polarization of the (c) insulator and (d) semiconductor ferroelectric layer. Energy band diagrams for the ferroelectric insulator/n-type semiconductor depending on the gate bias: (e) Vg > 0 V, (f) Vg = 0 V, and (g) Vg < 0 V. (h) Channel formation in a ferroelectric n-type semiconductor.

Close modal

There are two leading causes of the hysteresis phenomenon in the transfer curve of FeFETs. One is due to the charge trap phenomenon occurring between the channel layer and the insulator layer. Charge-trapping is a phenomenon in which the movement of charge carriers (electrons and holes) is disturbed due to a defect in the interface between the semiconductor and the insulator. This phenomenon generally disturbs the hysteresis caused by the polarization of ferroelectric materials in most FeFETs.46 The other is due to the polarization of ferroelectric materials. The hysteresis of the transfer curve is controlled in the up/down direction of polarization, which changes with the gate voltage. It plays a functional role in memory and in synapse operation by maintaining the polarization state or forming a multi-level channel current based on the gate voltage.11,46 After the external electric field determines the up/down direction of the polarization from the fresh state, the ferroelectric polarization can maintain the state in the insulator layer [Fig. 2(c)] and in the semiconductor layer [Fig. 2(d)].30 

Pb(ZrxTi1−x)O3(PZT), which has higher piezoelectric properties than BaTiO3, was first studied in 1952.20 It has been studied very actively until recently before encountering environmental issues due to lead toxicity and strong volatility at high temperatures.20,47,48 Lead zirconate titanate (PZT) belongs to the perovskite family and has been mainly used in the polycrystalline form. In the basic perovskite ABO3 structure, Pb ions are located at the A site, and Zr or Ti ions are located at the B site. In this structure, PZT has a polarization value in the up/down direction due to the displacement of Ti or Zr ions [Fig. 3(a)]. PZT is in the form of a solid solution of ferroelectric lead titanate (PbTiO3) and antiferroelectric lead zirconate (PbZrO3) and is located in the MPB.49,50 In the phase diagram of PbZrO3 and PbTiO3, MPB exists with a fixed ratio (Zr:Ti = 53:47, room temperature) defined by a single line. However, it is present in the form of a range depending on the synthesis method of PZT. When PZT is employed as a gate dielectric, PZT with various Zr and Ti ratios can be used. PbTiO3 and PbZrO3 have a tetragonal phase and a rhombohedral phase, respectively. They have six and eight polarization directions. In the MPB of PZT, various polarization levels can be easily obtained because there are 14 polarization directions with low energy barriers, in which PZT have the largest piezoelectric coefficient.51 

FIG. 3.

(a) Perovskite structure of Pb(ZrxTi1-x)O3 (PZT). The displacement of Ti2+ and Zr2+ ions (A site) causes the polarization of PZT. Piezoelectric force microscopy (PFM) for ferroelectric characteristics of PZT using SRO as the bottom electrode on the mica substrate. (b) Phase image. (c) Amplitude image. The P–E curve of the mica/CFO/SRO/PZT/Pt capacitor structure depending on the (d) bending radius and (e) bending cycles maintaining the bending radius at 6 mm. Reproduced with permission from Ren et al., Adv. Funct. Mater. 30, 1906131 (2020). Copyright 2019 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

FIG. 3.

(a) Perovskite structure of Pb(ZrxTi1-x)O3 (PZT). The displacement of Ti2+ and Zr2+ ions (A site) causes the polarization of PZT. Piezoelectric force microscopy (PFM) for ferroelectric characteristics of PZT using SRO as the bottom electrode on the mica substrate. (b) Phase image. (c) Amplitude image. The P–E curve of the mica/CFO/SRO/PZT/Pt capacitor structure depending on the (d) bending radius and (e) bending cycles maintaining the bending radius at 6 mm. Reproduced with permission from Ren et al., Adv. Funct. Mater. 30, 1906131 (2020). Copyright 2019 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Close modal

PZT films can be fabricated in various ways (e.g., sol–gel process, co-precipitation) using a solution state. In particular, the wet chemical method can synthesize thin films with homogeneous stoichiometry at the atomic level.52–58 A nanoscale PZT thin film beyond conventional bulk PZT has been studied as a memory device and as a synapse device.59–61 Recently, epitaxially grown PZT films have been studied for stronger ferroelectric properties than polycrystalline films.

Before making FeFETs, it is necessary to investigate the ferroelectric properties of the PZT material. Ren et al. measured the ferroelectric properties of epitaxially grown PZT thin films.62 In the mica/CFO/SRO/PZT capacitor structure, the piezoelectric characteristics and phase diagram of PZT (180 nm) were measured through piezoelectric force microscopy (PFM). The P–E curve was also measured by controlling the external electric field. In the PFM image, the contrasting images of phase [Fig. 3(b)] and amplitude [Fig. 3(c)] are clearly shown in the area to which DC ±10 V is applied. Additionally, P–E curve characteristics were identified under the non-stress condition and the mechanical stress conditions such as bending stress and cycle stress. The ferroelectric characteristics of PZT rarely degrade due to stress. Vc is 3.00 V and −2.50 V, and Ps and Pr are 93 µC/cm2 and 49 µC/cm2, respectively [Figs. 3(d) and 3(e)].62 Due to the asymmetry in the contact surface between the built-in electric field and the electrode, Vc is not symmetric with respect to 0 V.62,63

Ko et al. fabricated a 2D/FeFET whose transition-metal dichalcogenide (TMD) channel layer has different PL characteristics depending on the polarization of PZT.64 They deposited the epitaxial PZT film on SRO/STO [Fig. 4(a)]. WSe2 and MoS2 were used as p-type and n-type semiconductors for channel layers, respectively. Pr of PZT is 60 µC/cm2, which is quite large. When + Vg above |Vc| is applied to the gate electrode SrRuO3 (SRO), PZT exhibits up polarization in the channel direction, making a channel composed of electrons in the channel layer (MoS2). In contrast, when voltage is applied at -Vg lower than -|Vc|, PZT exhibits down polarization in the SRO direction, which causes the hole to make a channel in the WSe2 layer [Fig. 4(b)]. When the polarization is aligned in a direction in which the channel is not formed, a carrier depletion effect occurs and no current flows. From the transfer curve [Figs. 4(c) and 4(d)] of the FeFET composed of three layers of WSe2 and MoS2, it can be observed that the on/off ratio is higher than 104 and the hysteresis is caused by Pr rather than the charge trapping phenomenon. The range of Vg is narrower than that of the FeFET using polycrystalline PZT (8 V–20 V), which proves that low power driving is possible. It has a high dielectric constant (∼200) due to the epitaxial growth of PZT. The high-noise part of the transfer curve, which is the difference between the conventional FET (dotted line) and the PZT-FeFET, is caused by the polarization process of PZT. Noise can be lowered using thinner PZT and highly crystalline PZT to reduce defects.64 To grasp its utility as a memory device, it is necessary to measure the on/off response speed of the gate pulse and the retention. The length of the retention time is related to the stability in the operating state, and the reaction speed of the transistor to the gate pulse can be determined by adjusting the periodic poling wave. The periodic poling wave was adjusted in the range of pulse width (tw, 0.5 s−1 ms) and edge (te, 25 ms–10 µs), and Isd reaches a relaxation state as tw decreases. Reducing the contact resistance between the 2D channel and the metal interface increases the reaction rate by the external field, which is related to the RC delay between layers, and a reduced PZT defect, which is linked to the domain wall reaction rate. As shown in Fig. 4(e), the switching speed is significantly faster (in the ms range) compared to the poling time interval of 1 s for PVDF-based flexible devices.65,66 In addition to that, an on/off ratio of 102 is maintained in this situation.64 

FIG. 4.

(a) Schematic of the FeFET using Pb(Zr0.2Ti0.8)O3 as the ferroelectric insulator and TMD as the 2D channel. (b) Schematic diagram of polarization bound charge in the FeFET under polarization up and polarization down states. The hysteresis transfer curve of the FeFET device with PZT using (c) WSe2 and (d) MoS2 as a 2D channel compared with the transfer curve (dashed line) of the conventional FET without PZT. IDVSD in the inner box measured at Vg = 0 V with the polarization direction of PZT maintained. (e) ID-time plot depending on the gate pulse parameter (tw, te, VP). tw: pulse width, te: pulse edge, and VP: pulse voltage amplitude. Reproduced with permission from Ko et al., Adv. Mater. 28, 2923 (2016). Copyright 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

FIG. 4.

(a) Schematic of the FeFET using Pb(Zr0.2Ti0.8)O3 as the ferroelectric insulator and TMD as the 2D channel. (b) Schematic diagram of polarization bound charge in the FeFET under polarization up and polarization down states. The hysteresis transfer curve of the FeFET device with PZT using (c) WSe2 and (d) MoS2 as a 2D channel compared with the transfer curve (dashed line) of the conventional FET without PZT. IDVSD in the inner box measured at Vg = 0 V with the polarization direction of PZT maintained. (e) ID-time plot depending on the gate pulse parameter (tw, te, VP). tw: pulse width, te: pulse edge, and VP: pulse voltage amplitude. Reproduced with permission from Ko et al., Adv. Mater. 28, 2923 (2016). Copyright 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Close modal

In the IoT era, the demand for flexible materials for wearable devices, implanted systems, and brain-machine interfaces has increased.67 Poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)], which is flexible and has ferroelectric characteristics, has received a lot of attention, but thermal safety at high temperatures and the high power operation of the device are problem.62 Recently, a study on a flexible device using PZT has been conducted.61,67,68 They deposited an epitaxial PZT film on a mica substrate. This device has an average bending radius of about 5 mm, which is large compared to the device using [P(VDF-TrFE)],69 but has excellent thermal stability and a high on/off ratio. Ren et al. synthesized a low power inorganic flexible transistor device using the epitaxial PZT film grown on a mica substrate. This device shows a small operation voltage (6 V), flexibility, and high operation temperature (200 °C). ZnO was used as the channel layer, PZT was used as the insulator layer, and SRO was used as the gate electrode. The epitaxial SRO film was deposited using CoFe2O4 (CFO) as a buffer layer. Figure 5(a) shows that the polarization of the PZT layer is maintained even when the structure of mica/CFO/SRO/PZT/ZnO/Pt FeFET is bent. In the output curve, Isd is saturated within 6 V, indicating lower power consumption compared with the FeFET using PVDF [Fig. 5(b)]. The device operates without degradation for 1 h under the 6 mm radius bending state, and there is no significant degradation in performance even after 500 cycles [Fig. 5(c)]. Under the condition Vsd = 3 V, the transfer curve has a hysteresis curve shape. When Vg is swept from −6 V to 6 V, it has a MW of 1.5 V. This swept range of Vg is smaller than the range of a PVDF-based FeFET (±20 V–±40 V), which means that low power driving is possible.62 Besides, the device performance under stress was examined depending on time, bend radius, and cycle. The retention test was conducted for 4000 s under 4 mm radius bending conditions. The cycle stress test was carried out under 6 mm radius conditions. The result shows a large on/off ratio of 104, indicating high applicability as a memory device.62 Furthermore, Tsai et al. made a very competitive device with a bending radius of 5 mm, an on/off ratio of 103, and an endurance of 300 cycles, and a retention of 100 h with this structure.67 

FIG. 5.

(a) Schematic diagram of the inorganic flexible FeFET. The output curve (IDSVDS) of the flexible FeFET depending on the (b) bending radius and (c) operation cycle. Reproduced with permission from Ren et al., Adv. Funct. Mater. 30, 1906131 (2020). Copyright 2019 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

FIG. 5.

(a) Schematic diagram of the inorganic flexible FeFET. The output curve (IDSVDS) of the flexible FeFET depending on the (b) bending radius and (c) operation cycle. Reproduced with permission from Ren et al., Adv. Funct. Mater. 30, 1906131 (2020). Copyright 2019 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Close modal

It is important to use a material with excellent ferroelectric properties as an insulator to maximize this in the FeFET. However, interlayer insertion and using specific channel materials can improve the characteristics of memory devices.70,71 When the interlayer is used in the MFIS structure, the performance can be further improved in leakage current, MW, and breakdown.8,72,73 Using 2D transition-metal dichalcogenide (TMD) as a channel layer leads to an increase in the degree of integration, mobility, and retention performance.74 It also allows the heterostructure to be applied to other materials through van der Waals coupling.75,76 Recently, PZT FeFETs have been fabricated using VO2 nanowires (NWs),77 the GaN NW,78 2D black phosphorus (BP),76 and graphene79 as channel layers. High mobility can be obtained using graphene.74,79 By using the photoelectric properties of BP, it is possible to fabricate a photoelectric memory that reduces the side effects of readout crosstalk and depolarization during the reading process. When using BP, the data retention period can be increased dramatically to 3.6 × 106 s by using the optical read method.76 Besides, the PZT FeFET using ZnO as a channel shows synaptic characteristics based on spike-timing-dependent synaptic plasticity (STDP).80,81

In 2004, Schroeder et al. fabricated the first organic ferroelectric field-effect transistor (OFeFET) using nylon polymer and poly(m-xylylene adipamide) (MXD6) as a gate insulator and amorphous state pentacene (PEN) as a channel.82 The polymer-based ferroelectric material is capable of low-temperature solution processing such as spray, inkjet printing, and roll to roll print technologies,83,84 making it easy to synthesize flexible devices. OFeFETs are FETs using an organic material with ferroelectric properties as a gate insulator layer, and PVDF and P(VDF-TrFE) are representative ferroelectric materials. PVDF is mainly synthesized by free radical polymerization, which starts with monomer 1,1-difluoroethylene (VDF). P(VDF-TrFE) is a ferroelectric polymer having a specific ratio (20 mol. %–50 mol. %) of trifluoroethylene (TrFE) in PVDF.85,86 They have been used for many devices because it shows both flexibility and ferroelectricity with an easy synthesis method.87 

PVDF has a structure in which vinylidene fluoride (VDF) is repeated (–CH2–CF2–) and has a dipole moment due to the unmatched functional group of a negatively charged hydrogen atom and a positively charged fluorine atom (7.07 × 10−30 Cm).24 The basic structure of PVDF molecules is divided into three types: trans-gauche-trans-gauche (TGTG′), trans-trans-trans gauche (TTTG), and all-trans (TTTT) [Fig. 6(a)].26,88,89 In the crystalline structure, the polarization is determined according to how high dipole molecules are arranged. As shown in Fig. 6(b), it is classified into four phases, and all except the α phase have the property of causing polarization. In the α phase, TGTG′ molecules are aligned in an antiparallel manner so that the overall polarization value is canceled and, thus, has paraelectric properties. The β, γ, and δ phases have ferroelectric properties as TTTT, TTTG, and TGTG′ molecules are aligned in parallel, respectively.23,25,26,90,91 In particular, β can theoretically have the largest polarization value, and the value is 13 µC/cm2.24 However, since the potential energy per monomer unit is −6.03 Kcal (α phase) and −5.73 Kcal (β phase), the α phase is thermodynamically more stable than the β phase. Therefore, PVDF at room temperature mainly maintains the α phase.90,92,93 On the other hand, P(VDF-TrFE) can exist predominantly in the β phase under the same conditions by controlling the concentration of TrFe rather than PVDF.85,86

FIG. 6.

(a) Basic structure of the PVDF molecule. (b) Polarization properties according to the PVDF phase. The β phase represents the highest polarization value. Reproduced with permission from Zhu et al., Polym. Int. SCI, 26 (2020). Copyright 2020 Society of Chemical Industry. (c) P–E curve of the 300 nm P(VDF‐TrFE) layer. (d) Transfer curve (IsdVtg) of the 2D channel/PVDF FeFET. (e) IsdVsd curve at Vg = 0 V and polarization direction of PVDF maintained. Reproduced with permission from Wang et al., Adv. Mater. 27, 6575 (2015). Copyright 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

FIG. 6.

(a) Basic structure of the PVDF molecule. (b) Polarization properties according to the PVDF phase. The β phase represents the highest polarization value. Reproduced with permission from Zhu et al., Polym. Int. SCI, 26 (2020). Copyright 2020 Society of Chemical Industry. (c) P–E curve of the 300 nm P(VDF‐TrFE) layer. (d) Transfer curve (IsdVtg) of the 2D channel/PVDF FeFET. (e) IsdVsd curve at Vg = 0 V and polarization direction of PVDF maintained. Reproduced with permission from Wang et al., Adv. Mater. 27, 6575 (2015). Copyright 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Close modal

Wang et al. confirmed the ferroelectric properties of 300 nm-thick P(VDF-TrFE) by measuring Ps of 9 µC/cm2 at a gate voltage of ±50 V with a Sawyer–Tower circuit at 1 Hz voltage frequency [Fig. 6(c)].66 Compared with the FET using the SiO2 dielectric layer under the same conditions (channel layer: MoS2, three layers, room temperature), P(VDF-TrFE) has a larger difference between on-Vth and off-VthVth) than SiO2 [Fig. 6(d)]. In Fig. 6(e), Isd is adjusted and maintained depending on the up, down, and fresh states of polarization. This property is related to the retention characteristics of FeFET, implying that this device can be driven as a memory device.

OFeFETs using PVDF and P(VDF-TrFE) can also be used as neuromorphic devices. Basically, a presynaptic pulse is compared to pulse-type Vg and PSC to Isd. Vg in the form of a pulse causes the polarization in the ferroelectric layer to be multi-level, allowing Isd to have a step-by-step current value, and the FeFET to be able to be applied as a synaptic device.6 The ratio of two neighboring PSCs represents PPR, and the SW represents the difference between Isd before and after the gate pulse.75 As the distance between the two consecutive stimuli increases, the SW becomes smaller. LTP and STP indicate the difference in the SW depending on the Vg pulse time interval.94,95 Moreover, measurements of the SW according to the amplitude of the Vg pulse and the number of consecutive pulses are called spike amplitude-dependent plasticity (SADP) and SNDP, respectively.40,96 Lee et al. added BaTiO3 to P(VDF-TrFE) to synthesize a ferroelectric layer with small Ec that can change polarization more easily.40 Using this, a synapse device was fabricated with pentacene as a channel, and Fig. 7(a) shows the schematic of this device. In this experiment, the SS, on/off ratio, and mobility are analyzed in the transfer curve and in the output curve, and synaptic characteristics such as LTP, STP, and SW are investigated through PSC measurements. MoS2 is a p-type semiconductor, and when Vrec (that is, Vg) is negatively applied, polarization is aligned to the bottom gate in a downstate, and a channel is formed to allow current to flow. After this state, the polarization is aligned differently from the existing fresh state when the voltage applied to Vrec becomes 0 V again. Current can flow differently from the previous fresh state [Fig. 7(b)]. For gate pulses with 0.5 s pulse width and −10 V amplitude, FeFETs were applied at intervals of 1.42 Hz and 0.1 Hz to identify LTP and STP [Figs. 7(c) and 7(d)]. The SW by the gate pulse interval, an essential element of synaptic devices, was investigated. As shown in Fig. 7(e) for measuring SADP, the SW is 9.95 at a gate voltage of −20 V, the SW is 0.56 when it is −7 V, and the SW is −0.3 when it is −1 V. SNDP was measured under the condition of −10 V and 0.5 s. When the spiking number increased from 1 to 100, PSC also increased [Fig. 7(f)]. Based on Figs. 7(g) and 7(h), Ec of BaTiO3 (BT) NP(20 wt. %)/P(VDF-TrFE) nanocomposites is 48.83 MV/m, which was smaller than 88.2 MV/m of pure P(VDF-TrFE). This shows that the switch is more prone to drive low power. When using P(VDF-TrFE) with BT NP, the SW appears larger [Fig. 7(g)], and synaptic characteristics are exhibited more prominently in the SW change by frequency [Fig. 7(h)].

FIG. 7.

(a) Schematic of the Fe-OFET. Pentacene forms a channel layer, and PVDF with BaTiO3 added forms an insulator layer. (b) The principle of Fe-OFET synapse operation. The postsynapse current (PSC) value according to gate pulses variation: (c) Long-term potentiation (LTP) 0.1 Hz, (d) short term potentiation (STP) 1.42 Hz, (e) amplitude, and (f) the number of gate pulse under pulse width 500 ms and amplitude −10 V. Variation performance of the Fe-OFET using the dielectric layer as BT NP (20 wt. %)/P(VDF-TrFE and P(VDF-TrFE). (g) Variation of PSC for gate pulse width. (h) Synapse weight (SW) for gate pulse frequency. Reproduced with permission from Lee et al., Nat. Commun. 11, 2753 (2020). Copyright the Author(s) 2020, licensed under a Creative Commons Attribution 4.0 International License.

FIG. 7.

(a) Schematic of the Fe-OFET. Pentacene forms a channel layer, and PVDF with BaTiO3 added forms an insulator layer. (b) The principle of Fe-OFET synapse operation. The postsynapse current (PSC) value according to gate pulses variation: (c) Long-term potentiation (LTP) 0.1 Hz, (d) short term potentiation (STP) 1.42 Hz, (e) amplitude, and (f) the number of gate pulse under pulse width 500 ms and amplitude −10 V. Variation performance of the Fe-OFET using the dielectric layer as BT NP (20 wt. %)/P(VDF-TrFE and P(VDF-TrFE). (g) Variation of PSC for gate pulse width. (h) Synapse weight (SW) for gate pulse frequency. Reproduced with permission from Lee et al., Nat. Commun. 11, 2753 (2020). Copyright the Author(s) 2020, licensed under a Creative Commons Attribution 4.0 International License.

Close modal

When using the PVDF FeFET as a memory device, it is used to insert an interlayer or modify the channel layer to maximize the memory function. The most significant properties of a memory device are MW, retention, and endurance. Modifying the device structure, inserting an interlayer, and utilizing a specific channel layer (e.g., Si NW and TMD) can compensate for the on/off ratio and driving power value, which is the weakness of the PVDF-FET as a memory device.67 Hwang et al. enhanced the retention of the vertical channel ferroelectric field effect transistor (VC-FeFET) by one year and the endurance to 105 by lowering the injection barrier of the electron using a MoO3 electrode interlayer.97 Besides, the gate leakage and driving power can be reduced using poly(styrene-block-paraphenylene) (PS-b-PPP) modified reduced graphene oxides (rGOs) (PMrGOs) as interlayers placing between the ferroelectric layer and the gate electrode.98 Chang et al. significantly reduced the off current to 10−11 A using the poly(styrene-random-methylmethacrylate) copolymer P(S-r-MMA) interlayer between the bottom gate electrode and P(VDF-TrFE).99 Van et al. introduced a nanowire-based ferroelectric-complementary metal–oxide–semiconductor (NW FeCMOS) structure to construct the CMOS using the n+, p+ doped Si NW. It shows a write/erase voltage of ±5 V (MW 1 V), and the reading power consumption was minimal (0.1 pW). This device has an on/off ratio of 104 and a very high retention time of 1.2 × 104 s, while still maintaining an on/off ratio of 103. It makes this device drive at low-power. Therefore, it can be a structure that compensates for the disadvantages of the PVDF device.100,101 Additionally, the PVDF-FeFET can be fabricated using the TMD material as a channel. The PVDF FeFET using MoS2 (TMD) as a semiconductor layer for a memory device showed an on/off ratio of 107, the electron mobility of 175 cm2/Vs, and a MW of 15 V.102,103

The thickness of the PZT layer used in ferroelectric random-access memory (FRAM) is about 70 nm. In the process of high integration of the circuit and the transition from a planar structure to a vertical structure, PZT shows limitations such as leakage current and electrical breakdown due to a low bandgap (3 eV–4 eV).27,28,104–107 In particular, in the case of the ALD (Atomic Layer Deposition) process, large Pb is highly volatile, making it difficult to deposit a thin film. Oxygen, which has a relatively weak bond strength, decreases the reliability of PZT-based devices. The use of Pb is an environmental burden, so finding new ferroelectric materials has become crucial.104,106 To solve the problems associated with PZT, HfO2-based films have been studied.28 One obstacle to the use of HfO2 is that the tetragonal or cubic phase with a high dielectric constant is stabilized at 1750 °C and 2700 °C.108,109 HfO2 is stabilized in a monoclinic phase at room temperature. Initial attempts were made to maintain a phase with a high dielectric constant through Si doping. In 2011, HfO2 was doped with ZrO2. The resulting material maintains the orthorhombic phase (space group Pca21), which is a non-centrosymmetric structure at room temperature, as shown in Fig. 8(a). Atoms marked with red spheres are oxygen atoms, and structural asymmetry occurs due to the movement of oxygen atoms. Therefore, HZO can possess ferroelectric properties at room temperature.28 

FIG. 8.

(a) Polarization properties according to the Hf0.5Zr0.5O2 phase. Anisotropy crystal structure of the orthorhombic phase induces polarization. Reproduced with permission from Böscke et al., Appl. Phys. Lett. 99, 102903 (2011). Copyright 2011 AIP Publishing LLC. PFM (b) amplitude, (c) phase, and (d) hysteresis according to the bias voltage of 2.5 nm thick Hf0.5Zr0.5O2 on the n-Si substrate. Reproduced with permission from Chernikova et al., ACS Appl. Mater. Interfaces 8, 7232 (2016). Copyright 2016 American Chemical Society. (e) Polarization hysteresis curve according to Zr concentration doped in HfO2 on a 9 nm thickness film (10 kHz, 50 mV). Reproduced with permission from Müller et al., Nano Lett. 12, 4318 (2012). Copyright 2012 American Chemical Society.

FIG. 8.

(a) Polarization properties according to the Hf0.5Zr0.5O2 phase. Anisotropy crystal structure of the orthorhombic phase induces polarization. Reproduced with permission from Böscke et al., Appl. Phys. Lett. 99, 102903 (2011). Copyright 2011 AIP Publishing LLC. PFM (b) amplitude, (c) phase, and (d) hysteresis according to the bias voltage of 2.5 nm thick Hf0.5Zr0.5O2 on the n-Si substrate. Reproduced with permission from Chernikova et al., ACS Appl. Mater. Interfaces 8, 7232 (2016). Copyright 2016 American Chemical Society. (e) Polarization hysteresis curve according to Zr concentration doped in HfO2 on a 9 nm thickness film (10 kHz, 50 mV). Reproduced with permission from Müller et al., Nano Lett. 12, 4318 (2012). Copyright 2012 American Chemical Society.

Close modal

At first, there were many candidates for doping in the form of Hf1-xBxO2, such as Si, Al, Y, La, Zr, Sr, Gd, and Sc.110 Unlike other dopants showing chemical stability within 20%, Zr showed a chemical stability up to 50%. Furthermore, HZO has been used as it is because ZrO2 has a high dielectric constant without high-temperature heat treatment.28,104,106 In particular, the composition of Hf1-xZrxO2 (x = 0.3–0.5) changes from the tetragonal phase to the orthorhombic phase during 650 °C heat treatment, and ferroelectric properties become stronger when the doping concentration of ZrO2 is 50%. For the ALD process, the composition can be maintained by alternately stacking HfO2 and ZrO2 [Fig. 8(e)]. Since HfO2 itself remains in the monoclinic phase, thinner intersection thicknesses result in higher Ps values of thin films stacked on an atomic scale using ALD.104,106,111,112

Since the non-centrosymmetric structure induces the ferroelectric properties of HZO, the ferroelectric properties can be strengthened by structural deformation caused by external stress.29 Even under 650 °C, where the monoclinic phase of HZO is present, HZO can form an orthorhombic phase under tensile strain due to the lattice mismatch between HZO and the substrate. External stress can derive higher ferroelectric properties at lower temperatures and thinner thickness than PZT. When thin TiN is deposited on HZO, the tensile strength acts on HZO, and the orthorhombic phase is obtained through heat treatment at 450 °C.113 One study has reported improving the ferroelectricity of HZO in FeFETs by using HfN as the gate electrode.114 To observe the change in the ferroelectric properties of HZO due to the lattice mismatch with neighboring layers, Shiraishi et al. conducted an experiment in which different tensile strengths were applied to HZO through the differences in the thermal expansion of the substrate. Specifically, 17 nm-thick HZO was deposited on (1 1 1) Pt-coated SiO2, Si, and CaF2 substrates. It was observed that HZO showed the greatest tensile stress on SiO2 with the lowest thermal expansion coefficient and had the largest polarization value.115,116 Estandía et al. classified the HZO phases according to the substrate with different lattice parameters. The lattice mismatch range is about −4.1%–8.7%. The orthorhombic phase of HZO was formed with tensile strain rather than compressive strain.117 In addition, it was confirmed that HZO with a thickness of 5 nm–9 nm also has ferroelectric characteristics in the rhombohedral phase by the strain.118 

As the thickness of HZO increases, a monoclinic phase is formed, resulting in weaker ferroelectric properties. When it exceeds about 20 nm, the polarization decreases sharply, and this can be overcome using Al2O3 as an interlayer.27,119–121

Chernikova et al. proved that 2.5 nm-thick Hf0.5Zr0.5O2 deposited by ALD has ferroelectric properties. Figures 8(b) and 8(c) show PFM images of HZO deposited at 2.5 nm on the Si substrate, and it can be observed that the piezo characteristics [Fig. 8(b)] and phase [Fig. 8(c)] change dramatically according to the voltage. The TiN/Hf0.5Zr0.5O2/n+Si junction using a TiN electrode as the top electrode showed stronger polarization than the junction structure without TiN as the top electrode [Fig. 8(d)].113,122

Using HZO as the dielectric layer of FeFETs, various studies have been reported using interlayers and TMD as a channel layer to improve device performance.15,123,124 Zhang et al. made a memory device of HZO/Al2O3 (6 nm/2 nm) using MoS2, a representative TMD material. The on/off ratio was about 107, which was considerably higher than that of PZT and PVDF, and the endurance and retention were also high.125 Chen et al. investigated the multi-level nature of Isd by applying 2D WS2 as the channel layer and HZO as the insulator layer, and they measured the synaptic characteristics of the FeFET (e.g., LTP, STP, SADP, and SRDP). A P++Si/HZO/Al2O3/Ti/Au capacitor was fabricated, and the ferroelectric properties of HZO were measured. In the FeFET structure, HZO was deposited at 6 nm using ALD, and Al2O3 was deposited at 2 nm to prevent leakage current. HZO is a polycrystalline film formed by post-annealing at 400 °C for 30 s. Ps was about 4 µC/cm2, which is enough to make a synaptic transistor. An 8.3 nm-thick WS2 (bandgap 2.05 eV) layer was used as the channel layer, and Schottky-coupled Ti/Au electrodes were used [Fig. 9(a)]. The polarization of HZO varies depending on the Vg range, and a larger Vg range results in greater hysteresis in the transfer curve. The on/off ratio of this device is 106, and PSC and depression were sufficiently formed when Vg is given with an amplitude of 0.5 V and a pulse of 10 ms width at 20 ms intervals [Fig. 9(c)]. The change in the SW was 103 at 3 V, which controls the PSC according to the gate signal amplitude [Fig. 9(d)]. When the excitatory PSC (EPSC) was Vg = 3.5 V and the read voltages were 0.1 V and 0.5 V, Vg adjusts the carrier density and the EPSC saturated in a continuous stimulus, resulting in synaptic transistor behavior [Fig. 9(e)].41 

FIG. 9.

(a) FeFET with synapse property using ferroelectric property of HZO. (b) Transfer curve of the synaptic transistor (Ids-VG). (c) Postsynaptic current (PSC) for the variation of gate pulse width at VDS = 0.5 V. (d) Synaptic weight change ratio (SW) depending on the VG pulse amplitude. (e) PSC according to the repetitive gate pulse. Reproduced with permission from Chen et al., Adv. Electron. Mater. 6, 2000057 (2020). Copyright 2020 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

FIG. 9.

(a) FeFET with synapse property using ferroelectric property of HZO. (b) Transfer curve of the synaptic transistor (Ids-VG). (c) Postsynaptic current (PSC) for the variation of gate pulse width at VDS = 0.5 V. (d) Synaptic weight change ratio (SW) depending on the VG pulse amplitude. (e) PSC according to the repetitive gate pulse. Reproduced with permission from Chen et al., Adv. Electron. Mater. 6, 2000057 (2020). Copyright 2020 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Close modal

It is possible to manufacture an NVM transistor device capable of high-speed write/read using HZO to fabricate an MFIS structured FeFET. Performance as a memory device can be verified through MW, endurance, and retention measurements.7,34–39 When high-k ZrO2 is used as a seed layer, the ZrO2 layer improves the crystallinity of HZO and suppresses the growth of HZO in the monoclinic phase, thereby improving the ferroelectric properties of HZO and improving the memory characteristics [Fig. 10(a)].126 Xiao et al. measured the P–E curve of HZO and confirmed that the polarization effect was enhanced in the presence of a ZrO2 layer.126 In this device, the program/erase gate pulse was applied for 100 ns at 7 V, and Vsd for reading is 0.1 V, which results in low power use [Fig. 10(b)]. Due to the crystallinity of HZO and the formation of the orthorhombic phase, the basic MW shows a very large value of 2.8 V. The change in the MW has a linear relationship with the log scale of time [Fig. 10(c)]. High-k ZrO2 effectively prevents degradation due to trapped charges occurring in the gate insulator, reducing band bending at the interface.15,127 This FeFET maintained its program state well for up to 10 years, which is consistent with the change in the number of charge traps.15 The MW value is maintained until 103 cycles, and reliability is maintained up to 5 × 102 cycles. The MW value remained 0.9 V up to 104 cycles and has an effect 2.3 times greater than that of 0.4 V [Fig. 10(d)]. The leakage current increases as the cycle progresses due to trap sites, and a very low leakage current value (around 10−7 A) was maintained up to 1 × 103 A where MW was maintained [Fig. 10(e)].127 Various studies dealing with external conditions (e.g., temperature and radiation), the structure of the FeFET, and the MW changed by multi-level two bit storage of the HZO-FeFET are being actively conducted in the fields of memory and synaptic devices.128–132 

FIG. 10.

(a) Schematic of the FeFET using the HZO dielectric layer. (b) Gate voltage pulse for FeFET read/write. (c) Repetitive program/erase operation of the FeFET compared with and without the ZrO2 seed layer. The FeFET using the ZrO2 seed layer with a high memory window (MW) value. (d) Transfer curve for repetitive program/erase operation. (e) Low leakage current of the FeFET with the ZrO2 seed layer. Reproduced with permission from Xiao et al., Nanoscale Res. Lett. 14, 254 (2029). Copyright the Author(s) 2019 under the terms of the Creative Commons Attribution 4.0 International License.

FIG. 10.

(a) Schematic of the FeFET using the HZO dielectric layer. (b) Gate voltage pulse for FeFET read/write. (c) Repetitive program/erase operation of the FeFET compared with and without the ZrO2 seed layer. The FeFET using the ZrO2 seed layer with a high memory window (MW) value. (d) Transfer curve for repetitive program/erase operation. (e) Low leakage current of the FeFET with the ZrO2 seed layer. Reproduced with permission from Xiao et al., Nanoscale Res. Lett. 14, 254 (2029). Copyright the Author(s) 2019 under the terms of the Creative Commons Attribution 4.0 International License.

Close modal

Since FeS-FETs using ferroelectrics as a semiconductor layer have a higher retention value compared with conventional FETs, they are considered to be a suitable structure for realizing an NVM transistor [Fig. 2(a)]. Non-destructive read and construction of high-density integrated circuits can be achieved.30,31 In the FeS-FET, it is possible to use higher quality amorphous materials as an insulator layer than polycrystalline materials since the semiconductor layer has ferroelectric properties. The charge-trapping phenomenon can be reduced by band bending between the insulator and the semiconductor. Since the mobile charge in the ferroelectric semiconductor suppresses the formation of the depolarization field, it has a higher retention value compared to the FeFET.30,46,133–135

In the FeS-FET, since polarization occurs in the semiconductor, the band bending to form the channel is tuned according to the electric field formed by Vg. Si et al. adjusted the electric field range using the EOT (effective oxide thickness). The hysteresis direction can be controlled in the transfer curve according to the position of the channel.30 

Si et al. fabricated the FeS-TFT using α-In2Se3, which has a non-centrosymmetric rhombohedral R3m structure136 and a single crystalline structure, as a ferroelectric semiconductor. A SiO2 (90 nm) film having a high EOT value and a HfO2 (15 nm) film having a low EOT value were deposited on a p-doped Si substrate (bottom gate). By using a 10 nm-thick Al2O3 film, the device properties were improved through the passivation layer and electron doping effect due to the positive fixed charge [Fig. 11(a)].30 The FeS-FET using SiO2 (90 nm) and HfO2 (15 nm) has an on/off ratio of 108 or more. When HfO2 is used, the Vg voltage range is narrower than that of SiO2, implying that low power driving is possible. The electric field has a narrow effect on the semiconductor layer in the case of SiO2 and a wider effect in the case of HfO2. Therefore, the hysteresis direction is clockwise [Fig. 11(b)] when the channel in SiO2 is formed on the insulator side (bottom surface) in the semiconductor. The HfO2 channel is formed on the Al2O3 side (top surface), and the hysteresis direction is counterclockwise [Fig. 11(c)]. When the EOT is 0.5 nm [Fig. 11(d)], the electric field by Vg affects the overall polarization of the ferroelectric semiconductor, and when the polarization direction is up, the conducting surface is formed on the source and drain sides [Fig. 11(e)]. When the EOT is 30 nm [Fig. 11(f)], the electric field caused by Vg affects the partial polarization of the ferroelectric semiconductor, and when the polarization direction is down, a conducting surface is formed on the oxide layer side [Fig. 11(g)].30 

FIG. 11.

(a) Schematic of the FeS-FET using the ferroelectric semiconductor (In2Se3) as a channel layer. Transfer curve (IDVGS) using (b) 90 nm SiO2 (clockwise direction hysteresis curve) and (c) 15 nm HfO2 (counterclockwise direction hysteresis curve) as a dielectric. (d) Transfer curve of thin effective oxide thickness (0.5 nm HfO2). (e) Band diagram for charge dynamic. (f) Transfer curve of thick effective oxide thickness (30 nm SiO2) and (g) band diagram for charge dynamic. Reproduced with permission from Si et al., Nat. Electron. 2, 580 (2019). Copyright the Author(s), under exclusive license to Springer Nature Limited 2019.

FIG. 11.

(a) Schematic of the FeS-FET using the ferroelectric semiconductor (In2Se3) as a channel layer. Transfer curve (IDVGS) using (b) 90 nm SiO2 (clockwise direction hysteresis curve) and (c) 15 nm HfO2 (counterclockwise direction hysteresis curve) as a dielectric. (d) Transfer curve of thin effective oxide thickness (0.5 nm HfO2). (e) Band diagram for charge dynamic. (f) Transfer curve of thick effective oxide thickness (30 nm SiO2) and (g) band diagram for charge dynamic. Reproduced with permission from Si et al., Nat. Electron. 2, 580 (2019). Copyright the Author(s), under exclusive license to Springer Nature Limited 2019.

Close modal

The ferroelectric 2D oxide material has a thin thickness, wide bandgap (3 eV–4 eV), and a non-centrosymmetric structure, so it is a highly versatile material with a high-k dielectric constant and ferroelectric characteristics as an insulator.137 Theoretically, using 2D materials is ideal, but there are obstacles such as size effects and dead layers that affect ferroelectric properties. The dead layer is a phenomenon that occurs because ferroelectric properties are contaminated due to the strain on the adjacent surface and the local chemical environment. Since the 2D and vdW materials have a strong bond in the in-plane direction, they can be easily exploited, which can easily eliminate the external environment that causes the dead layer. In 2016, Liu et al. observed ferroelectric properties in layered CuInP2S6 using PFM and second-harmonic generation (SHG).138 Since then, FeFET research using 2D ferroelectric materials has been actively conducted.

The ferroelectric properties of 2D materials have directional properties. Group IV monochalcogenides (MX; M = Ge, Sn; X = S, Se) have an in-plane direction, and d1T-MoTe2 have an out-of-plane direction, and the III2-VI3 compound (In2Se3) has intercorrelated ferroelectrics.31,136,139–142 2D ferroelectric materials can be used for memory and synaptic devices in this direction.

Kwon et al. fabricated a synapse device using SnS as a channel and investigated its properties. A 6 nm-thick SnS (orthorhombic) was prepared by synthesizing SnS2 (hexagonal) using CVD and annealing at 400 °C for 30 min. It exhibited excellent characteristics as a synaptic device with a low leakage current at a thin thickness and a weak screen effect due to a small mobile charge concentration.136 In particular, it shows 92.1% higher cognitive ability in the virtual pattern recognition test.140 Unlike conventional SnS2, SnS belongs to the Pnma space group and induces polarization in the 2D channel with a non-centrosymmetric atomic structure.143 The second-harmonic generation (SHG) signal is measured at a thickness of less than 20 nm and is most strongly observed in 3.7 nm-thick SnS films. Unlike α-In2Se3, SnS has ferroelectric properties in the in-plane direction, so it has a limitation in reducing the degree of integration of the device. However, it is suitable for making a 2D photodetector or junction switch device in the horizontal direction. Unlike α-In2Se3, it does not require a passivation layer30 and shows the applicability of 2D ferroelectric materials for synaptic devices.140 

The memory performance and synaptic characteristics of flexible/epitaxial PZT-FeFETs have been studied until recently.80,81 Additionally, attempts have been made to increase the MW and decrease leakage current in the MFIS structure by introducing a HfO2 high-k material into the PZT layer.144 However, Pb has a special adverse effect on the human nervous system, and when lead accumulates in the body, it causes poisoning symptoms. The high lead volatility during the calcination and sintering process makes environmental pollution more serious.48,49 Due to such environmental regulations and the volatility of lead at high temperatures, the use of PZT is highly restricted. While maintaining the perovskite structure of PZT, research on lead-free ferroelectric perovskite oxides is actively underway. In general, BaTiO3 (BT), BiNaTiO3 (BNT), BiKTiO3 (BKT), and KNaNbO3 (KNN), which use alkali metal instead of lead in the perovskite structure, are the representative lead-free ferroelectric ceramics. However, when the alkali metal is used, the material has a very narrow sintering temperature, relatively poor ferroelectric properties, stability (corrosive), higher volatility, and a lower Curie temperature than that of PZT.90 Recently, even in the perovskite structure, ferroelectric properties were observed in 2D, not in a bulk system. Typically, d0 cations (Ti4+, Nb5+, and Ta5+) in BO6 octahedral units cause Jahn–Teller distortion of an asymmetric structure to exhibit ferroelectric properties. Ca2Na2Nb5O16 has ferroelectricity even at the 2.7 nm level.31 Ji et al. showed that three-unit-cell-thick SrTiO3 and BiFeO3 epitaxial films have ferroelectric properties on any substrate using the transfer process.145 However, when compared to the HZO film, ferroelectric properties are rapidly degraded at the thin thickness (under 10 nm) and high leakage current is generated with the small bandgap (3 eV–4 eV). For this reason, most of the research works on ferroelectric oxides have been mainly focused on HZO since 2011.28,29,104,146

HZO is the most prominent material for making the FeFET, and it is being studied a lot recently because it has strong ferroelectricity even in nm-thick scale and is capable of being used in the ALD process currently used in industrial processes. Doping, tensile stress, thickness effect, and interface states are controllable factors that can induce stronger ferroelectric properties. By controlling these growth conditions, HZO can induce higher polarization values at thin thickness than any ferroelectric materials including PZT and PVDF and at the same time has a sufficiently high dielectric constant. Hence, for high integration and low power drive of the circuit, it is necessary to use HZO, which maintains a ferroelectric characteristic even at a thickness of several nanometers in the form of NVM transistors and synaptic transistors.

PVDF is a next-generation material with the flexibility and the ferroelectricity required for various devices. It has the great advantage of having a bending radius that is incomparable to the flexible device using PZT introduced above. Research should focus on the on/off ratio and low power driving that allows for the optimization of the channel layer and ferroelectricity, which are the weaknesses of PVDF-FeFETs.62,67 Since the applicability as a biomaterial and the applicability of actual processes are high, it may have many advantages than metal oxide-based FeFETs represented by HZO.40 

For the FeS-FET device, ferroelectric 2D materials were used as the semiconductor layer. If a device is fabricated using 2D materials and a circuit is constructed, it will be possible to make a low-power device, a highly integrated memory, and synaptic device in a manner different from before. However, applying the highly uniform large scale of 2D materials to the existing process industry system is still challenging and must be supplemented.147 

In addition to this, it is possible to improve the performance of the FeFET through structural changes in the device, apart from the material properties of ferroelectric. Ferroelectric materials can also be used in low-power driving devices in the form of a negative capacitance field effect transistor (NCFET). In the NCFET, a ferroelectric layer is deposited between the gate electrode layer and the dielectric, causing a negative capacitance phenomenon, so that a SS with a Boltzmann limit can be achieved below 60 mV. This means that it can be switched with minimal energy compared to other FETs, and it is a promising next-generation logic device.148 

We reviewed the ferroelectricity of representative ferroelectric materials such as PZT, PVDF, HZO, and 2D materials and the characteristics of FeFET and FeS-FET devices. Each ferroelectric material had polarization due to its non-centrosymmetric structure, and it remained strong even when the external electric field was removed. The polarization was varied according to external conditions, and this was mainly analyzed through PFM and P–E curves. FeFET, FeS-FET, and MFIS structures using ferroelectric materials have the characteristics of memory or synaptic devices, which were evaluated based on electrical properties. HZO had a large MW and SW by maintaining strong ferroelectric properties even in a thin film state, which was very useful for fabricating memory and synaptic devices, respectively. A device using PVDF is flexible and works even with a small bending radius. PZT has a high thermal stability and an on/off ratio even in a flexible device using a mica substrate. The FeS-FET using the 2D material has improved retention, which is a weak point of the existing FeFETs. Although each device has disadvantages such as power consumption, on/off ratio, retention, endurance, 2D material shape control, and environmental problems, research will proceed in a direction that can address these disadvantages.

This research was supported by the National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT (Grant No. 2020M2D8A206983011) and the Ministry of Science, ICT & Future Planning (Grant No. 2017R1A2B3009135). The Inter-University Semiconductor Research Center and Institute of Engineering Research at Seoul National University provided research facilities for this work.

Data sharing is not applicable to this article as no new data were created or analyzed in this study.

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