Recent advances in the field of integrated circuits based on sustainable and transparent amorphous oxide semiconductors (AOSs) are presented, demonstrating ultrahigh performance operating state-of-the-art integrated inverters comprising metal–semiconductor field-effect transistors (MESFETs) with amorphous zinc tin oxide (ZTO) as a channel material. All individual circuit layers have been deposited entirely at room temperature, and the completed devices did not require undergoing additional thermal annealing treatment in order to facilitate proper device functionality. The demonstrated ZTO-based MESFETs exhibit current on/off ratios of over 8 orders of magnitude a field-effect mobility of 8.4 cm2 V−1 s−1, and they can be switched within a voltage range of less than 1.5 V attributed to their small subthreshold swing as low as 86 mV decade−1. Due to adjustments of the circuit layout and, thus, the improvement of certain geometry-related transistor properties, the associated Schottky diode FET logic inverters facilitate low-voltage switching by exhibiting a remarkable maximum voltage gain of up to 1190 with transition voltages of only 80 mV while operating at low supply voltages ≤3 V and maintaining a stable device performance under level shift. To the best of our knowledge, the presented integrated inverters clearly exceed the performance of any similar previously reported devices based on AOS, and thus, prove the enormous potential of amorphous ZTO for sustainable, scalable low-power electronics within future flexible and transparent applications.

Recent developments in the field of active thin-film technology have advanced beyond use in common active-matrix flat-panel display backplanes toward manifold applications, such as photovoltaics and wireless communication systems, as well as memory and sensor elements. Conventionally deployed polycrystalline and amorphous silicon, however, struggles to keep up with the continuously growing demand for scalable electronics operating at higher frequencies, especially when future trends aim for developing mechanically flexible and transparent multifunctional thin-film devices with low power consumption.1,2 These unique requirements can currently be satisfied using predominantly ZnO-based amorphous oxide semiconductors (AOSs), in particular, indium gallium zinc oxide (IGZO). However, the increasing scarcity and cost of indium and gallium in the context of their high criticality triggered recent efforts to substitute IGZO with the alloy systems composed of naturally abundant elements.3 

An emerging, yet by far less mature, alternative is amorphous zinc tin oxide (ZTO), since ZTO comprises only earth-abundant as well as non-toxic elements, and it exhibits high transparency in the visible spectral range and facilitates fabrication at room temperature with free-carrier mobilities exceeding 10 cm2 V−1 s−1.4 The first successful integration of ZTO as an active channel material in metal–insulator–semiconductor field-effect transistors (MISFETs) already dates back to 2005, followed by numerous studies reporting on either the sputtered or the solution-processed ZTO thin films and the corresponding devices, such as inverters and ring oscillators.5 Nonetheless, the majority of previously published results involve high processing temperatures of ZTO or additional thermal post-deposition annealing treatment to obtain proper device functionality.

As an alternative approach to conventional MISFETs, Dang et al. demonstrated the first metal–semiconductor field-effect transistors (MESFETs) based on ZTO in 2017, exhibiting subthreshold swings of only 180 mV decade−1 and consequently enabling low-voltage switching due to the absence of a gate dielectric.6 Even though MISFETs maintain a significantly lower gate leakage current, MESFETs are overall capable of low-voltage operation as well as faster switching, since carrier scattering processes at the channel–insulator interface do not have to be taken into account and, thus, are more suitable for high-frequency applications. Recently, we demonstrated the first room-temperature-fabricated integrated circuits and ZTO-based FETs with even lower subthreshold swings of 61 mV decade−1, approaching the thermodynamic limit and exhibiting high current on/off ratios over 8 orders of magnitude.7–9 Even though no additional annealing was performed, the corresponding inverters attained full swing and high gain of 347 using a supply voltage of 5 V.

To facilitate potential cascading of multiple inverters containing only unipolar transistors, we used the Schottky diode FET logic approach (SDFL) to obtain a compatible output voltage range required to switch a subsequent inverter. Compared to the complementary metal-oxide-semiconductor (CMOS) logic, based on p-type and n-type FETs, or direct-coupled FET logic (DCFL), using enhancement and depletion mode transistors, the SDFL inverter requires only one deposition step to prepare both channels of the transistors simultaneously. By employing an improved circuit layout regarding the geometry and, thus, the properties of associated transistors, the presented integrated inverters were capable of exhibiting ultrahigh performance, demonstrating a remarkable, highest yet reported maximum voltage gain of 1190 with a uncertainty level of only 80 mV for a supply voltage of 3 V, resulting in a peak gain magnitude per volt of pgm/VDD = 397 V−1.

Devices and circuits have been patterned using photolithography with a conventional lift-off process and, thus, were exposed to maximum baking temperatures of 110 °C for no longer than 60 s, required to develop photo-resist structures. ZTO thin films with a cation composition of 1:1 Zn:Sn have been deposited on 10 × 10 mm2 SiO2 substrates at room temperature by long-throw radio frequency (RF) magnetron sputtering using a single ceramic target. The sputtering process was ignited in an oxygen-rich atmosphere, inducing oxygen incorporation during thin film growth in order to prevent the formation of a highly conductive electron accumulation layer close to the ZTO-substrate interface that inhibits sufficient depletion of the channel.7 Subsequently, a conductive ZTO thin film has been deposited on top of the 10 nm thin intrinsic buffer layer (ρ ≫ 103 Ω m). A large target-to-substrate distance of 25 cm has been chosen to enable homogeneous growth and to reduce sputter-induced damage.10 Information on the layer thickness of ZTO channels have been obtained by performing x-ray reflectivity measurements.

Source and drain contacts consist of ∼50 nm Au, deposited by DC sputtering at room temperature. Prior to the gate fabrication, another thin intrinsic ZTO layer has been deposited on top of the active channel to reduce the leakage current through the gate diode by saturating under-coordinated cation bonds due to a transfer of oxygen near the channel surface.11,12 The metal contacts of the Schottky diodes required for level shifting and transistor gate contacts, consisting of 50 nm PtOx with a Pt capping layer, have been fabricated in a single deposition process by long-throw RF magnetron sputtering at room temperature. A corresponding schematic cross section through a MESFET, illustrating the basic material stacking order, is depicted Fig. S1(a) in the supplementary material. As a final step, the Pt capping layers of each i-ZTO/PtOx/Pt stack have been directly connected to associated underlying Au conduction paths, for instance, at the inverter input or output, by 10 nm DC sputtered Au in order to obtain ideal ohmic behavior [Fig. S1(b) in the supplementary material].8 Since the Schottky diodes and unipolar transistor structures are patterned simultaneously, the employed SDFL approach requires the same amount or even less processing steps (five photolithography steps in the present case) compared to the conventional CMOS layout, where the deposition of n-type and p-type semiconductors, as well as the often required additional thermal annealing step has to be taken into account.

Static current–voltage characteristics were recorded using an Agilent 4155C semiconductor parameter analyzer and a SÜSS wafer prober system. The electrical properties of ZTO thin films have been determined by performing Hall effect measurements in the Van-der-Pauw geometry at room temperature.

Static room-temperature transfer characteristics and the corresponding absolute gate leakage currents |IG| of ZTO/PtOx-based MESFETs with varying channel thickness d are depicted in Fig. 1. The source–drain voltage was fixed at 2 V for all measurements. The investigated devices contain multi-gate structures with gate lengths of L = 3 µm and a total gate width of W = 400 µm. A schematic cross section through a MESFET, illustrating the basic material stacking order, is displayed in Fig. S1(a) in the supplementary material. The corresponding electrical properties of each ZTO channel, determined by Hall effect measurements, as well as the associated characteristic transistor parameters are compared within Table I. All MESFETs exhibit a clear field effect with current on/off ratios as high as 8 orders of magnitude and can be switched on and off within a low gate voltage range ΔVG < 2.5 V, given by the difference between the threshold voltage and the on-voltage, where ID saturates. By increasing the channel thickness from 9 nm to 13 nm, a significant increase in the on-current, and thus, the maximum transconductance gmax from 8 µS to 525 µS is observed, since gmax is limited by the channel resistivity and by the leakage current over the gate diode. Simultaneously, the off-current shifts from 8 × 10−13 A (d = 9 nm) to 3 × 10−9 A (d = 13 nm) due to an increased amount of leakage current flow over the gate diode for gate voltages VG ≤ −1 V. All the investigated devices are normally on with the threshold voltages VT ranging from −380 mV (d = 13 nm) to −80 mV (d = 9 nm). As expected, VT shifts toward more negative source–gate voltages with increasing the channel thickness. Consequently, the lowest subthreshold swing S of 86 mV decade−1 is obtained for the MESFET with the lowest channel thickness of 9 nm. A slight dependency of VT on the voltage sweep direction as well as a crossing of ID around VG = 0 V is observable for the majority of measured transistors. This hysteresis is likely to be attributed to the localized states close to the ZTO/PtOx interface, acting as charge traps.13 An estimation of the field-effect mobility μFE was done using the maximum transconductance gmax, determined by the channel conductivity and calculated from the transfer characteristics displayed in Fig. 1. The expression μFE = gmaxL/(endW) yields a field-effect mobility of 1.5 cm2 V−1 s−1 (d = 9 nm), 6.8 cm2 V−1 s−1 (d = 11 nm), and 8.4 cm2 V−1 s−1 (d = 13 nm), where e, n, d, and W denote the elementary charge, the charge carrier concentration, the channel thickness of the MESFET, and the gate width, respectively. However, μFE of only 1.5 cm2 V−1 s−1 clearly underestimates the corresponding Hall mobility of 6.7 cm2 V−1 s−1 since gmax cannot be reached due to limiting effects induced by the increasing gate leakage current occurring for VG > 1.5 V.

FIG. 1.

Room-temperature transfer characteristics (teal) and the corresponding gate leakage currents |IG| (orange) of ZTO/PtOx-based MESFETs with varying channel thickness d, as labeled. The source–drain voltage was fixed at VD = 2 V for all measurements. Solid and dashed lines correspond to the voltage sweep direction from negative to positive gate voltages and vice versa, respectively.

FIG. 1.

Room-temperature transfer characteristics (teal) and the corresponding gate leakage currents |IG| (orange) of ZTO/PtOx-based MESFETs with varying channel thickness d, as labeled. The source–drain voltage was fixed at VD = 2 V for all measurements. Solid and dashed lines correspond to the voltage sweep direction from negative to positive gate voltages and vice versa, respectively.

Close modal
TABLE I.

Characteristic parameters of ZTO-based MESFETs, depicted in Fig. 1, as well as the electrical properties of the corresponding ZTO channels with various thicknesses d determined by Hall effect measurements at room temperature.

dμHnSgmaxμFEVTVD
(nm)(cm2 V−1 s−1)(cm−3)log(ION/IOFF)(mV decade−1)(μS)(cm2 V−1 s−1)(mV)(V)
6.7 2.8 × 1017 6.9 86 1.5 −80 
11 7.8 1.1 × 1018 8.1 285 168 6.8 − 180 
13 8.8 2.2 × 1018 5.2 526 525 8.4 − 380 
dμHnSgmaxμFEVTVD
(nm)(cm2 V−1 s−1)(cm−3)log(ION/IOFF)(mV decade−1)(μS)(cm2 V−1 s−1)(mV)(V)
6.7 2.8 × 1017 6.9 86 1.5 −80 
11 7.8 1.1 × 1018 8.1 285 168 6.8 − 180 
13 8.8 2.2 × 1018 5.2 526 525 8.4 − 380 

Figure 2(a) schematically illustrates the circuit layout of an SDFL inverter that is investigated in the present study. The input of the basic inverter configuration, containing a driving (DRV) transistor, responsible for switching, and a pull-up (PU) transistor as load with source and gate shorted, is connected to an additional pull-down (PD) transistor with WLPD=13WLDRV and three forward-biased n-ZTO/i-ZTO/PtOx/Pt Schottky barrier diodes with an individual area of 450 µm2 for level shifting in terms of voltage drops across the diodes. VGND = 0 V and VDD denote the constant operating voltages, applied to the ground potential and to the drain side of the PU transistor, respectively. While the DRV transistor has to be provided with a gate voltage VG = VIN in the range of at least −VTVINVDD + VT to switch between high and low output levels, the PD transistor is supplied with a negative voltage Vbias and serves as a constant-current supply for the diodes. A level shift configuration is necessary to obtain a compatible output voltage range in order to enable the cascading of multiple inverters, for instance, required within ring oscillators or related interconnected logic circuit applications.14 The geometry ratio between the DRV transistor and the PU transistor is β = (W/L)DRV/(W/L)PU = 0.5 for all investigated inverters.

FIG. 2.

(a) Schematic basic circuit layout of an SDFL inverter, employing a pull-down transistor (PD) and three ZTO/PtOx Schottky barrier diodes for the level shifting of the output signal. DRV and PU denote the driving transistor and pull-up transistor, respectively. (b) VTCs of a ZTO-based SDFL inverter without and with a series connection of up to three level-shifting diodes, comprising MESFETs with a channel thickness of 9 nm as well as W/L = 67, and operating at supply voltages VDD between 1 V and 3 V. (c) Behavior under level shift and VDD-dependence of pgm values, as well as uncertainty levels (transition voltages) of inverters based on the MESFETs depicted in Fig. 1.

FIG. 2.

(a) Schematic basic circuit layout of an SDFL inverter, employing a pull-down transistor (PD) and three ZTO/PtOx Schottky barrier diodes for the level shifting of the output signal. DRV and PU denote the driving transistor and pull-up transistor, respectively. (b) VTCs of a ZTO-based SDFL inverter without and with a series connection of up to three level-shifting diodes, comprising MESFETs with a channel thickness of 9 nm as well as W/L = 67, and operating at supply voltages VDD between 1 V and 3 V. (c) Behavior under level shift and VDD-dependence of pgm values, as well as uncertainty levels (transition voltages) of inverters based on the MESFETs depicted in Fig. 1.

Close modal

Exemplary voltage transfer characteristics (VTCs) of an SDFL inverter based on MESFETs with a channel thickness of 9 nm and W/L = 67 are depicted in Fig. 2(b). The VTCs approach the applied supply voltages VDD between 1 V and 3 V, and thus, exhibit full swing, even while operating under level shift with up to three diodes connected to the input. Vbias was fixed at −2 V, causing the PD transistor to constantly operate in saturation. The VTCs exhibit a shift of the output signal toward positive input voltages by means of the voltage drop Vshift across the ZTO/PtOx diodes. Vshift is strongly dependent on the thickness of the ZTO layer, resulting in a voltage shift per diode of 0.3 V, 0.7 V, and 1.5 V for d of 9 nm, 11 nm, and 13 nm, respectively. A slight dependence on the voltage sweep direction is observed for the case without the level shift (not shown); however, the hysteresis of the output voltage remains below 20 mV and can further be reduced by increasing the integration time during the input voltage modulation. Important figures of merit to evaluate the performance of inverters are the maximum gain or the peak gain magnitude pgm = max|∂VOUT/∂VIN| and the uncertainty level VUC, also referred to as the transition voltage, defined as the input voltage difference between the transition points of a VTC where the absolute value of the gain equals unity.

The VDD-dependence of pgm values as well as VUC for all three inverters based on MESFETs with varying channel thicknesses of 9 nm, 11 nm and 13 nm is depicted in Fig. 2(c) for the case with and without the level shift. All SDFL inverters exhibit reasonable performance stability under level shift; only slight deviations of the pgm are observed at VDD = 3 V for a channel thickness of 11 nm. As expected, the pgm is clearly dependent on VDD and increases for higher supply voltages. VUC, on the other hand, seems to be unaffected by varying VDD, except for a channel thickness of 13 nm, where the uncertainty level increases from 250 mV (VDD = 1 V) to 400 mV (VDD = 3 V). The highest pgm of 560 (VDD = 3 V) is obtained for the inverter with a ZTO channel thickness of 11 nm, while the lowest uncertainty level of 56 mV results for the MESFET-based inverter with a 9 nm ZTO channel, since the corresponding transistors exhibit the by far lowest subthreshold swing and highest threshold voltage. It should be noted that among the three SDFL inverters, the one based on MESFETs with the highest channel thickness of 13 nm, and consequently with the lowest threshold voltage of −380 mV does not quite approach the low output level of 0 V and exhibits a voltage swing of 2.75 V at VDD = 3 V. This is due to the fact that the low threshold voltage causes the PU transistor to increasingly operate in saturation at higher ID. Consequently, VDD divides over both DRV transistor and PU transistor, even though VDD is supposed to entirely drop across the PU transistor for VIN ≫ 0 V. Furthermore, the lower VT for MESFETs with the highest channel thickness explains the smaller gain and the larger transition voltage compared to the other devices with threshold voltages closer to zero. The overall high gain and low transition voltage obtained for the presented inverters results from the high threshold voltage of the MESFETs approaching 0 V as well as the excellent current saturation behavior of ID,sat. As soon as VDD is larger than 2|VT|, the maximum gain occurs at VDD/2 close to VIN ≈ 0 V and is then determined by the saturation behavior of the drain current of both DRV and PU transistor, given by

ID,sat=IP13VbiVINVP+2VbiVINVP3/2+α(VDVP+Vbi),
(1)

where the second summand corresponds to an empirical term, describing the non-zero slope of ID,sat with increasing VD for non-ideal devices.15,16 In the literature, α=ID,sat/VD|VG is often outlined in terms of a finite output resistance ro1, modeling the linear dependence of ID,sat on VD.17 Thus, VT close to zero and low α are favorable to obtain high gain within a narrow transition voltage regime.

Recently, we demonstrated the first ZTO-based SDFL inverters comprising ZTO/PtOx MESFETs, operating at VDD = 3 V with a maximum gain as high as 108 and a transition voltage of 270 mV.8 Since the previously employed active ZTO channel layers exhibited similar electrical properties compared to the here presented devices, the significant improvement of the inverters with voltage gains exceeding 1000 and VUC below 100 mV is consequently related to performance-enhancing adaptations regarding the circuit layout and the transistor geometry. Unlike the conventional MISFETs, where the source and drain contacts overlap the gate at the edges due to the often preferred bottom-gate layout, MESFETs have a gap between gate and source/drain contacts, denoted by the length Z of the exposed parts of the channel. Z contributes considerably to the series resistances of the channel RS = ρZ/(Wd), lowering both the effective drain voltage by 2VS and the gate voltage by VS due to the voltage drop VS = RSID across RS.35 A decrease of Z from 10 µm to 5 µm for the DRV, PU, and PD transistors, implemented in the presented inverters, consequently yields a significant increase in gmax, and thus, a higher current on/off ratio. The smaller voltage drop across Z = 5 µm increases the effective VD and VG compared to the transistors with Z = 10 µm. As a result, VT slightly shifts toward higher gate voltages and an improved subthreshold swing is observable, both of which are desirable to obtain high-gain inverters operating at low voltages. Additionally, a decrease of α from 11 nA/V to 4 nA/V (W/L = 10) by reducing Z from 10 µm to 5 µm is notable. The same applies to higher W/L ratios due to the lowered transconductance and the increased effective channel length for VD > VGVT.17 Exemplary output characteristics, illustrating the geometry-dependency of α according to Eq. (1), are depicted in Fig. 3 for W/L ranging from 5 to 67.

FIG. 3.

Output characteristics of MESFETs with various W/L ratios and a channel thickness of 11 nm, recorded at 0 V gate bias. α denotes the non-zero slope of the saturation drain current with increasing VD, extracted by a linear fit of ID,sat.

FIG. 3.

Output characteristics of MESFETs with various W/L ratios and a channel thickness of 11 nm, recorded at 0 V gate bias. α denotes the non-zero slope of the saturation drain current with increasing VD, extracted by a linear fit of ID,sat.

Close modal

The previously reported SDFL inverters exhibited a dependence of Vshift on the total amount of level-shifting diodes, resulting in a reduction of Vshift with an increase in the number of diodes connected to the input.8 To further improve the former inverter layout, the Pt capping layer of the corresponding gate contacts has been connected to their associated underlying conduction paths using a thin Au layer to bypass the i-ZTO buffer as well as PtOx in order to obtain ideal ohmic connections between conduction paths and gate contacts [Fig. S1(b) in the supplementary material]. The conduction path crossings between VDD, VGND, and Vbias have been removed as well to reduce the amount of parasitic capacitances present in the former circuit layout, and thus, to favor the operation at lower voltages (Fig. S2 in the supplementary material).8 Eventually, the inverters with the adapted circuit layout have been fabricated and are compared regarding the impact of different W/L ratios (Z = 5 µm) on the device performance. The resulting pgm values and VUC of an SDFL inverter based on MESFETs with a channel thickness of d = 11 nm and varying W/L between 5 and 67 are displayed in Fig. 4. A significant improvement of the pgm and VUC for lower W/L ratios is observed. The associated drain current saturation behavior in dependence on W/L is depicted in Fig. 4(a) for an ensemble of 20 MESFETs and the corresponding exemplary output characteristics are compared in Fig. 3. Decreasing W/L from 67 to 5 yields a noticeable improvement of α from 47 nA/V to 1 nA/V. The inverters with W/L = 5 exhibit a superior voltage gain as high as 1190, and simultaneously an uncertainty level of only 80 mV, which are, to the best of the authors’ knowledge, the highest yet reported pgm and lowest VUC values for inverters based on any amorphous oxide semiconductor. It should be noted that a slight shift of the VTC toward larger input voltages in the range of 7 µV–30 µV, attributed to the geometry ratio of β = 0.5, as well as a small dependency on the voltage sweep direction are observable, resulting from the hysteresis of the MESFETs, as depicted in Fig. 1.

FIG. 4.

(a) Impact of the transistor geometry ratio on the drain current saturation behavior as a function of VD, described by the non-zero slope α and extracted for an ensemble of 20 MESFETs with various W/L. The deviations of α are denoted by the error bars. (b) Dependence of the pgm and VUC on the W/L ratio for SDFL inverters implementing MESFETs with a channel thickness of 11 nm, using an operating voltage of VDD = 3 V. (c) VTC and the corresponding voltage gain of the best inverter for VDD = 3 V, based on MESFETs with W/L = 5 and α = 1 nA/V.

FIG. 4.

(a) Impact of the transistor geometry ratio on the drain current saturation behavior as a function of VD, described by the non-zero slope α and extracted for an ensemble of 20 MESFETs with various W/L. The deviations of α are denoted by the error bars. (b) Dependence of the pgm and VUC on the W/L ratio for SDFL inverters implementing MESFETs with a channel thickness of 11 nm, using an operating voltage of VDD = 3 V. (c) VTC and the corresponding voltage gain of the best inverter for VDD = 3 V, based on MESFETs with W/L = 5 and α = 1 nA/V.

Close modal

To put the obtained results into context, the key properties of all previously published ZTO-based inverters are compared within Table II. The ZTO channels have either been fabricated by RF sputtering or using inkjet-printing and solution-processing techniques. Alongside often required high operating voltages, the majority of the so far reported ZTO-based inverters rely on fabrication-method-related deposition at elevated temperatures exceeding 150 °C or additional thermal annealing to obtain functional devices. A more comprehensive comparison of more than 200 AOS-based inverters reported in the literature has been provided by Schlupp et al.34 To further facilitate performance comparability, the figure of merit pgm/VDD is compared in Fig. 5 for all the devices listed in Table II. The inverters presented in this study attain the highest yet reported pgm per VDD of 397 V−1, and thus, represent current state-of-the-art ZTO-based devices.

TABLE II.

Comparison of so far published results on ZTO-based inverters. Logic types: CMOS (complementary metal-oxide-semiconductor); SDFL (Schottky diode FET logic); DCFL (direct-coupled FET logic); NMOS (n-type metal-oxide-semiconductor). Tprocess corresponds to the maximum temperature during either the deposition process of the ZTO channel or during post-deposition thermal annealing treatment [(RT) room temperature]. Boldface values correspond to the results reported in this work, representing current state-of-the-art inverters based on amorphous oxide semiconductors.

MethodFET typeLogic typeTprocess (°C)VDD (V)pgmVUC (V)YearReferences
RF-sputtered MISFET DCFL 425 10 10.6 1.87 2009 18  
Inkjet-printed MISFET NMOS 500 10 2a >10a 2010 19  
Sol.-processed MISFET DCFL 500 60 9.9 >10a 2011 20  
RF-sputtered MISFET DCFL 425 10 1.4 2011 21  
Sol.-processed MISFET CMOS 500 40 >5a 2013 22  
Inkjet-printed MISFET CMOS 200 22.8 0.3a 2014 23  
Inkjet-printed MISFET CMOS 500 17.1 0.5a 2014 24  
Inkjet-printed MISFET CMOS 500 9.3 2a 2014 25  
Sol.-processed MISFET DCFL 500 15 23.2 1a 2015 26  
Inkjet-printed MISFET CMOS 500 34a 0.5a 2015 27  
RF-sputtered MISFET DCFL 500 10 25.2 2.4 2015 28  
Sol.-processed MISFET NMOS 350 2.5 11 0.28 2017 29  
RF-sputtered MISFET NMOS 300 10 3.5 4a 2018 30  
RF-sputtered MISFET NMOS 150 0.5a 2018 31  
RF-sputtered MESFET NMOS RT 119 0.13 2018 7  
RF-sputtered MESFET SDFL RT 294 0.27 2019 8  
RF-sputtered JFET SDFL RT 347 0.26 2019 8  
RF-sputtered MESFET SDFL RT 83 0.5 2019 14  
RF-sputtered MISFET CMOS 300 20 4.2 >10a 2019 32  
Sol.-processed MISFET NMOS 520 12.1 0.96 2020 33  
RF-sputtered JFET NMOS RT 464 0.13 2020 34  
RF-sputtered MESFET SDFL RT 3 1190 0.08 2020 This work 
MethodFET typeLogic typeTprocess (°C)VDD (V)pgmVUC (V)YearReferences
RF-sputtered MISFET DCFL 425 10 10.6 1.87 2009 18  
Inkjet-printed MISFET NMOS 500 10 2a >10a 2010 19  
Sol.-processed MISFET DCFL 500 60 9.9 >10a 2011 20  
RF-sputtered MISFET DCFL 425 10 1.4 2011 21  
Sol.-processed MISFET CMOS 500 40 >5a 2013 22  
Inkjet-printed MISFET CMOS 200 22.8 0.3a 2014 23  
Inkjet-printed MISFET CMOS 500 17.1 0.5a 2014 24  
Inkjet-printed MISFET CMOS 500 9.3 2a 2014 25  
Sol.-processed MISFET DCFL 500 15 23.2 1a 2015 26  
Inkjet-printed MISFET CMOS 500 34a 0.5a 2015 27  
RF-sputtered MISFET DCFL 500 10 25.2 2.4 2015 28  
Sol.-processed MISFET NMOS 350 2.5 11 0.28 2017 29  
RF-sputtered MISFET NMOS 300 10 3.5 4a 2018 30  
RF-sputtered MISFET NMOS 150 0.5a 2018 31  
RF-sputtered MESFET NMOS RT 119 0.13 2018 7  
RF-sputtered MESFET SDFL RT 294 0.27 2019 8  
RF-sputtered JFET SDFL RT 347 0.26 2019 8  
RF-sputtered MESFET SDFL RT 83 0.5 2019 14  
RF-sputtered MISFET CMOS 300 20 4.2 >10a 2019 32  
Sol.-processed MISFET NMOS 520 12.1 0.96 2020 33  
RF-sputtered JFET NMOS RT 464 0.13 2020 34  
RF-sputtered MESFET SDFL RT 3 1190 0.08 2020 This work 
a

Quantitative values have been estimated from figures.

FIG. 5.

Comparison of the figure of merit pgm/VDD for the entirety of ZTO-based inverters published so far. Filled symbols correspond to the inverters employing ZTO thin films that have been deposited at room temperature and did not undergo additional thermal annealing to accomplish sufficient device functionality. The dashed line corresponds to the temporal evolution of the overall highest pgm/VDD values per year.

FIG. 5.

Comparison of the figure of merit pgm/VDD for the entirety of ZTO-based inverters published so far. Filled symbols correspond to the inverters employing ZTO thin films that have been deposited at room temperature and did not undergo additional thermal annealing to accomplish sufficient device functionality. The dashed line corresponds to the temporal evolution of the overall highest pgm/VDD values per year.

Close modal

The capability of amorphous ZTO to obtain state-of-the-art, ultrahigh-performing integrated inverters based on MESFETs has been demonstrated. Furthermore, all individual implemented thin film layers have been fabricated entirely at room temperature and did not require undergoing post-deposition thermal annealing in order to facilitate sufficient device functionality. To provide the possibility of cascading multiple inverters based on unipolar devices, the SDFL approach has been deployed to maintain a compatible output voltage range by integrating additional ZTO-based Schottky diodes for level shifting.

MESFETs with different ZTO channel thickness have been compared regarding their DC performance, exhibiting current on/off ratios of over 8 order of magnitude and a field-effect mobility of up to 8.4 cm2 V−1 s−1. The presented devices operate at low voltage and exhibit a subthreshold swing as low as 86 mV decade−1 due to the absence of a gate dielectric. The associated ZTO-based inverters attain remarkable voltage gain of up to 1190 for a supply voltage of 3 V and can be switched within an input transition voltage range of only 80 mV. In contrast, the inverters based on amorphous IGZO so far do not exceed a maximum gain of 226 (VDD = 3 V), while requiring a processing temperature of at least 225 °C.36 Comparing the figure of merit pgm/VDD with the entirety of the so far published results on the ZTO-based inverters yields the highest yet achieved value for maximum gain per supply voltage of 397 V−1 in the case of the here demonstrated devices.

Overall, our results exemplify the enormous potential of amorphous ZTO-based integrated circuits as a promising indium-free alternative to widely commercially exploited IGZO, even though the conventional IGZO-based transistors and the related integrated circuits are, in addition, typically annealed at temperatures above 150 °C to enhance the device performance. Restriction to room temperature deposition further facilitates the transfer of devices from rigid to thermally unstable, flexible substrates, paving the way for novel transparent, bendable circuitry and sustainable, low-cost applications with reasonable dynamic capability based on amorphous ZTO.

See the supplementary material for a schematic illustration of the basic material stacking order employed in the demonstrated devices as well as laser-scanning microscopy images depicting the circuit design of the presented integrated inverters. Figure S1—Illustration of (a) the basic material stacking order of a ZTO-based MESFET and (b) the schematic cross section through the DRV/PU/PD FET, including an additional Au capping required to bypass the i-ZTO/PtOx layers in order to ensure ideal ohmic behavior between gate contacts and the underlying Au conduction paths. A distance between the conduction path and the channel of 20 µm was chosen to compensate any potential misalignment during photolithographic patterning. Figure S2—Microscopic image of (a) the here presented integrated SDFL inverter layout and (b) the former circuit design,8 implementing the conduction path crossings insulated by a 200 nm HfOy layer that appears bluish and yellowish due to thin film interferences. (c) Depiction of the corresponding SDFL circuit schematic of both inverters.

The data that support the findings of this study are available from the corresponding author upon reasonable request.

Parts of this work have been funded by Deutsche Forschungsgemeinschaft within the framework of Schwerpunktprogramm SPP 1796 “High Frequency Flexible Bendable Electronics for Wireless Communication Systems (FFlexCom)” (Grant No. GR 1011/31-2). We further acknowledge support from Leipzig University for Open Access Publishing.

1.
J. F.
Wager
, “
Transparent electronics
,”
Science
300
,
1245
1246
(
2003
).
2.
M.
Grundmann
,
H.
Frenzel
,
A.
Lajn
,
M.
Lorenz
,
F.
Schein
, and
H.
von Wenckstern
, “
Transparent semiconducting oxides: Materials and devices
,”
Phys. Status Solidi A
207
,
1437
1449
(
2010
).
3.
M.
Lokanc
,
R.
Eggert
, and
M.
Redlinger
, “
The availability of indium: The present, medium term, and long term
,” Technical Report No. NREL/SR-6A20-62409,
National Renewable Energy Laboratory (NREL)
,
Golden, CO, USA
,
2015
.
4.
P.
Schlupp
,
H.
von Wenckstern
, and
M.
Grundmann
, “
Amorphous zinc–tin oxide thin films fabricated by pulsed laser deposition at room temperature
,”
MRS Proc.
1633
,
101
104
(
2014
).
5.
H. Q.
Chiang
,
J. F.
Wager
,
R. L.
Hoffman
,
J.
Jeong
, and
D. A.
Keszler
, “
High mobility transparent thin-film transistors with amorphous zinc tin oxide channel layer
,”
Appl. Phys. Lett.
86
,
013503
(
2005
).
6.
G. T.
Dang
,
T.
Kawaharamura
,
M.
Furuta
, and
M. W.
Allen
, “
Zinc tin oxide metal semiconductor field effect transistors and their improvement under negative bias (illumination) temperature stress
,”
Appl. Phys. Lett.
110
,
073502
(
2017
).
7.
S.
Vogt
,
H.
von Wenckstern
, and
M.
Grundmann
, “
MESFETs and inverters based on amorphous zinc-tin-oxide thin films prepared at room temperature
,”
Appl. Phys. Lett.
113
,
133501
(
2018
).
8.
O.
Lahr
,
Z.
Zhang
,
F.
Grotjahn
,
P.
Schlupp
,
S.
Vogt
,
H.
von Wenckstern
,
A.
Thiede
, and
M.
Grundmann
, “
Full-swing, high-gain inverters based on ZnSnO JFETs and MESFETs
,”
IEEE Trans. Electron Devices
66
,
3376
3381
(
2019
).
9.
O.
Lahr
,
M. S.
Bar
,
H.
von Wenckstern
, and
M.
Grundmann
, “
All-oxide transparent thin-film transistors based on amorphous zinc tin oxide fabricated at room temperature: Approaching the thermodynamic limit of the sub-threshold swing
,”
Adv. Electron. Mater.
(published online
2020
).
10.
H.
Frenzel
,
T.
Dörfler
,
P.
Schlupp
,
H.
von Wenckstern
, and
M.
Grundmann
, “
Long-throw magnetron sputtering of amorphous Zn–Sn–O thin films at room temperature
,”
Phys. Status Solidi A
212
,
1482
1486
(
2015
).
11.
P.
Schlupp
,
F.-L.
Schein
,
H.
von Wenckstern
, and
M.
Grundmann
, “
All amorphous oxide bipolar heterojunction diodes from abundant metals
,”
Adv. Electron. Mater.
1
,
1400023
(
2015
).
12.
P.
Schlupp
,
H.
von Wenckstern
, and
M.
Grundmann
, “
Schottky barrier diodes based on room temperature fabricated amorphous zinc tin oxide thin films
,”
Phys. Status Solidi A
214
,
1700210
(
2017
).
13.
F. J.
Klüpfel
,
F.-L.
Schein
,
M.
Lorenz
,
H.
Frenzel
,
H.
von Wenckstern
, and
M.
Grundmann
, “
Comparison of ZnO-based JFET, MESFET, and MISFET
,”
IEEE Trans. Electron Devices
60
,
1828
1833
(
2013
).
14.
O.
Lahr
,
S.
Vogt
,
H.
von Wenckstern
, and
M.
Grundmann
, “
Low-voltage operation of ring oscillators based on room-temperature-deposited amorphous zinc-tin-oxide channel MESFETs
,”
Adv. Electron. Mater.
5
,
1900548
(
2019
).
15.
W.
Shockley
, “
A unipolar “field-effect” transistor
,”
Proc. IRE
40
,
1365
1376
(
1952
).
16.
F. J.
Klüpfel
,
A.
Holtz
,
F.-L.
Schein
,
H.
von Wenckstern
, and
M.
Grundmann
, “
All-oxide inverters based on ZnO channel JFETs with amorphous ZnCo2O4 gates
,”
IEEE Trans. Electron Devices
62
,
4004
4008
(
2015
).
17.
A. S.
Sedra
and
K. C.
Smith
,
Microelectronic Circuits
, 5th ed. (
Oxford University Press
,
2004
).
18.
D. P.
Heineck
,
B. R.
McFarlane
, and
J. F.
Wager
, “
Zinc tin oxide thin-film-transistor enhancement/depletion inverter
,”
IEEE Electron Device Lett.
30
,
514
516
(
2009
).
19.
Y.-H.
Kim
,
K.-H.
Kim
,
M. S.
Oh
,
H. J.
Kim
,
J. I.
Han
,
M.-K.
Han
, and
S. K.
Park
, “
Ink-jet-printed zinc–tin–oxide thin-film transistors and circuits with rapid thermal annealing process
,”
IEEE Electron Device Lett.
31
,
836
838
(
2010
).
20.
K. H.
Kim
,
Y.-H.
Kim
,
H. J.
Kim
,
J.-I.
Han
, and
S. K.
Park
, “
Fast and stable solution-processed transparent oxide thin-film transistor circuits
,”
IEEE Electron Device Lett.
32
,
524
526
(
2011
).
21.
C.-G.
Lee
,
T.
Joshi
,
K.
Divakar
, and
A.
Dodabalapur
, “
Circuit applications based on solution-processed zinc-tin oxide TFTs
,” in
69th Device Research Conference
(
IEEE
,
2011
), pp.
247
248
.
22.
R. D.
Chandra
,
M.
Rao
,
K.
Zhang
,
R. R.
Prabhakar
,
C.
Shi
,
J.
Zhang
,
S. G.
Mhaisalkar
, and
N.
Mathews
, “
Tuning electrical properties in amorphous zinc tin oxide thin films for solution processed electronics
,”
ACS Appl. Mater. Interfaces
6
,
773
777
(
2014
).
23.
B.
Kim
,
S.
Jang
,
M. L.
Geier
,
P. L.
Prabhumirashi
,
M. C.
Hersam
, and
A.
Dodabalapur
, “
Inkjet printed ambipolar transistors and inverters based on carbon nanotube/zinc tin oxide heterostructures
,”
Appl. Phys. Lett.
104
,
062101
(
2014
).
24.
B.
Kim
,
S.
Jang
,
M. L.
Geier
,
P. L.
Prabhumirashi
,
M. C.
Hersam
, and
A.
Dodabalapur
, “
High-speed, inkjet-printed carbon nanotube/zinc tin oxide hybrid complementary ring oscillators
,”
Nano Lett.
14
,
3683
3687
(
2014
).
25.
B.
Kim
,
M. L.
Geier
,
M. C.
Hersam
, and
A.
Dodabalapur
, “
Complementary D flip-flops based on inkjet printed single-walled carbon nanotubes and zinc tin oxide
,”
IEEE Electron Device Lett.
35
,
1245
1247
(
2014
)
26.
S.-P.
Tsai
,
C.-H.
Chang
,
C.-J.
Hsu
,
C.-C.
Hu
,
Y.-T.
Tsai
,
C.-H.
Chou
,
H.-H.
Lin
, and
C.-C.
Wu
, “
High-performance solution-processed ZnSnO TFTs with tunable threshold voltages
,”
ECS J. Solid State Sci. Technol.
4
,
P176
(
2015
).
27.
B.
Kim
,
J.
Park
,
M. L.
Geier
,
M. C.
Hersam
, and
A.
Dodabalapur
, “
Voltage-controlled ring oscillators based on inkjet printed carbon nanotubes and zinc tin oxide
,”
ACS Appl. Mater. Interfaces
7
,
12009
12014
(
2015
).
28.
S.
Han
and
S. Y.
Lee
, “
High performance of full swing logic inverter using all n-types amorphous ZnSnO and SiZnSnO thin film transistors
,”
Appl. Phys. Lett.
106
,
212104
(
2015
).
29.
A.
Liu
,
Z.
Guo
,
G.
Liu
,
C.
Zhu
,
H.
Zhu
,
B.
Shin
,
E.
Fortunato
,
R.
Martins
, and
F.
Shan
, “
Redox chloride elimination reaction: Facile solution route for indium-free, low-voltage, and high-performance transistors
,”
Adv. Electron. Mater.
3
,
1600513
(
2017
).
30.
C.
Fernandes
,
A.
Santa
,
Â.
Santos
,
P.
Bahubalindruni
,
J.
Deuermeier
,
R.
Martins
,
E.
Fortunato
, and
P.
Barquinha
, “
A sustainable approach to flexible electronics with zinc-tin oxide thin-film transistors
,”
Adv. Electron. Mater.
4
,
1800032
(
2018
).
31.
K.
Lee
,
Y.-H.
Kim
,
J.
Kim
, and
M. S.
Oh
, “
Transparent and flexible zinc tin oxide thin film transistors and inverters using low-pressure oxygen annealing process
,”
J. Korean Phys. Soc.
72
,
1073
1077
(
2018
).
32.
M. R.
Shijeesh
,
P. A.
Mohan
, and
M. K.
Jayaraj
, “
Complementary inverter circuits based on p-Cu2O and n-ZTO thin film transistors
,”
J. Electron. Mater.
49
,
537
543
(
2020
).
33.
Y.
Son
,
B.
Frost
,
Y.
Zhao
, and
R. L.
Peterson
, “
Monolithic integration of high-voltage thin-film electronics on low-voltage integrated circuits using a solution process
,”
Nat. Electron.
2
,
540
548
(
2019
).
34.
P.
Schlupp
,
S.
Vogt
,
H.
von Wenckstern
, and
M.
Grundmann
, “
Low voltage, high gain inverters based on amorphous zinc tin oxide on flexible substrates
,”
APL Mater.
8
,
061112
(
2020
).
35.
F. J.
Klüpfel
,
H.
von Wenckstern
, and
M.
Grundmann
, “
Low frequency noise of ZnO based metal-semiconductor field-effect transistors
,”
Appl. Phys. Lett.
106
,
033502
(
2015
).
36.
Y.
Yuan
,
J.
Yang
,
Z.
Hu
,
Y.
Li
,
L.
Du
,
Y.
Wang
,
L.
Zhou
,
Q.
Wang
,
A.
Song
, and
Q.
Xin
, “
Oxide-based complementary inverters with high gain and nanowatt power consumption
,”
IEEE Electron Device Lett.
39
,
1676
1679
(
2018
).

Supplementary Material