Toward CMOS like devices from two-dimensional channel materials

Complementary metal-oxide semiconductor (CMOS) devices have been the “workhorses” of the information technology (IT) industry over the last few decades. What makes the CMOS so successful is its complementary nature that n-type and p-type transistors can be made from silicon alike. An n-type field-effect transistor (FET) is characterized by operating in its on-state under positive drain voltages (V_ds) and gate voltages (V_gs) beyond its threshold voltage V_th-n. For V_gs < V_th-n, the device is in its off-state. The situation is mirrored in terms of voltage polarities for a p-type FET. Combining both types of FETs allows for power efficient circuits. For example, in an inverter that consists of an n-FET and a p-FET in series between ground and the supply voltage V_DD with a common input to the two gates, energy is only dissipated during the actual switching process that defines the output to be low or high.¹ Thus, mimicking this device behavior in novel channel materials is highly desirable.

Scaling silicon transistors over the last decade has, in particular, focused on making devices smaller while preserving the electrostatics through the use of thin silicon fins. However, silicon fins with ultrathin bodies (t_body) below ∼3 nm show a strong degradation of their mobility, which makes the smaller t_body more significant due to increased scattering at the Si/SiO₂ interfaces.^2,3 Ultimately, it is desirable to achieve body thicknesses in the subnanometer range without the introduction of excess scattering in the semiconductor.

After the groundbreaking work by Novoselov et al. in 2004⁴ on few-layer graphene, a semimetal, the scientific community started searching for other two-dimensional (2D) crystals as the ultimate implementation of an ultrathin body channel, with the declared goal to identify semiconducting materials for electronic applications. In 2011, Radisavljevic et al.⁵ reported on the first single layer MoS₂ transistors with a bandgap around 1.8 eV, followed by the demonstrations of FETs from black phosphorus (BP) in 2014.^6,7 While these devices in fact exhibit body thicknesses below 1 nm, their mobility was found to be in the range of tens to hundreds of cm²/V s,^6–11 making them attractive for ultimately scaled transistor applications as an extension of the above mentioned work on silicon fin FETs.

However, creating the desired n-type and p-type FETs from the same 2D channel material that exhibit the above described unipolar transport properties, i.e., only electrons (holes) are involved in current transport in the case of an n-FET (p-FET), has been proven difficult. This lies in part in the fact that substitutional doping to create an n/p/n or p/n/n profile along the channel, as in the case of silicon devices, is hard to achieve due to the small number of atoms involved in forming the device channel. As a result, most of the prototype devices on 2D channels are using metal electrodes (instead of doped semiconductors) as source and drain contacts. The resulting devices are so-called Schottky barrier (SB) field-effect transistors, where gating includes the source and drain contact regions. Ambipolar transport is typically observed since for positive gate voltages, electrons are involved in current transport, while for negative V_gs, hole transport occurs through the valence band.¹² 

In order to address this undesirable situation, it is important to understand some details about the operation of Schottky barrier field-effect transistors (SB-FETs). Figure 1 illustrates in simple terms how device characteristics depend on a number of critical parameters as the Schottky barrier heights Φ_SB-p, Φ_SB-n, and the geometric screening length λ. For all graphs, it was assumed that the conduction band edge E_c and valence band edge E_v respond 1:1 to the gate voltage V_gs in the off-state of the device. This implies, in particular, that an ideal inverse subthreshold slope (SS) of 60 mV/dec at room temperature is achievable when carrier injection (electrons or holes) into the channel is mediated by thermal emission (I_th) over band edge E_c or E_v.

Let us first focus on the green curve in Fig. 1 that plots the logarithmic current from source to drain as a function of gate voltage. The device is in its on-state when V_gs < V_th-p for hole transport and V_gs > V_th-n for electron transport. The corresponding image band structures for the voltages marked (1) and (3) are shown next to the device characteristics with E_Fs and E_Fd denoting the Fermi level in the metal source and drain, respectively. For voltages in between V_th-p and V_th-n, the device is in its off-state with three distinct slopes. Between V_th-p and the flat band voltage V_FB [marked (2) in Fig. 1], device characteristics are determined by thermal assisted tunneling I_tunnel through the Schottky barrier Φ_SB-p. This is the case since for an ultrathin body device, the characteristic tunneling distance is given by the so-called geometric screening length $λ=εbodyεox⋅tox⋅tbody$ that can become very small for small t_body values. Here, ε_body and ε_ox are the dielectric constants and t_body and t_ox the thicknesses of the channel material and the gate dielectric, respectively. The SS value in this region depends on the actual value of λ and varies between 60 mV/dec for λ = 0 (dark blue curve) and SS = ∞ for λ = ∞ (orange curve). The orange marked triangle on the left of Fig. 1 indicates the range of allowed inverse subthreshold slopes. Once flat band voltage is reached, only thermal emission is allowed (I_th) until a minimum current is reached at V_min. At this point, the thermally injected hole current through the valence band becomes equal to the thermally assisted electron tunneling current through Φ_SB-n into the conduction band. Finally, for V_min < V_gs < V_th-n, tunneling of electrons through the Schottky barrier Φ_SB-n dominates in the device, defining SS within the range marked by the orange triangle on the right of the graph, depending as before on the exact value of λ. Note that the entire discussion above focused on the device off-state, which is why scattering in the channel that dominates in the on-state was not part of our consideration.

The goal to achieve one type of carrier injection only is thus intimately related to the question of how to suppress Schottky barrier injection of holes for an n-FET and injection of electrons for a p-FET. As stated above, e.g., p-FET operation in CMOS requires negative gate and drain voltage polarities. Since the lateral electric field in the channel is positive from source to drain for negative drain voltages, this implies that electron injection between V_min < V_gs < V_th-n occurs from the drain side. For an n-FET, the undesirable hole injection also occurs from the drain, since operation is under positive drain voltages. This observation is key to designing devices that show unipolar characteristics, i.e., only electron currents for n-FETs and hole currents for p-FETs.

Many approaches have tried to suppress either electron or hole carrier transport to recover unipolar device characteristics. Often this is done at the expense of on-current performance by using thick oxides.¹³ For devices as shown in Fig. 1 with a Schottky barrier height that is substantially smaller (Φ_SB-p or Φ_SB-n < E_g/4) for one carrier type than the other, increasing λ by using thick oxides indeed improves the on/off current ratio I(V_th-n-or-p)/I(V_min)—compare, e.g., the green and the blue characteristics. However, only n-FETs or p-FETs can be realized in this way for a given choice of metal source/drain electrodes that define Φ_SB-p and Φ_SB-n. Moreover, the thicker gate oxide that translates into a larger screening length λ harms the on-state current, since injection from the source beyond threshold is occurring by tunneling through a thicker barrier. Another approach is to leave the drain side of the device ungated.^13,14 While this indeed suppresses drain injection, it results in highly nonlinear output characteristics I_d − V_ds for low drain voltages. Carriers injected from the source cannot leave the channel on the drain side due to the thick tunneling barrier that is a result of an absent gating of the drain. An improved version of this design incorporates an additional gate at the drain side, which is tied to the drain electrode so that the drain injection is suppressed at zero gate-to-drain voltage V_gd.¹⁵ However, in this feedback-gate design, the injection from the source is still affected by the additional gate at low V_ds, causing nonlinear output characteristics.

All of the above discussion is in general independent of the actual choice of channel material. The material properties become relevant only in that (i) the gate voltage range from V_th-p to V_th-n depends on the actual bandgap, (ii) the Schottky barrier heights depend on the combination of chosen metal source/drain electrodes and semiconducting channel, and (iii) the on-state current level itself, of course, depends on the achievable carrier concentration (determined by the density of states—DOS) and mobility of the chosen channel material.

Different from the above described approaches, a device layout was presented at the Device Research Conference (DRC) 2018¹⁶ that combines (a) linear output characteristics (I_d − V_ds) with (b) high on-state currents and (c) unipolar transfer characteristics. To achieve this goal, a device with an asymmetric double gate (ADG) on top and underneath a black phosphorus flake had been built using source/drain metals with a preferred line-up closer to the valence band edge (p-FET) or conduction band edge (n-FET)—for details, see the section titled “Implementation.” The key design feature is that while the respective oxides of the two gate stacks had both aggressively been scaled to an equivalent oxide thickness (EOT) of ∼3 nm, one of the two gates only partially covers the device channel and does not gate the drain region of the SB-FET. In addition, the choice of source/drain metal allows for the preferred injection of one carrier type. The impact of this type of gate layout in comparison with a fully double gated (DG) device structure is graphically illustrated in Fig. 2. Increasing the effective value of λ by removing one of the two gates entirely would change the device characteristics qualitatively from the set of green to the set of red curves as shown in Fig. 2(a). Different from Fig. 1, Fig. 2 also illustrates the drain voltage dependence. A negative drain voltage of V_ds = −0.1 V in comparison with a negative V_ds-value close to zero volts results in a shift of the electron branch (right side of device characteristics) toward negative gate voltages by exactly the amount of the applied drain voltage under the conditions assumed for this model. This is the case since the threshold voltage for electron injection from the drain has been altered by applying V_ds as is the flat band voltage on the drain side. Correspondingly, V_FB-d2(V_ds = −0.1 V) = V_FB-d1(V_ds ∼ −0 V) − 0.1 V and V_th-n-d2(V_ds = −0.1 V) = V_th-n-d1(V_ds ∼ −0 V) − 0.1 V. If, on the other hand, λ is kept small by using a double gate in the source region, while λ is made somewhat larger in the drain region by removing the impact of one of the two gates, on-currents of this particular p-FET are almost preserved, while the electron current from the drain is strongly suppressed. Figure 2(b) illustrates how the double gated (DG) p-FET (green) compares with the new asymmetric double gated (ADG) p-FET design presented here.¹⁷ Applying the same scheme to a device with low work function source/drain metal contacts consequently results in an n-FET. Figure 2(c) summarizes the outcome of this approach and illustrates how the same channel material displays the desired (almost) unipolar complementary (i.e., n-type and p-type) device characteristics. Figures 2(d) and 2(e) show the comparison of band diagrams of a p-type DG FET and a p-type ADG FET in the on-state and off-state, respectively. At the source side, the two types of FETs have the same λ and the on-currents remain almost unaffected. However, when a positive V_gs is applied to turn the devices off, a larger λ′ in the ADG FET suppresses the electron injection from the drain, resulting in a smaller off-state current, as shown in Fig. 2(b). The operation of an n-type ADG FET can be understood in a similar fashion.

Following the above presented idea, this section discusses in detail the experimental implementation of unipolar p-type and n-type SB-FETs. Among various 2D materials, black phosphorus (BP) was chosen as a channel material due to its high mobility and moderate bandgap.^6,18 The relatively small bandgap of BP enables both electron and hole injection in SB-FETs and facilitates the implementations of both p-type and n-type transistors, as neither of the Schottky barrier heights Φ_SB-p and Φ_SB-n is too large to block carrier injection. Therefore, BP transistors usually exhibit ambipolar characteristics, and complementary BP SB-FETs and circuits have been demonstrated in Ref. 19. However, although BP SB-FETs are “blessed” with easier access to both the p-type and n-type branches and thus allow for implementation of complementary transistors, they are also “cursed” with significant ambipolar behavior and thus low I_ON/I_OFF ratios. In the following, the problem posed by ambipolar branches is further illustrated using a more concrete example of a complementary BP double-gate (DG) FET. Next, the ADG-FET design is introduced to resolve this issue to achieve unipolar characteristics as well as high I_ON/I_OFF ratios.

Figure 3(a) shows the device structure of a BP DG-FET. A BP flake was transferred onto the bottom gate (BG), composed of 2 nm Ti as gate metal and 0.8 nm Al seeding layer plus 4 nm Al₂O₃ grown by atomic layer deposition (ALD) as gate dielectric. Then, 40 nm Ti or 1.5 nm/40 nm Cr/Au were evaporated and patterned as source/drain metal contacts for the n-FET and the p-FET, respectively. Another 0.8 nm Al seeding layer and 4 nm ALD-grown Al₂O₃ were deposited on top of BP as top-gate (TG) dielectric, followed by evaporation and patterning of 40 nm Ti as TG metal. The BG and TG are electrically connected to form a double-gate structure (the gate voltage V_gs is applied to both TG and BG). Figure 3(b) shows a representative false-colored SEM image of a BP DG-FET.

As described in the section titled “The Idea,” source/drain metal contacts with different work functions are employed to tune the Schottky barrier heights Φ_SB-p and Φ_SB-n in favor of one particular type of carrier injection from the source, i.e., a low work function metal like Ti favors electron injection in an n-FET, while a high work function metal such as Cr/Au favors hole injection in a p-FET. Figures 3(c) and 3(d) show the transfer characteristics of a p-type BP DG-FET and an n-type BP DG-FET, respectively. It is apparent from the high respective on-current levels that the metal work function engineering is effective and that complementary operation is achieved for the same gating scheme in BP FETs. In addition, thanks to the strong gate control from the double-gate structure, both the p-FET and the n-FET show steep SS values of 85 mV/dec and 80 mV/dec, respectively. Figures 3(e) and 3(f) show fits of transfer characteristics obtained for the p-type BP DG-FET and the n-type BP DG-FET employing the Schottky barrier model from Ref. 18 to extract the respective Schottky barrier heights. The extracted Schottky barrier heights are Φ_SB-p = 0.12 eV and Φ_SB-n = 0.35 eV for Cr/Au contacts, and Φ_SB-p = 0.37 eV and Φ_SB-n = 0.1 eV for Ti contacts, respectively. Figure 3(g) shows the Schottky barrier heights for electrons vs metal work function in various semiconductors, including MoS₂,^10,20 Si,²¹ and BP. Due to metal-induced gap states, the Schottky barrier heights of metal-semiconductor junctions do not follow the ideal Schottky-Mott rule, which predicts the Schottky barrier height for electrons to increase linearly with the metal work function exhibiting a slope of 1. Instead, an effect referred to as Fermi-level pinning arises,^10,21 causing the Schottky barrier heights to increase with metal work function with a slope much smaller than 1, as shown by the green line (Si, S = 0.27) and the red line (MoS₂, S = 0.1) in Fig. 3(g). A recent discovery shows that by transferring metal contacts onto MoS₂ instead of direct metal evaporation, an excellent metal-semiconductor interface quality can be achieved and the gap states can be eliminated, approaching the Schottky-Mott limit (S = 1),¹⁰ as shown by the black line (S = 0.96) in Fig. 3(g). Figure 3(g) also shows the data extracted from Figs. 3(e) and 3(f) assuming a Ti work function value of WF = 4.33 eV and a Cr/Au value of WF = 5.1 eV. Note that we assumed here that the 1.5 nm thin Cr adhesion layer does not change the work function of the Cr/Au stack to be different from Au. From our data, two important conclusions can be drawn (1) Fermi level pinning is indeed present in our metal-BP junctions, as apparent from the blue line (S = 0.32) in Fig. 3(g), and (2) despite the Fermi level pinning, work function engineering of the metal contacts is sufficiently effective to enable low barriers for electron injection (Ti, Φ_SB-n = 0.1 eV) and hole injection (Cr/Au, Φ_SB-p = 0.12 eV) in n-type and p-type BP FETs, respectively.

While we have in this way achieved complementary BP FETs using contact work function engineering, the still existing ambipolar branches caused by drain injection are severe for both FETs and result in low I_ON/I_OFF ratio, especially at high drain biases [compare Fig. 2(a)]. Transistors with high I_ON/I_OFF ratios are essential to achieve low static power consumption and a full output swing for CMOS circuits, which requires modification of the above device layout. The solution lies, as discussed in the section titled “Idea,” in designing an asymmetric double gate (ADG) FET structure.

We have demonstrated complementary BP ADG-FETs with nearly unipolar characteristics and high I_ON/I_OFF ratios during the Device Research Conference (DRC) in 2018.¹⁶  Figure 4(a) presents the device structure of a BP ADG-FET, in comparison with a DG-FET. In the ADG-FET, the BG is placed overlapping with only the source contact and part of the BP channel. The drain side of the FET remains ungated by the bottom gate, while the TG covers the entire channel. The process flow of fabricating an ADG-FET is similar to that of a DG-FET, with the only difference being that the drain electrode is placed outside of the BG region. Figure 4(b) shows a false-colored SEM image of a BP ADG-FET. By introducing the underlap of BG with respect to the drain in the ADG-FET, the impact of BG is eliminated on the drain side of the device, and thus the effective value of λ is made larger for the drain injection than for the source injection. As discussed in section titled “The Idea” and shown in Fig. 2(b), this approach is expected to suppress the drain injection while preserving the source injection, resulting in higher I_ON/I_OFF ratios and almost unipolar characteristics.

The experimental outcome of the ADG-FET approach is shown by the transfer characteristics of a p-type and an n-type BP ADG-FET in Fig. 4(c). The ambipolar branches are substantially suppressed as expected from our analysis, and almost unipolar p-type and n-type FETs are achieved, with significantly improved I_ON/I_OFF ratios if compared to the BP DG-FETs. Moreover, the p-type and n-type BP ADG-FETs exhibit steep SS values of 78 mV/dec and 88 mV/dec, respectively, underlining the strong gate control of the double-gate structure. Figure 4(d) shows the output characteristics of the p-type and n-type BP ADG-FETs. Both types of ADG-FETs show rather linear output characteristics at low V_ds values, as the drain side of the device is still gated by the TG, which is an improvement over the highly nonlinear output characteristics of the device structure in Refs. 13 and 14, where the drain side is ungated. Moreover, both types of FETs exhibit high ON-current values of ∼100 µA/μm at |V_ds| = 1.2 V, owing to the proper engineering of the source/drain contact metal work functions, which impact the Schottky barrier heights Φ_SB-p and Φ_SB-n for hole and electron injections as described above. Also note that current saturation is observed for both types of ADG-FETs in the output characteristics as expected for properly designed scaled devices with both gate and drain voltages in the ∼1 V range.

Based on the complementary BP ADG-FETs discussed in section titled “Implementation,” we next demonstrate a simple CMOS circuit—an inverter.¹⁶  Figures 5(a) and 5(b) display the schematic and a false-colored SEM image of an inverter built from a p-type BP ADG-FET and an n-type BP ADG-FET in which the p-FET and the n-FET are fabricated on the same BP flake.

As evident from the voltage transfer characteristics [Fig. 5(c)] and gain [Fig. 5(d)] of the inverter at different supply voltages V_DD, excellent performance specs have been achieved, thanks to the high performance of the individual BP FETs as shown in Figs. 4(c) and 4(d) in the section titled “Implementation.” A number of aspects are worth noting: First, the inverter is fully operational even at V_DD values as low as 0.2 V, since the individual p-FET and n-FET have steep subthreshold slopes and the input voltage range required to turn on and off the devices is small. Second, a full output swing from V_DD to 0 is obtained, since unipolar characteristics were successfully achieved by suppressing the drain injection by employing the above described ADG-FETs. The key is that both the n-FET and the p-FET can be turned off effectively when the input is 0 or V_DD. Finally, the inverter exhibits a very high gain of 21.1 at V_DD = 0.6 V, and even at the lowest supply voltage of V_DD = 0.2 V, a peak gain of 10.2 is still retained. This high gain of the inverter is a result of the relatively high output resistances of the BP ADG-FETs in their respective saturation regions,¹ as depicted in Fig. 4(d).

It is worth noting that since the transfer characteristics of the p-FET and the n-FET are symmetrical with respect to a nonzero gate voltage, i.e., V_gs = −0.2 V, as shown in Fig. 4(c), the input voltage has been shifted in Figs. 5(c) and 5(d) by 0.2 V, i.e., V_in,shift = V_in + 0.2 V to compensate for the mismatch of threshold voltages of the p-FET and the n-FET. This problem can be resolved by various threshold voltage tuning schemes to shift the voltage back to zero, such as gate metal work function tuning and interface dipole engineering.²² 

In this article, we have reviewed some recent efforts of demonstrating CMOSlike devices using 2D materials. Starting from a review of the operation principle of Schottky barrier field-effect transistors, ambipolar current injection in transistors made from 2D channels has been carefully discussed. A recently demonstrated device structure, i.e., an ADG-FET has been presented to suppress ambipolar device characteristics effectively and has been implemented in n-type and p-type black phosphorus FETs and a CMOS inverter circuit. Our work may provide guidance to the design of future generations of 2D materials’ based devices and logic circuits.