Two-Dimensional (2D) materials have been a “beyond CMOS” focus for more than a decade now, and we are on the verge of a variety of breakthroughs in the science to enable their incorporation into next generation electronics. This perspective discusses some of the challenges that must be overcome, as well as various opportunities that await us in the world of 2D for beyond CMOS.
Type “graphene” in any peer review article search engine and you will get >30 000 articles just in 2017 that include a range of applications such as wearable sensors,1 antimicrobial films,2 immunology,3 and electronics,4 to name a few. The field of “2D materials” is continuing to grow at an exponential rate, with new materials being theoretically predicted and experimentally realized on nearly a daily basis. This mind boggling number of new material systems can quickly lead to an inability to keep up with what our colleagues have accomplished, and therefore we often see new review articles being published on a monthly, or even weekly, basis. This is because the properties and shear breadth of 2D layer combinations, even just within the chalcogenide family [Fig. 1(a)], have invigorated the imagination of many.
CONVENTIONAL THINKING IN UNCONVENTIONAL MATERIALS DOES NOT WORK
From the perspective of next generation electronic technologies, the carrier mobility and bandgap are two figures of merit that often attract attention for comparing to traditional semiconductors. Figure 1(b) provides a broad comparison of the bandgap and mobility of a variety of mechanically exfoliated 2D materials that are of most interest for electronic applications.5–26 Of these, black phosphorous (phosphorene) is often been touted as the ideal material,14 but the high mobility is only found in thick layers.27 To take advantage of the “2D thinness” in scaling, and therefore achieve superior electrostatics, one must scale to monolayer, which results in carrier mobility values less than that found in the 2D chalcogenides. On the other hand, even the most highly scaled 2D chalcogenide-based field effect transistors, with a 1-nm physical gate length, do not beat the Boltzmann limit.28 Thus, if we think of utilizing these materials in the typical CMOS architectures and silicon-mindset, they will likely not have a meaningful impact on beyond CMOS. Fortunately, parallel to “beyond CMOS” is a push for 2D/3D hybrids and 2D heterostructures, where we are able to take advantage of the vertical transport through atomically thin semiconducting layers. Furthermore, there are opportunities to combine 2D materials with traditional 3D semiconductors (2D/3D hybrids) to realize extreme performance in beyond CMOS devices.29 Looking ahead, we must address a variety of challenges in 2D material synthesis, property control, and device architectures to realize the variety of opportunities that come with these novel materials. In the following paragraphs, I will discuss some of the challenges and opportunities of 2D to make an impact on “beyond CMOS and traditional CMOS architectures.”
THERE ARE CHALLENGES
Two-dimensional materials have the potential to impact everything from water filters to high end electronics, but there are many challenges to realizing their full potential.
Defects control many things (nucleation, growth, hetero-integration, and electronic transport), especially when dealing with materials that are on the same order of thickness as the defect itself.30 Defects come in all shapes and sizes, from point defects like vacancies and impurities to line defects such as grain boundaries. Regardless of the synthesis technique, all materials contain structural defects that impact the physico-chemical properties of the layers and how the layers can be utilized in a given application. The most common defect among the semiconducting transition metal dichalcogenides is the chalcogen deficiency but can also include impurities due to the growth environment. Only until recently have defects become a focus of the synthesis process, and even simple improvements in precursor and chamber purity lead to orders-of-magnitude improvements in 2D layer purity and defect density. From a transport perspective, some argue that grain boundaries do not impact transport properties,31 while others use the impact in transport properties for creating novel devices based on 2D.32 Defects and impurities have impacted transport in every known semiconductor to date and do impact 2D transport considering the overwhelming evidence that vacancies, impurities, and grain boundaries [Fig. 2(a)] strongly influence the band structure of the layers.30 Therefore, understanding and controlling the structure, chemistry, and density of defects will continue to be a grand challenge in 2D layers.
To date, the majority of 2D layer growth beyond graphene has been on amorphous silicon dioxide (SiO2). However, the utilization of crystalline sapphire substrates to create aligned domains has shown great promise for enabling “2D epitaxy.”33,34 This type of epitaxy could be called van der Waals epitaxy, but the interaction between the substrate and 2D layer is found to exhibit very strong coupling [Fig. 2(b)] that often requires the transfer of the 2D layer from the parent substrate to a new substrate to achieve the weak coupling often found in exfoliated layers.35 Furthermore, the substrate/2D interaction can dominate doping efficacy36 and transport properties,37 as well as dramatically affect optical properties.34 In fact, without engineering of the 2D/substrate interface, it may be difficult to achieve monolayer epitaxial 2D layers with high electron mobility simply because the substrate induces too much scattering in the layer, suggesting that few layer epitaxial films may be preferred for improved electronic performance if one is to eliminate the transfer processes so often used in the current literature.38
The oxidation of metallic and semiconducting 2D layers is a true technological problem. In some cases, exposure to ambient can completely oxidize layers in a few hours.39 There are a variety of techniques to avoid oxidation, including moving all experimentation into oxygen-free gloveboxes or dielectric capping layers.40 While these often achieve improved stability over days or months, the general tendency of the semiconducting and metallic 2D layers is to transform to their most stable form: an oxide.41 Therefore, continuing to develop robust routes for ensuring 2D layer stability is a critical need for large-scale applications.
THERE ARE OPPORTUNITIES
Recent years have seen a variety of demonstrations of 2D heterostructures for low-power devices, with many being predicted to improve performance beyond current CMOS technologies,42–44 but the experimental realization of a sub-60 mV device over many decades simply with heterostructures is still elusive. This suggests that many of the extrinsic factors in the device design (e.g., contacts and gate dielectrics) limit the performance. However, various routes to achieving sub-60 mV/dec performance by combining 2D with 3D materials have yielded promising results, including integrating 2D layers with ferroelectric polymers,45 adaptation of the piezoelectronic transistors,46,47 and utilization of negative capacitance (NC) materials.48 In the case of the NC materials, a MoS2 FET is combined with a hafnium zirconium oxide (HZO) ferroelectric that yields sub-60 mV/dec switching over multiple decades of current up to the micro-ampere range. Beyond ferroelectric/2D hybrids, there is an ever increasing interest in combining 2D layers with 3D semiconductors to enhance the performance. Perhaps the most promising example to date of the 2D/3D semiconductor hybrid is the MoS2/germanium tunnel transistor.29 The key to its subthermionic transport is band-to-band tunneling (BTBT) that occurs due to the Ge/MoS2 band alignment that enables a small tunneling barrier height necessary for BTBT. While it does enable sub-60 mV/dec over four decades, it suffers from much lower on-currents compared to the 2D NC-FET,46 which could ultimately be improved through continued optimization. Regardless, several paths are now forming that indicates 2D/3D hybrids, where both components provide a unique function beyond traditional semiconductor physics, could be a viable option for next generation, subthermionic devices.
Back-End of the Line (BEOL)
The back-end of the line is simply all device and circuit processing that happens after the transistor is formed. While this is not necessarily “beyond-CMOS,” developing means to enhance functionality in the BEOL architecture that could dramatically improve the performance/energy ratio. However, there are severe thermal processing limitations that limit growth temperatures to below 500 °C. This typically leads to the formation of nanocrystalline 2D layers with electronic properties not necessarily suitable for transistor applications.49 However, just because the layers are nanocrystalline, it does not mean that they are not useful for CMOS and beyond-CMOS applications. Recent reports on the use of 2D layers where electronic properties are secondary are quite promising.32,50,51 Atomically thin 2D materials such as graphene and h-BN with engineered nano-pores can act as functional membranes in resistive memory elements, wherein the nano-pores enable controlled ionic transport across the atomically thin material while the rest of the material remains impermeable.51 This ultimately can lead to significant improvements in the reliability and performance of the devices and does not rely on the electronic performance of the layer.
Phase change materials
Applications such as energy storage,52 field effect transistors,21 and non-volatile memory53 require improvements to achieve ultrafast electronic switching, and one opportunity lies in the utilization of metal to insulator (or semiconductor) transition (MIT) materials. The MIT phenomenon can occur in a variety of ways; however, one such process is through a correlated electron effect54–56 that occurs on extremely fast scales, much faster than traditional semiconductor device physics is able to achieve. Interestingly, 2D materials such as the transition metal dichalcogenides are not only atomically thin, but some also exhibit the desired metal to insulator transitions that could lead to ultra-fast transistors.57–59 Many semiconducting transition metal dichalcogenides are stable in the lowest energy phase (2H phase); however, it has been shown with MoS2 through lithium intercalation that the 2H can be converted to the metallic 1T′ phase upon post-synthesis processing.60 While the 1T′ phase transitions can be induced in MoS2, it is not amenable to 2H1T′ cycling. This is because there is a large energy difference between these phases, calculated to be as high as 0.87 eV,61 making it difficult to easily transition back and forth between the two phases. On the other hand, TMDs such as MoTe2 could potentially exhibit a reversible phase change from the 1T′ (semi-metallic) to 2H (semiconductor, with 1 eV bandgap) structure because of the small energy difference between the 2 phases—only 31 meV.62 In fact, publications are now beginning to appear on this topic,63 suggesting that phase transitions in TMDs could propel 2D materials beyond CMOS applications.
Two-dimensional materials are still quite young, with many new phenomena being discovered on nearly a continuous basis. The field has gone from studying one material (graphene) to understanding that there are potentially thousands to be explored, with nearly an infinite number of combinations for heterostructures. There are plenty of challenges, but there are also an unimaginable number of potential opportunities, most of which will be outside of the “beyond-CMOS” application space. If 2D materials are to make an impact, then they cannot simply provide an incremental improvement in current technologies. Instead, they must address, as Herbert Kroemer stated in his 2000 Nobel Lecture,64 the “Lemma of New Technology”: The principal applications of any sufficiently new and innovative technology always have been—and will continue to be—applications created by that technology.
J.A.R. acknowledges support from the National Science Foundation, Northrop Grumman, Intel, Corning, and the Center for the Low Energy Systems Technology.