Perspective: Optical measurement of feature dimensions and shapes by scatterometry

The process of patterning the next generation of structures that become transistors, capacitors, or interconnects continues to challenge the semiconductor industry. A critical aspect of patterning is producing structures with identical feature shape and dimensions across the patterned area and across the wafer. Historically, ellipsometry (single wavelength and spectroscopic) has been a critical part of the process control ecosystem for decades as the workhorse for thin film metrology.¹ Critical dimension metrology had strictly been performed by image-based microscopy until critical dimensions dropped below the resolution limit, necessitating the move to critical dimension scanning electron microscopy (CDSEM). The move to scatterometry for critical dimension metrology started with the need to measure structure dimensions that are invisible to top-down approaches, such as re-entrant features and gratings with profiles larger than 90°. The transition to 3d architectures for DRAM, flash memory, and then logic in the middle to late 2010s really solidified the place of scatterometry (and ellipsometry by extension) in the process control loop. The term scatterometry refers to the use of optical scattering from a period array to determine feature dimensions and shape. Here we discuss scatterometry equipment that uses spectroscopic ellipsometry to measure specular scattering from a periodic array and then compares simulated response to experimental data until the optical model of the shape and dimension matches the data.² 

This paper will provide an overview of scatterometry that includes a description of ellipsometry, optical modeling, and application of scatterometry.¹ Optical modeling for ellipsometry and scatterometry requires knowledge of the complex refractive index of the nanoscale materials contained in the structure. The complex refractive index (dielectric function) of the materials needs to be known over the wavelength range of the measurement system and be appropriate for the nanoscale dimension of the material. There are now a number of examples of the impact of the film thickness on the dielectric function for materials that are used in integrated circuits. Examples include metal films,³ semiconductor layers such as silicon⁴ or germanium, and dielectric films.⁵ Furthermore, the optical properties of materials such as the gate dielectric layer are a function of process conditions which alter the crystal phase and grain size. In that light, Sec. II discusses the complex refractive index of nanoscale semiconductor materials.

The information obtained from an ellipsometric measurement depends on the optical path inside the ellipsometer.² In this paper, Mueller matrix spectroscopic ellipsometry (MMSE) is described. Ellipsometry is based on the polarized reflection of light from a sample with light polarized parallel to the plane of incidence (P) scattering differently than light polarized perpendicular to the plane of incidence (S). Mueller matrix systems provide both the traditional wavelength dependent psi and del values as well as a 16 element matrix.^1,2 The MMSE characterizes the amount of light scattered from P to S and vice versa. The MMSE will be described in Sec. III.

Scatterometry measurements are simulated using a Rigorous Coupled Wave Analysis (RCWA)⁷ method that provides an approximate solution to Maxwell’s equations. The optical model of the structure and the RCWA method are described in Sec. IV. The application of MMSE scatterometry to future gate-all-around transistor structures that are beyond traditional CMOS is presented in Sec. V. Section VI will discuss the use of plasmonically active metal structures to improve the sensitivity of scatterometry to dimensional changes in metal interconnect lines.

The complex refractive index of some materials is experimentally determined and then used as reference data to determine the film thickness or in scatterometry simulations.¹ For other materials, the optical properties are fit to a representative functional form such as the Cauchy, Lorentz, Tauc–Lorentz (T-L), Cody–Lorentz (C-L), and other functional forms. Traditionally, the Cauchy model is used for materials that do not absorb light (k = 0). For example, many dielectric films do not absorb light at near IR, visible, and UV wavelengths. The same is true for semiconductors in restricted wavelength ranges that are below the band gap in energy but above the energy range in the IR where phonon absorption occurs. Although the simple Cauchy model is not K-K consistent, most optical modeling software includes an altered optical model that is K-K consistent. The fitting process usually requires knowledge of the thin film thickness.

Nanoscale dimensions have a significant impact on optical properties of thin semiconductor films and structures. The source of the effects depends on whether or not the samples are single crystal or polycrystalline. The thickness dependent optical properties of nickel metal films (see Fig. 3) were shown to be correlated to the change in Drude free electron relaxation time [see Eq. (3)].⁶ This change in relaxation time was traced to the change in both grain boundary reflection coefficient and grain size.⁶ 

The optical path is schematically shown in Fig. 6. The use of a rotating compensator before and after the sample enables the measurement of the full 16 element Mueller matrix. The operating wavelength range for the MMSE in the J. A. Woollam RC2 laboratory system used in the studies discussed here is 200 nm–1500 nm. The light from the RC2 system can be focused into an elliptical spot that is at best 200 μm in length at the operating angle of incidence. Fully automated scatterometry systems based on MMSE can focus light into areas less than 40 μm × 40 μm.

In order to apply the rigorous coupled wave approximation for solving Maxwell’s equations, a periodic grating is measured.

Now that Mueller matrix ellipsometry and RCWA have been thoroughly introduced, we can go forward with presenting relevant “Beyond CMOS” examples incorporating MM scatterometry and RCWA. In this paper, we used the analysis package NanoDiffract™ from Nanometrics, Inc. NanoDiffract provides an entire ecosystem for scatterometry analysis using RCWA-based analysis algorithms. Within NanoDiffract, the optical model structures are built and 3D models are visualized before scatterometry simulations are performed. This software is used to determine structure and material parameterization and simulate measurement uncertainty, sensitivity, and correlation of the “free” parameters using the built-in Uncertainty and Sensitivity Analysis (US&A) capability. Section V A will briefly describe how the US&A capability works, and then we will look at specific examples of key process steps for a horizontal GAA device and a vertical GAA device. In Sec. VI, we describe a back end of the line (BEOL) interconnect test structure that utilizes a plasmonic resonance sensitivity enhancement.

The use of full Mueller matrix data for scatterometry falls into three categories: the case where MM data enable the measurement, the case where MM data enhance measurement by providing extra information to improve parameter decorrelation, and the case where MM data are nice to have. For the first case, full MM data are necessary for the measurement of structural anisotropy, like tilt or overlay shift.¹¹ For the second case, MM data are critical for extremely complex structures, like FinFET solid state doping (SSD) etch, because they add extra unique spectral information that aids in parameter decorrelation. The final case is that where MM data are nice to have, but it is not completely necessary. This can happen, but using a dual rotating compensator ellipsometer enables the collection of the full MM without the need to move to different analyzer angles. Therefore, it takes no extra time to collect the full MM, so the extra MM information is essentially free and used.

As we continue to scale logic devices to keep up with Moore’s Law, we are quickly approaching the limit of FinFET devices. The industry consensus as of now has FinFET devices scaling down to the 7 nm node (fully scaled node and 5 nm foundry node). Below the 7 nm node, the contacted gate poly pitch (CPP) drops below 40 nm and the electrostatic control of fins is not possible, necessitating the need to move to a GAA device.¹³ Horizontal GAA is currently in the roadmap for Samsung at what they are calling their “4 nm node.” The process flow is very similar to that of a FinFET device, with a few key modifications to create the stacked nanowires. Figure 9 shows the process flow for vertically stacked horizontal nanosheet GAA transistors.

The most critical, and likely most challenging, process step is the inner spacer etch back. Figure 10 shows a schematic view of the step. This step is critical for two reasons: first, it protects the epi S/D (S/D refers to the epitaxially deposited transistor source and drain) region during the nanowire release step¹⁴ and, second, it suppresses parasitic capacitance between the S/D and gate.¹⁵ Figure 10 shows a schematic view of the step.

Control of the transistor gate is referred to as critical dimension (CD) control. Figure 10 shows the inner spacer etch back model used for this simulation. The term spacer refers to a dielectric that is deposited on both sides of the transistor gate. This simulation compares using MMSE vs conventional spectroscopic ellipsometry (SE). The measurement azimuth is 45° relative to the fin, and the wavelength range used is 200-1000 nm. Design rules used for the simulation are roughly equal to foundry-scaled 7 nm node for fin and gate pitches.¹⁶ Figure 11 shows the raw sensitivity curves for low-K (low dielectric constant material with a K value less than silicon dioxide) spacer, SiGe CD, Si offset CD, and inner spacer CD.

Figure 12 illustrates the US&A comparison between MMSE and conventional SE. Using MMSE reduces the “Degree of Correlation” for all parameters and directly affects the parameter uncertainty (all parameters show a 2-7× improvement in uncertainty utilizing MMSE over SE).

Beyond the horizontal GAA device, there are a few different directions to go into continue logic scaling. IMEC, among others, has proposed complimentary stacked GAA, vertical GAA, TFET, and 2D FET’s (utilizing graphene or dichalcogenides).¹⁴ In this example, we will take a closer look at the vertical GAA device. In theory, a vertical GAA device with a Si nanowire has all of the electrostatic benefits of a horizontal GAA device, but its gate length is not restricted by its “footprint” on the wafer. This allows for relaxing of gate length dimensions (and even the nanowire diameter) and still allowing for lateral device scaling by up to 20% for the same node.^17,18

One of the key process differences between a vertical GAA device and a horizontal GAA device (or even a FinFET) is that the gate length and contact alignments switch from being defined lithographically to being defined by deposition and etch back processes.¹⁷ The process control of these new key steps is well suited for scatterometry and MMSE, in particular.

The process flow used for this example follows the “channel-first” flow proposed by IMEC.¹⁸ Channel doping is first done to define the source, gate, and drain regions for N and P type transistors followed by nanowire patterning and etch. After the nanowires are etched, there are 2 critical deposition-etch back steps that define the drain, gate length, and contact alignments. For this example, we will focus on the dummy (sacrificial structure that is later removed by etching) a-Si etch back step. This step is critical because it defines the gate length and needs to be precisely defined in the vertical direction to the nanowire junction doping profile (measurement needs to be done with other type of metrology system).

The simulated structure has a pitch of 40 nm, nanowire bottom, and top CD of 15 nm, nanowire height of 120 nm, SiO₂ hardmask height of 10 nm, silicon nitride thickness of 30 nm (aligned to drain), and dummy a-Si thickness of 60 nm after etch back (model image can be seen in Fig. 13). The measurement azimuth is 22.5° relative to the nanowire lattice (to maximize symmetry breaking between the structure and plane of incidence), and the wavelength range used is 200-1000 nm.

Looking at the simulated MMSE spectra between the SiN etch back step (the step before a-Si deposition) and dummy a-Si etch back, it is clear that the off-diagonal response is highly attenuated for the latter step due to the high absorption of a-Si acting as a “substrate” and lowering the interaction volume compared to the prior step (Fig. 14). This means that using MMSE over conventional SE measurements will not be beneficial from the standpoint of lowering parameter correlation. Nevertheless, using ellipsometry for this step is still a viable measurement as means of controlling the a-Si thickness, as US&A predicts 1 sigma uncertainty to be <0.009 nm.

Scatterometry sensitivity to linewidth changes needs to improve as copper interconnect metal linewidths decrease with scaling. The term sensitivity has been used to describe the spectral change in response to the structural parameter change. Here, the sensitivity increase is obtained through the wavelength shift for a plasmon-induced spectral feature with change in linewidth, and we refer to that sensitivity increase in this section.^19,20 This issue is illustrated in Fig. 15 using the simulated change in the M₁₂ Mueller matrix element with the copper linewidth. Although the linewidths are varied from 18 nm to 30 nm in 2 nm steps, M₁₂ does not show great sensitivity to linewidth variation even though the linewidths are at the current state of the art. In order to improve sensitivity to linewidth changes, O’Mullane, et al. employed a cross-grating plasmonic structure that changed reflection in a manner that increased sensitivity to the linewidth of copper interconnect lines.^19–21 

The cross-grating test structure uses a grating that has the dimensions and pitch (periodicity) that result in surface plasmon polaritons when the light of appropriate wavelength from the ellipsometer scatters from the grating at an operational angle of incidence of 65°.^19–21 The linewidth features in the surface plasmonic grating are larger than the state-of-the-art copper interconnect linewidths. For example, a copper grating with 250 nm wide lines and a pitch of 500 nm will launch surface plasmons at a wavelength of 950 nm for light incident at 65°. The copper lines in the cross-grating have linewidths representative of the state of the art in copper interconnects. One can vary the linewidth and pitch of the wider grating and the pitch of the narrower grating to obtain the maximum sensitivity to linewidth variation over the wavelength range of the ellipsometer especially when the wavelength range extends in the IR to 1500 nm.^19–21 Although the original concept was based on surface plasmon polaritons, O’Mullane et al. found that a copper plate below the cross-grating resulted in localized plasmons between the top grating and copper plate that enhanced sensitivity to the copper linewidth.^19,20 These simulations were based on both RCWA and the finite element method. The cross-grating structure is shown in Fig. 16, and plots of Mueller matrix elements show a linewidth dependent feature in Fig. 17. Simulations also showed that the cross-gratings did not lose sensitivity when corner rounding was present.²⁰ Using a cross-grating test structure, a sensitivity of 0.1 nm linewidth is possible.

This paper describes the application of Mueller matrix spectroscopic ellipsometry and RCWA simulations to scatterometry for the measurement of feature shape and dimensions of advanced semiconductor structures. The sensitivity of scatterometry to gate-all-around transistor structures for future process control applications is demonstrated for the key process step of inner spacer etch back. The extension of scatterometry to process control for next generation copper interconnects is shown by the application of a plasmonically active test structure.

ACD gratefully acknowledges the many contributions of Vimal Kamineni, Raja Muthinti, Dhairya Dixit, Sam O’Mullane, and post-doctoral fellow Sonal Dey to the work shown in this publication.