After more than five decades, Moore’s law1 scaling has finally brought silicon logic and memory technologies to the cusp of single digit nanometer devices. As has been the case throughout the long history of Moore’s law,2 significant debate abounds concerning how much longer such scaling can continue.3 Given that Moore’s law has driven a 400 × 109 dollar4 industry that has continuously brought new and revolutionary products to the world, the timing of the ultimate demise for this maxim has significant economic and societal implications.
The arguments for and against the eventual end of Moore’s law revolve around economics and various technical challenges associated with the scaling of complementary-metal-oxide-semiconductor (CMOS) devices,5–7 optical (e.g., EUV) lithography,8–10 metal interconnect resistance-capacitance delays,11 and thermal/heat management12 to name a few. Unfortunately, the recent dissolution of the International Technology Roadmap for Semiconductors13 has left a somewhat murky picture to those outside and within the industry for how this epic journey may continue. However, if the past is any prediction of the future, new developments in materials, metrology, and computational modeling will play a key role in extending the CMOS technology to whatever its ultimate limits may turn out to be and in enabling whatever futuristic devices are determined capable of extending things beyond CMOS.14 Metrology and computational modeling in turn are likely to play a substantial role in the discovery of such new materials and enabling new materials process technologies as well.
While the end-of-the-roadmap for Moore’s law-related scaling and other technologies is not clear, we seek in this special topic of APL Materials to establish that, thanks to numerous exciting developments in new devices, materials, materials-related processes, metrology, and computation modeling, there is still plenty of room to go. This special issue specifically presents new advances in 2D materials and devices that may allow the CMOS technology to be extended further, as well as resistive random access memory (RRAM) devices that allow beyond-CMOS scaling. Several papers also demonstrate new materials and processes to address the challenges of nanoscale patterning and the thermal, mechanical, and electrical reliability of nanoscale devices. Finally, the role that optical metrology and computational modeling can play in advancing device-material-process research is illustrated throughout many of the articles in this special issue. In short, we hope this special issue helps filling part of the void left by the dissolving of the ITRS and provides a small beacon for the future of semiconductor/nanoelectric devices.