A high density two-dimensional electron gas in an oxide heterostructure on Si (001)

Thin film crystalline oxides present a rich and diverse field of study, stimulating research in both fundamental condensed matter physics and the development of applications based on their material properties. Advancements in thin film growth and characterization have enabled artificial oxide heterostructures to be engineered with atomic-scale precision. These advancements have led to the discovery of interesting physical phenomena that arise at oxide interfaces, including switchable magnetism,¹ superconductivity,² and metallic conduction.³ Much of this rich behavior has been observed in 2-dimensional electron gases (2DEGs) that form at oxide interfaces in which a discontinuity in polarization exists. The RTiO₃/SrTiO₃ (RTO/STO) system is a quintessential example of such a polar interface, where R denotes a rare earth element such as La,⁴ Gd,⁵ Sm,⁶ or Nd.⁷ Along the {100} directions, RTiO₃ has alternating planes of RO and TiO₂ that are nominally +1 and −1 in ionic charge, respectively. In contrast, the alternating planes of SrO and TiO₂ along the {100} directions of SrTiO₃ are charge neutral. The formation of a 2DEG compensates or screens the discontinuity in polarization at the interface. In theory, 2DEGs that have a charge density of ∼3.3 × 10¹⁴ charges/cm² (0.5 electrons per unit cell (u.c.)) fully compensate or screen the discontinuity in polarization. The densities of such 2DEGs are an order of magnitude higher than those of 2DEGs found in state-of-the-art AlGaN/GaN heterostructures⁸ and have been experimentally confirmed at interfaces between GdTiO₃/STO.⁹ The high carrier densities offered by oxide 2DEGs could lead to the development of technologies for infrared and optical plasmonics,^10,11 “charge gain” devices,^12,13 and highly scaled devices in general.^14–16 

In order to explore the potential application of oxide 2DEGs in optical and microelectronic devices, the integration of oxide 2DEGs on Si is required. Integration of crystalline oxides on a Si platform circumvents the problem of growing larger variations of ceramic substrates typically used to grow oxide heterostructures. Furthermore, the integration of oxide 2DEGs on silicon offers significant advantages for heat dissipation for potential power applications, since the thermal conductivity of silicon is an order of magnitude higher than that of typical oxide substrates. Here, we utilize oxide molecular beam epitaxy (MBE) to grow heterostructures comprised of LaTiO₃ (LTO) and STO on Si (001). Structural characterization indicates the LTO/STO heterostructures are single crystalline and epitaxial to the Si substrate. The sheet resistances and carrier densities of the heterostructures are strongly dependent on the number of LTO/STO interfaces, consistent with the presence of high density 2DEGs at the interfaces between LTO and STO.

LTO/STO heterostructures are grown using reactive oxide MBE in a custom chamber operating at a base pressure of 1 × 10⁻¹⁰ Torr. The structures are epitaxially grown on undoped (>3000 Ω cm), (001) oriented silicon wafers that are grown using the float-zone technique (Virginia Semiconductor, Inc.). Prior to film deposition, the wafers are cleaned in piranha solution (3:1 H₂SO₄:H₂O₂, 130 °C), etched in dilute hydrofluoric acid (3:70 with water), and subsequently oxidized for 30 s under an ultraviolet lamp to form a layer of SiO_x. The resulting protective layer of SiO_x is desorbed from the surface by heating the substrate to 900 °C (thermocouple temperature) in ultra-high vacuum (UHV) until a 2 × 1 reconstruction is observed in the reflection high energy electron diffraction (RHEED) pattern, indicating the presence of a clean dimerized surface,¹⁷ as shown in Fig. 1(a). The substrate is then cooled to 670 °C, after which a 1/2 monolayer (ML) of Sr (99.99%, Sigma-Aldrich) is deposited to form a template for the subsequent deposition and crystallization of STO.¹⁸ The substrate is then cooled to room temperature, after which an additional 1/8 ML Sr is deposited and oxidized in a background pressure of 5 × 10⁻⁷ Torr of O₂. Finally, deposition of 7/8 ML of SrO followed by codeposition of 3/2 ML of SrO and 2 ML of TiO₂ (99.99% Ti, Alfa Aesar) is performed in a background pressure of 5 × 10⁻⁷ Torr of O₂. The amorphous SrO and TiO₂ layers are then annealed in UHV at 720 °C to form 2.5 u.c. of crystalline STO. Subsequent layers of STO and LTO (99.9% La, ESPI Metals) of various thicknesses and layering sequences, discussed below, are deposited at 600 °C. The STO layers are grown in an oxygen background pressure of 5 × 10⁻⁷ Torr, whereas LTO is grown at a reduced pressure of 1 × 10⁻⁷ Torr to avoid the formation of a pyrochlore phase (La₂Ti₂O₇).^19,20

RHEED and x-ray diffraction (XRD) measurements indicate that the heterostructures are single crystalline and epitaxial to the underlying Si substrate. Sequential RHEED images for a tri-layer heterostructure comprised of 15 u.c. STO/10 u.c. LTO/4.5 u.c. STO/Si are shown in Figs. 1(b)–1(d). The streaky RHEED patterns and high contrast of the streaks from the background indicate the growth mode is 2-dimensional and that the epitaxial layers are of excellent crystallinity. XRD 2θ–ω spectra (Rigaku Smartlab diffractometer) are shown in Fig. 2(a). Data from all of the films are fit numerically and out-of-plane lattice constants (a_oop) for both the STO and LTO layers are summarized in Table I. In comparison, bulk lattice parameters are 3.905 Å and 3.97 Å for STO and LTO,²¹ respectively, with the latter being represented by a pseudocubic unit cell. The slightly larger (smaller) measured a_oop for LTO (STO) suggests that the LTO and STO are coherently strained to one another with the STO tensiley strained and the LTO compressively strained. After five unit cells, the LTO/STO layers are expected to be relaxed with respect to the silicon.²² 

One result of relaxation during film growth is increased interface roughness. Fits to x-ray reflectivity (XRR) measurements indicate that the average interface roughness is on the order of 1 u.c. (see Table I), with the roughness lowest in the 4.5 u.c. STO buffer layer on Si and highest in the topmost layer. The film roughness persists to the surface of the heterostructure stack, as indicated by atomic force microscopy (AFM, Digital Instruments Nanoscope III) shown in the right inset of Fig. 2. A high-angle annular dark-field (HAADF) image shown in Fig. 2(b) obtained using a scanning transmission electron microscope operating at 200 kV (STEM, Tecnai Osiris, FEI) indicates that the interfaces between the STO/Si and LTO/STO are abrupt at atomic length scales, although the interface between STO/LTO appears less sharp, which is consistent with the extracted roughness values from the XRR data.

Electrical transport measurements indicate that the conductivity within our LTO/STO/Si heterostructures arises from the formation of a 2DEG at the interface between LTO and STO. Four-point electrical transport measurements (Quantum Design, Physical Properties Measurement System) are performed as a function of temperature in the Van der Pauw geometry. Electrical contact to the LTO/STO/Si heterostructures is established by wire bonding Al wires to Au contacts that are deposited on the corners of 5 × 5 mm² samples. Figure 3 shows sheet resistance measurements of tri-layer heterostructures of the format 15 u.c. STO/x u.c. LTO/4.5 u.c. STO/Si as a function of the number of LTO unit cells, x. For x = 0, i.e., no LTO layer, the STO film exhibits semiconducting behavior, which we attribute to the presence of residual oxygen vacancies that act as n-type dopants. The insertion of just 2 u.c. (x = 2) of LTO into the STO film induces a significant reduction in the sheet resistance, as shown in Fig. 3. However, this decrease in sheet resistance is independent of the thickness of the LTO layer; namely, the sheet resistance does not scale with LTO thickness as shown in Fig. 3 for x = 10. From this, we can rule out conduction through the bulk of LTO, which has been shown when the films are grown oxygen-rich²⁰ or when LTO is compressively strained, where films compressively strained above 1.6% yield conductive behavior.²¹ Measurements of the lattice parameter for the LTO/STO heterostructures discussed above indicate a strain less than that required for conduction in the LTO. In addition, we calculate an upper bound for compressive strain in the LTO due to the STO in the heterostructure to be 0.7%, significantly smaller than the amount observed to yield a metal-insulator transition. From both the measured strain and the LTO thickness dependence, we conclude that conduction within our LTO/STO heterostructures occurs at the LTO/STO interface.

To further establish the presence of interfacial conductivity, the number of interfaces within our heterostructures is varied while keeping the overall thickness of the heterostructures constant. Heterostructures with 2, 4, 6, and 8 LTO/STO interfaces are grown and electrically characterized, as summarized in Table I. All samples have an identical total film thickness of 29.5 u.c., consisting of 25 u.c. of heterostructures on a 4.5 u.c. STO buffer deposited on silicon. Figure 4(a) shows that the sheet resistance is strongly dependent on the number of LTO/STO interfaces, decreasing monotonically with increasing number of interfaces.

Hall measurements show that the sheet carrier density scales with the number of interfaces within the heterostructures, indicating that the conductivity occurs predominantly at LTO/STO interfaces. We present Hall data measured at an intermediate temperature of ∼140 K, where the Hall resistance is linear over the measured field, indicating that the effects of thermally generated carriers in the Si are minimized. Scaling of the sheet carrier density with the number of interfaces within the LTO/STO/Si heterostructures is observed, as shown and summarized in Fig. 4(b) and Table I, respectively. The average sheet carrier density per LTO/STO interface, shown in Fig. 4(c), is ∼8.9 × 10¹⁴ cm⁻², which is nearly a factor of 3 higher than the theoretical limit of 3.3 × 10¹⁴ cm⁻² needed to compensate for the polar discontinuity at the interface. While oxygen vacancies in the STO generated during growth of LTO under low O₂ pressures have been cited as a potential source of additional carriers,^23,24 we believe the higher measured densities may arise from intermixing at the LTO/STO interfaces. Because the increase of carrier density does not scale with the total number of STO layers, the additional carriers cannot be attributed to oxygen vacancies in the bulk. Fig. 4(b) shows an extrapolated zero-interface intercept reasonably close to the origin, suggesting that other non-interfacial means of conduction are not significant. However, we cannot rule out oxygen vacancies that may be localized to the LTO/STO interfaces. Alternatively, intermixing of La and Sr at each LTO/STO interface could generate additional carriers. Table I shows the theoretical maximum to the 3D carrier concentration, assuming the LTO/STO heterostructures are completely intermixed to form solid solution La_xSr_1−xTiO₃. The measured 3D carrier density of each LTO/STO heterostructure is lower than the corresponding solid-solution equivalent, indicating the conductivity is predominantly an interfacial effect.²⁵ These conclusions are also consistent with the measured interface roughness for the films. Therefore, La/Sr intermixing at interfaces may explain the higher than expected measured carrier concentration.

In summary, we have demonstrated epitaxial growth of the LTO/STO oxide system onto silicon by molecular beam epitaxy. We show that the heterostructures are single crystalline and epitaxial to the Si substrate. The LTO/STO interface generates a 2DEG, which we measure to have a carrier concentration of 8.9 × 10¹⁴ cm⁻². We attribute the higher than theoretical density to additional carriers originating from intermixing at the LTO/STO interfaces, but also note that other mechanisms such as interface-bound oxygen vacancies may play a role as well. The integration of a high density oxide 2DEG on Si provides a pathway to explore the exceptional properties of this electronic system in microelectronic and photonic devices.

This work was funded by the Office of Naval Research Multidisciplinary University Research Initiative to support the EXtreme Electron DEvices (EXEDE) program, along with partial support for by the National Science Foundation through NSF DMR-1309868 and NSF MRSEC DMR-1119826. Marvin Wint, Carol Jenkins, and Alexis Ernst are acknowledged for valuable technical assistance and TEM sample preparation.