β-Gallium oxide power electronics

Andrew J. Green, James Speck, Grace Xing

With extreme rarity, a materials result has the power to rally the research community around a new semiconductor technology. There are many reasons for this, but first and foremost, potential leap-ahead performance must be present from multiple rare intrinsic material properties. Second, a materials supply chain must often be created and sustained by multiple long-term government investments (semiconductor research tends to be cost prohibitive). Finally, the research community must break through technical barriers that inhibit performance and commercialization. For the first time in decades, a research community has risen in support of a new technology. β-Ga₂O₃ has the technical and programmatic momentum not seen in decades since the rise of SiC and GaN research in the 1990s.

β-Ga₂O₃ is unique. The material has a collection of properties that, until recently, has not been observed in one system. β-Ga₂O₃ has an ultra-wide bandgap of nearly 5 eV. The material can not only conduct electrons but also maintain extremely high fields. Most importantly, it has a large, scalable low-cost substrate. These properties existing together have enabled one of the most exciting fields to explode. The availability of substrates is greater now than it ever has been, and with new companies developing substrates for commercialization in the near future, the pace of progress is expected to grow. Figure 1 shows commercialization progress for various sectors in the β-Ga₂O₃ semiconductor development chain. As expected, materials synthesis has made the most progress toward large scale production as high-quality materials are almost a prerequisite for advanced device development. While many device demonstrations have taken place, many design optimizations still need to be explored. The relatively new opportunity to purchase 2-in. diameter substrates will enable large-scale experiments. The large bandgap and field strength have created a new set of problems for materials and device researchers. To this date, avalanche breakdown has not been measured in β-Ga₂O₃. Every device breakdown to date has resulted from catastrophic dielectric failure. Until avalanche breakdown is observed, the true potential of this technology will not be known. Finally, integration and application demonstrations have still yet to be realized. The availability of large-scale substrates should be a significant enabling factor for the circuit and application demonstrations. One major step forward requires the community needs to reach up to application engineers to probe for requirements that β-Ga₂O₃ can address. Overall, the maturation of this material has progressed with incredible pace.

Per Baliga’s Figure of Merit, mobility and field strength are the main predictors of conduction losses and therefore performance for a power device. As seen in Fig. 2 (left), multiple groups have been able to demonstrate bulk doping for a variety of concentrations. This enabled the device community to make quick strides in fabricating high performance devices. Figure 2 (right) shows a collection of β-Ga₂O₃ lateral device results. Until 2016, no device in any material had measured a greater average critical field strength than SiC. (2.5 MV/cm). Since then, β-Ga2O3 has repeatedly pushed the boundaries for high field devices.

The large breadth of the device that results over the past decade is a testament to the materials quality and availability. Figure 3 shows the Power Figure of Merit (PFOM) as a function of device breakdown voltage (BV) for multiple device topologies. There are major gaps which have yet to be demonstrated. Surprisingly, voltages >3 kV have been rare in β-Ga₂O₃. This is expected to change over in the next five years as field management issues are addressed. On the right-hand side of Fig. 3, historical progress of lateral β-Ga₂O₃ device PFOMs is compared to SiC bipolar junction transistors (BJTs). Incredibly, the β-Ga₂O₃ PFOM has improved exponentially over the past decade approaching that of the BJT from the middle to late 2000s. For continued improvement, parasitic removal and field management will need to be achieved.

There has been incredible progress over the past decade, but there is still work to be done. This document serves to identify the main challenges that currently limit β-Ga₂O₃ from reaching the full performance potential. For each chapter in this Roadmap, the state of the art is described briefly followed by an analysis of the most important technical barriers in each respective section. This serves as a call to action, for if the community can address these barriers, it will enable β-Ga₂O₃ to be the next commercialized semiconductor. β-Ga₂O₃ is at a critical point in the development cycle. The materials supply chain is healthy. Device results are swift and encouraging. The technology readiness level is improving, but the community must establish application pull to attract serious investment further motivating development. This guide will help inform future research directions and help propel β-Ga₂O₃ to the world’s next great commercial semiconductor technology.

Peter Moens, Fredrik Allerstam, Krister Gumaelius, Thomas Neyer

For many decades, Si-based devices dominated the field of power electronic devices. Substantial progress and device improvement was achieved by the commercialization of the HEXFET^® transistor in the 1980s, the insulated gate bipolar transistor (IGBT) in the 1990s, and the superjunction transistor in the 2000s. Each major improvement was due to clever junction engineering using Si as the base substrate. However, since 2010, devices based on other material systems entered the market and the focus shifted from junction engineering to materials engineering. SiC diodes were introduced around 2010 and junction field-effect transistors (JFETs) and MOSFETs followed soon after. Steady and continuous improvement in SiC material quality, increase in wafer size (up to 200 mm today), and better process control have resulted in lower cost substrates. In 2019, SiC devices took up ∼3% of the total power device market (including modules) growing to exceed 12% in 2025.¹ Recently, GaN-based vertical power devices are available from several suppliers (JFETs and MOSFETs). These devices are built on native GaN bulk substrates, similar to SiC. The wafer size is limited to 100 mm. Another emerging class of devices are based on AlGaN/GaN high-electron-mobility transistors (HEMTs), which can be built on low-cost 200 mm Si wafers on which a thin (∼few μm) GaN-based layer is grown by metal organic chemical vapor deposition (MOCVD).² Although their market share is small, it is expected to grow substantially over the next few years, serving applications below 900 V. This is a similar technology to what is used for RF devices for mm wave applications. First successful attempts to grow GaN-on-Si on 300 mm have been published.³ 

Looking toward the future, a number of other wide-bandgap materials are currently being explored in research. The most studied is diamond that is considered to be the “ultimate material.” However, technological obstacles (lack of efficient n-type doping, conductive surface channels, lack of substrates, and difficulties to make ohmic contacts) have for a long time blocked the demonstration of performant devices. Unless spectacular progress is made on these issues, no real-world implementations are expected in the foreseeable future.⁴ AlN is probably the most interesting wide bandgap material because it combines high thermal conductivity with a very large bandgap of 6.2 eV. The bandgap is even higher than that of diamond (5.5 eV). Currently, a few AlN bulk substrate suppliers exist and the substrates are 2 in. in diameter or below.

Gallium oxide is the only wide bandgap material that can be grown from a melt and as such is potentially a low-cost material. It can be n-type doped by several elements with good control over a wide range. Doping from a melt results in resistivity down to 10 mΩ cm. Halide vapor phase epitaxy (HVPE) grown epi can be controlled corresponding to doping concentrations ∼10¹⁹ and mid 10¹⁵ cm⁻³, respectively. By Si implantation, resistivity can be as low as 1 mΩ cm. Ohmic and Schottky contacts can be made by using standard metals (Ti, Al, and Ni) and relatively low annealing temperatures.⁵ Wafering and lapping can be done using standard production tools. Different dielectrics [e.g., atomic layer deposition (ALD) deposited Al₂O₃] can be used as a gate dielectric. Recently, a number of publications reported on promising device characteristics and performance.^6–9 

β-Ga₂O₃ is a material system with a high critical electric field and a relatively low mobility, which allows devices with improved performance compared to SiC and even GaN. Equally important, the material can be grown from a melt and can thus be produced with a very high crystalline quality at low cost when compared to (bulk) GaN, SiC, AlN, and diamond. The crystal growth techniques used today allow scaling from 100 to 150 mm.

Figure 4 depicts the estimated critical electric field E_c vs the bandgap energy E_g for different material systems which are attractive to power semiconductor applications. Only homo-epitaxial material systems are included, which are the ones of interest for making vertical devices. β-Ga₂O₃ is well positioned in terms of E_c and has an estimated substantial lower material cost than any other ultra wide bandgap material. Figure 5 shows the predicted device performance (on-state resistance Ron vs blocking voltage capability V_bd), with the assumptions on substrate thickness and resistivity, bulk and inversion layer mobility, device pitch, etc., as calculated from basic device physics. Figure 5 clearly shows the potential to reach lower Ron for a given breakdown voltage V_bd (e.g., for a 1.2 kV device, a typical breakdown is around 1.5 kV).

Besides on-resistance (R_ON) and breakdown voltage (V_BK), also switching capacitance, output capacitance, charge, and energy are important. Based on the physics equations that relate the output capacitance (C_OSS), charge (Q_OSS), and energy (E_OSS) to the expansion on the depletion width, R_ON * Q_OSS and R_ON * E_OSS can be calculated using the same assumptions as shown in Fig. 5. Table I shows the calculated values for a 1.2 kV rated device (with an assumed V_bd = 1.5 kV). The prime transistor figures of merit R_ON * Q_OSS and R_ON * E_OSS are ∼3× better than for 4H–SiC and ∼20% better than for bulk GaN. Figure 5 and Table I show the great promise of β-Ga₂O₃ as a material for power switching devices.

There are, however, some important obstacles and areas of research which need to be overcome to make β-Ga₂O₃ based power devices economically viable and a reality in real-life power switching applications.

With a value of ∼0.2 W/cm K, β-Ga₂O₃ has a thermal conductivity which is 8× lower than bulk GaN and ∼30× lower than SiC. Efficient heat transfer is a must for power devices. This is especially true for transistors with a small overall die area. As can be deduced from Table I, for a device with the same voltage and current (or on-resistance) rating, a β-Ga₂O₃ die will be 10× smaller than a corresponding SiC die. Therefore, die thinning (<50 μm) is a must, and technologies to transfer thin die directly to the lead frame need to be explored. The possibility to easily cleave the β-Ga₂O₃ may pose a way forward to produce very thin die. In addition, heat removal from the top surface needs to be studied through innovative assembly technologies. Demonstrations of heat removal techniques^10,11 are expected to be a major research area as devices begin to be distributed throughout the community in the next five years. This will have major ramifications with respect to application space (i.e., power rating and duty cycle).

To date, there is no p-type doping in β-Ga₂O₃ since acceptor states are deep in the bandgap, >1 eV from the valence band. The valance band is also theorized to be flat resulting in negligible hole transport. This means that no avalanching p–n junction can be made. The lack of an avalanching junction is a concern for applications that are used in regions with noisy power grids or need to take over large inductive loads rapidly, like UPS systems.

Management of the electric fields at the die edge is an important device design focus point, as it impacts the voltage rating of the transistor or diode as well as its reliability. For termination structures, the lack of p-type can perhaps be mitigated by the integration of p-type oxides, such as sputtered NiO. Also beveled terminations are under investigation.

Today, the maximum wafer size that is commercially available is 100 mm. From a practical commercial point-of-view, the minimum wafer size should be 150 mm, with a roadmap to 200 mm. Larger wafer size does not only reduce the product cost but also allows the device processing in more advanced fabrication lines, which result in better process control, lower defect densities, etc.

Ga₂O₃ has many poly-types, among which the α-phase and β-phase are the most investigated. α-Ga₂O₃ is rhombohedral, has a high E_c ∼ 10 MV/cm, but is only thermally stable up to ∼600 to 700 °C. Since Al₂O₃ and epitaxial In₂O₃ have the same α-structure, it paves the way to hetero-structures in a similar way as is done for the AlN/GaN/InN material system. P-type would be possible through combination with α-Ir₂O₃ and α-Rh₂O₃, which are p-type oxides. These hetero-structures are, however, lateral device types. β-Ga₂O₃ is monoclinic, can be grown from a melt, and is thermo-mechanically stable until 1700 °C. From a research perspective, the multitude of different phases is interesting, but from a commercialization point of view, it would be preferred if the development effort could be focused on the β phase due to the maturity of the sample supply chain.

The lack of p-type also puts restrictions on how to make e-mode transistors. First results using fin field-effect transistors (FINFET) type of accumulation FETs are promising but require tight process control and advanced processing equipment. It remains to be seen if this is a viable option. Another option is to use a depletion mode transistor cascoded with a Si (or other) low voltage MOSFET. Market adoption for cascaded SiC JFETs or AlGaN/GaN HEMTs is limited due to the fact that the internal node cannot be controlled during switching.

Reliability on any type of β-Ga₂O₃ device (diode or transistor) is still in its infancy.

From a power device manufacturer’s perspective, β-Ga₂O₃ is the preferred ultra wide bandgap material because it can be grown from a melt and has a high crystalline quality and a relatively low cost. There is a roadmap to 150 mm. The lack of p-type is a serious drawback for transistors. On the plus side, most of the fundamental process modules for making β-Ga₂O₃ Schottky diodes are available: standard Ohmic and Schottky metallization’s, good control of the n-type doping of the epi, and low resistivity substrates. Termination structures for the diodes will have to be optimized and further developed. A good market entry point for these diodes could be the 600 V and 1. 2 kV voltage classes, where they will compete with SiC diodes, e.g., for high-end power supplies used in server farms or in boost stages of energy efficient power converters. These devices could potentially offer better than SiC performance at reduced cost. According to Ref. 1, this market alone will amount to 100 M$ by 2025 and is driven by efficiency standards mandated by governments. β-Ga₂O₃ diodes will potentially enable a further improvement step from “80 plus” titanium (currently the highest certification level for power supply efficiency) with efficiencies exceeding >95% at full load. If by that time β-Ga₂O₃ diodes can prove reliability at good cost and they can be sourced easily on the power electronic market, they could take significant share of the TAM in 2025.

At higher voltage classes (e.g., 1.7 kV and beyond), doping control has to be proven to be reproducible and stable for production. In addition, the larger surface fields will create additional challenges with the passivation layers on top of the termination. Below 600 V, there will be competition also with lateral devices that are not limited to bulk properties.

Andrea Arias-Purdue, Vivek Mehrotra

Much of the traditional military system’s power conversion needs have been fulfilled by sub-assemblies that have continuously leveraged improvements in commercial semiconductors and integrated circuits, such as state-of-the-art MOSFETs, drivers, and controllers. For applications ranging from low-voltage to kV power converters, switched-mode power supplies have become the dominant approach due to their efficiency benefits. For example, switching regulators (such as buck converters) offer typical efficiencies of 70%–95%, up to switching frequencies in tens of megahertz for commercial parts^12,13 and up to hundreds of megahertz in research.^14–16 This remarkable progress is also complemented by research efforts such as DARPA’s Microscale Power Conversion (MPC) program,^17,18 where DARPA requested a ∼1 GHz switching GaN-based power converter to enable very high bandwidth and efficiency supply modulators for power amplifiers. Significant challenges surfaced during the MPC effort. The switches and gate drivers developed needed to have at least an order of magnitude less total gate charge and power dissipated, respectively, for efficient 1 GHz switching converters (28 mΩ nC¹⁹ is the lowest R_ON × Q_G demonstrated under MPC). It also became apparent that the co-design of the power amplifier and the switch modulator would result in the most efficient system design.

As new wider bandgap semiconductor materials have matured and have become widely available (i.e., SiC and GaN devices), state-of-the-art modules with progressively improved performance have followed—improvements in size, weight, efficiency, operational temperature range, and cost. In addition, several DoD systems require ruggedness at high ambient temperature: for this reason, ultra wide bandgap (UWBG) materials, such as β-Ga₂O₃, are excellent candidates for maximizing performance even under these extreme environmental conditions. While several circuit techniques can be employed to effectively switch a power circuit at a frequency higher than its individual branches, we note that the maximum performance benefit is often achieved when the power commutation path is monolithically (or perhaps 3D) integrated using the least number of components, thus operating at the maximum feasible switching frequency as allowed by the device’s dynamic losses and as permitted by the intrinsic losses of the wiring closing the critical power commutation path.

Switching power converters operating at >1 GHz remain a challenge due to the stringent R_ON × Q_G requirements imposed on the main switch, a necessary condition to achieve high efficiency. Owing to its ultra-high Baliga figure of merit, β-Ga₂O₃ MOSFETs with over 3.8 and 5.3 MV/cm of mean peak breakdown field strengths²⁰ have been demonstrated, constituting the highest field of any lateral FET measured to date. The key requirements for next-generation β-Ga₂O₃ power devices and ICs are low loss power devices for high frequency operation: low conduction (R_ON) and switching losses (Q_G) and low turn-on and turn-off energy. We estimate that a sheet charge density N_SH of 9.6 × 10¹² cm⁻² and a state-of-the-art mobility of 200 cm²/V s along with a contact resistance of 0.1 Ω mm and submicrometer access regions will enable β-Ga₂O₃ devices with a total gate charge Q_G ∼ 0.8 pC/mm for a >100 V breakdown voltage lateral device, a >5× improvement with respect to state-of-the-art GaN switches.

One of the key advantages of UWBG materials is their ability to withstand high ambient temperature, as demonstrated in Ref. 21, where β-Ga₂O₃ MOSFETs showing stable operation up to 300 °C were reported. In addition, packaging to enable high reliability in harsh environments will be required, taking into account coefficient of thermal expansion (CTE) matching and incorporating heat spreading, given the low coefficient of thermal conductivity for β-Ga₂O₃. It is likely that the development of new encapsulation compounds will be needed, simultaneously requiring low signal-loss and considering the device thermal budget. These challenges will need to be addressed at the multi-chip package level. Monolithic integration of power devices, gate drivers, and passives for lower parasitic beyond a certain critical frequency (∼1 GHz) becomes necessary, since stray inductance and capacitance can completely negate the benefits of high frequency switching. Currently, magnetics are available which address switching frequencies at 1 GHz. Advanced 3D integration that can enable approximately tens of micrometers pitch between different chips is also a viable option.

High switching frequency (>1 GHz) enables size reduction of magnetics and capacitors as well as high bandwidth control for special applications, such as transient loads and envelope tracking (ET). For example, for ET, the output of the converter may be a pulse-width modulated signal with a control bandwidth that needs to be 10× faster than the signal bandwidth. Reduced volume magnetics are especially relevant for size-constrained platforms, such as Unmanned Aerial Vehicle (UAV) power systems and phased array power distribution, which necessitate both high efficiency due to limited heatsinking and small components due to the constrained area available in arrays operating at mm-wave frequencies. The magnetics required to support 1 GHz converters will have negligible hysteresis and Eddy current losses, with enough magnetic permeability and saturation flux density up to ∼10 GHz. We note that to materialize high speed converters, these passive components will have to be developed alongside emerging β-Ga₂O₃ devices. Novel materials such as FeSi-based magnetic compounds are possible candidates.²² 

Gate drivers are key to the implementation of the converter: they are essentially pulse amplifiers. The input pulse train from a control circuit defines the interval during which the main power switch should be on and off. The function of the gate driver circuit is to supply and remove charge from the gate of the main switch rapidly so that its state reflects the desired condition. The rate at which this charge is delivered and taken away is a major factor in determining how fast the main device switches. To maintain a square gate pulse, power delivery to each switch gate containing up to several harmonics of 1 GHz carrier fundamental is required to preserve high efficiency. In addition, realizing high efficiency, the gate driver output stage capacitances must be considerably less than those of the power device. To minimize switching losses, the gate driver must be able to turn the switch on and off at least additional 10× faster (10% of the period), leading to an extremely challenging 20 ps rise and fall time requirement of the converter’s pulse width modulated (PWM) output waveform, for a 1 GHz carrier converter. We note that the current state-of-the-art commercial gate drivers exhibit ∼350 ps of rise and fall times,²³ while research gate drivers have been demonstrated to switch at 1 GHz carrier while exhibiting 106 ps/122 ps transitions and consuming 3 W of power,²⁴ not yet adequate for 1 GHz converters—since ∼5× faster transitions are required. Therefore, to enable 1 GHz β-Ga₂O₃ converters, a new class of ultra-short transition and low power consumption gate drivers must be developed, and critically, they must be integrated alongside the main switch power commutation loop so that stray inductance does not significantly lower the system efficiency. While highly scaled GaN could potentially be used if a suitable complementary technology was developed, it is possible that the most efficient gate driver solution would come from specifically tailored highly scaled β-Ga₂O₃ MOSFETs.

For Pulse Width Modulated (PWM) converters, the switch rise and fall times must be negligible as compared to both carrier frequency and minimum duty cycle—this is important to maintain low switching losses. Both the power switch and the control elements’ bandwidth must be at least 20× greater than the fundamental switching frequency for negligible dynamic losses. In addition to switching frequency, control rise/fall time can be optimized to better leverage the β-Ga₂O₃ device’s low gate charge by generating very high device slew rates, thus minimizing dynamic losses. An application where this feature can offer a critical advantage is direct AC to AC conversion.

For many applications, a synchronous converter topology can be chosen to maximize efficiency: this is expected to also apply to ∼1 GHz switching converters.

We note that for power distribution systems, an intermediate bus structure and Point of Load (PoL) regulators provide flexibility and maximize efficiency, and coupled with their high frequency and smaller footprint, β-Ga₂O₃ converters will provide the necessary degrees of freedom for high performance power system design.

For Pulse Width Modulated (PWM) converters, the switch rise and fall times must be negligible as compared to both carrier frequency and minimum duty cycle—this is important to maintain low switching losses. Both the power switch and the control elements’ bandwidth must be at least 20× greater than the fundamental switching frequency for negligible dynamic losses. In addition to switching frequency, control rise/fall time can be optimized to better leverage the β-Ga₂O₃ device’s low gate charge by generating very high device slew rates, thus minimizing dynamic losses. An application where this feature can offer a critical advantage is direct AC to AC conversion.

For many applications, a synchronous converter topology can be chosen to maximize efficiency: this is expected to also apply to ∼1 GHz switching converters.

We note that for power distribution systems, an intermediate bus structure and Point of Load (PoL) regulators provide flexibility and maximize efficiency, and coupled with their high frequency and smaller footprint, β-Ga₂O₃ converters will provide the necessary degrees of freedom for high performance power system design.

β-Ga₂O₃ and GaN switch performance is compared in Fig. 6. The projected β-Ga₂O₃ curves correspond to aggressively scaled devices (50 nm of gate length with sub-micrometer drain to source spacing assuming 383 and 500 V/μm of breakdown voltage for the best material parameters and ideal material parameters curves, respectively). The assumed material and calculated device parameters are included in Table II. We note that even based on the best β-Ga₂O₃ material parameters reported to date, our projected β-Ga₂O₃ device has a considerably lower R_ON × Q_G product as compared to both COTS and SOA GaN HEMTs of similar voltage rating.

Future DoD needs include next generation phased array power distribution: high efficiency will require point of load (PoL) power conversion at the element/tile array level while also leveraging high bandwidth adaptive supplies to maximize the transmitter efficiency. It will be important to leverage high control bandwidths and ultra-low size and weight in mm-wave arrays (very compact platforms due to the lambda/2 spacing requirement) to fulfill the need for high efficiency. UAV applications, typically also requiring lower voltage, will consist of similar needs—ultra-size, optimized PoL converters. We envision a modular library of PoL β-Ga₂O₃ power devices that can fulfill these needs for a host of power conversion ratios—both boost and down converters—and power levels.

Reduced size, high efficiency converters for emerging applications, such as mm-wave digitally steered arrays and next generation UAVs, will necessitate fundamentally advanced power switches. β-Ga₂O₃ is poised to enable next generation power systems due to its superior material properties that enable its potential for significantly lower dynamic power losses as compared to Si and GaN, as well as its ability to withstand harsher environmental conditions, in part, due to its wider bandgap.

While it might not be advantageous to increase the converter switching frequency for high power applications (>100 W), the control bandwidth can be increased, thereby resulting in significant system efficiency improvements. To better understand these practical limitations, the intrinsic material-driven losses (wiring stray capacitance and inductance) must be considered within the converter design space to establish a fundamental switching frequency vs power loss trend for the wiring environments (including filter components) available to the power electronics designer.

Akito Kuramata, Kohei Sasaki, Shinya Watanabe, Kimiyoshi Koshi

The most important index affecting the economic model of β-Ga₂O₃ for power-device applications is the device price per unit current. The index is determined by the wafer price and the current density of devices. It is expected that β-Ga₂O₃ wafers will be able to be manufactured at low cost because β-Ga₂O₃ is suitable for melt growth, has medium hardness, and can be easily processed.²⁶ This expectation is in contrast to the situation of other new power device materials, such as SiC or GaN, which suffer from high wafer manufacturing costs due to difficulties in bulk growth and wafer processing. Furthermore, since Baliga’s figure of merit for β-Ga₂O₃ is larger than that of SiC or GaN, it is expected that the on-resistance of diodes or transistors can be reduced, and as a result, the current density can be made large.²⁷ Low-cost production will be enabled by filling the technological gaps in terms of the two factors mentioned above. In this chapter, we describe the challenges to reducing the wafer price of β-Ga₂O₃. See the discussion in Chaps. II, III, XI, XII, and XIII for challenges involved with improving device performance.

The present commercialization status of β-Ga₂O₃ substrates and epitaxial wafers are as follows: Currently, substrates made by the edge-defined film-fed growth (EFG) method in wafer sizes up to 4 in. are commercially available. In addition, 6-in. EFG substrates have been fabricated⁵ and 2-in. substrates made by the Czochralski (CZ) method are expected to be commercially available in 2021.²⁸ Growth of 2-in. bulk crystals by using the vertical Bridgman (VB) method has been reported.²⁹ As for β-Ga₂O₃ epitaxial wafers, 4-in. wafers grown by halide vapor phase epitaxy (HVPE)³⁰ and 1-in. wafers grown by molecular beam epitaxy (MBE) are commercially available.³¹ Metal organic chemical vapor deposition (MOCVD) epitaxial growth with excellent electrical properties has been reported.³² β-Ga₂O₃ epitaxial wafers are still more expensive than SiC epitaxial wafers of the same size because β-Ga₂O₃ devices have not been commercialized yet and few wafers have been produced.

The challenges of low-priced wafer production are described below.

The biggest challenge to lowering the manufacturing cost of bulk β-Ga₂O₃ crystal is that some of the expensive precious metal crucibles are lost during crystal growth or by recasting. In the EFG method and CZ method, Ir, which has a high melting point and can be used only in a low-concentration oxygen atmosphere, is used as a crucible material. Galazka et al. pointed out that a small amount of Ga exists in an equilibrium state of the gallium oxide melt above the melting point, and when it reacts with Ir, part of the crucible is lost.³³ This problem becomes more serious as the size of the substrate increases. In the case of the EFG method, the lifespan of the crucible is about 6 months in the production of 2-in. bulk crystals, whereas during trial production of 6-in. bulk crystals, some holes opened at the bottom corner of the crucible after a considerably shorter period. In the case of 6-in. bulk crystals, the amount of Ga increases as the amount of Ga₂O₃ melt increases, and the temperature difference inside the crucible increases, resulting in increased reaction in the high-temperature part of the crucible. These phenomena are presumed to shorten the lifespan of the crucible. As far as the EFG method and CZ method go, it is possible to solve this problem by reducing the size of the crucible. In the VB method, the temperature distribution in the furnace can be narrowed and the maximum temperature can be lowered, which expands the choice of metal materials. On the other hand, the method requires an atmosphere with a high oxygen concentration. Under such conditions, Pt–Rh alloy is a suitable crucible material.²⁹ The VB method can reduce the amount of precious metal lost in one growth, but it is necessary to recast the crucible after each growth. Therefore, the amount of precious metal wear cannot be reduced by more than an order of magnitude. The floating zone (FZ) method enables crystal growth without using precious metals, but the diameter of the reported crystals is as small, about 1 cm, and there are no reports of large crystals having been successfully grown.

The challenge regarding the wafer fabrication process is to increase the number of substrates taken from one bulk. To meet it, the thickness of the substrate should be reduced. β-Ga₂O₃ has the property of being easily cleaved on the (100) and (001) planes. In order to suppress cracking of the wafer due to cleavage, bevel processing has to be performed with high accuracy. Since gallium oxide has a crystal structure of a monoclinic system with low symmetry, the ease of scraping and cracking of the crystals differs depending on the position of the outer peripheral portion of the wafer. As such, a fine processing technique is required, such as by changing the processing conditions according to the position of the outer periphery of the wafer. The crystallographic planes of β-Ga₂O₃ substrates commercially available at present are the (100), (010), and (001) because epitaxial layers with good crystalline quality can be grown on these planes. Other intrinsic material properties of interest are transport (which is thought to be isotropic), thermal conductivity, and field strength (which is thought to be anisotropic). Manufactures have chosen to prioritize yield and growth quality when producing wafers, although other orientations may be of interest. Process optimization should be done in different ways appropriate for each plane. It is also necessary to take measures to reduce the amount of scraping in the polishing process. The related steps are the slicing step, grinding step, polishing step, and Chemical Mechanical Polishing (CMP) step, but in each step, it is necessary to remove a region thicker than the damaged layer generated in the previous step. To reduce the total amount of scraping as much as possible, a processing method that causes less damage has to be developed. To date, a detailed methodology above has not been published. Optimization of this process may have significant impact on the future of β-Ga₂O₃ manufacturing cost.

HVPE or MOCVD is a candidate of the epitaxial growth method for vertical power devices that require a thick film, while MOCVD or MBE is a candidate for lateral power devices that require a film with a flat surface. Regardless of which epitaxial growth method is chosen, the cost challenge is the same, which is to increase the number of wafers to be manufactured per unit equipment per unit time.

One solution is to use multi-wafer equipment. However, at present, there is no multi-wafer equipment capable of mass production in HVPE or MOCVD. It is expected that with increased investment into the technology, multi-wafer equipment will be offered by tool manufacturers. The current HVPE apparatus has a hot-wall-type configuration with a reactor made of quartz, since GaCl is used as a raw material. The reactor made of quartz makes it difficult to build large, reproducible manufacturing equipment. In particular, the gas flow changes because of the low dimensional accuracy of the quartz parts. If the HVPE method is to be used in the future, a mass production furnace with high dimensional accuracy has to be developed. HVPE systems have not been commercially available but have been originally designed. We are planning to develop an advanced HVPE system to increase the production volume. The system will be developed by 2023 which will produce 7 × 150 mm² epitaxial wafers per run. On the other hand, the barrier to realizing multiple-wafer growth in MOCVD is low because it usually uses a stainless-steel reactor. However, the MOCVD has another problem: the Ga metal organic raw material it uses is expensive.

Another solution is to increase the rate of epitaxial growth. The current growth rate is about 10 µm/h in the HVPE method and about 1 µm/h in the MOCVD method (while maintaining high mobility). The HVPE method is desired to be several times faster, whereas MOCVD is desired to be one order of magnitude faster. In addition, countermeasures to shorten the interval between growths, such as by using a maintenance-free furnace or high-temperature transportation system, would affect a cost reduction.

Figure 7 shows the expected β-Ga₂O₃ wafer price against production volume. The values were calculated by considering the progress level of β-Ga₂O₃ crystal growth and epi-film formation technology which will be available in 2027 for 150 mm wafer size. The β-Ga₂O₃ wafer price is anticipated to decrease drastically with increasing production volume due to several factors as explained earlier in this section. These low-priced wafers will offer substantial cost-competitive merits in the discrete market sector.

In this chapter, we described the technical challenges to reducing the wafer price of β-Ga₂O₃. If the challenges described here can be resolved and the number of wafers manufactured increased to mass production scale through commercialization of β-Ga₂O₃ power devices, the price of β-Ga₂O₃ epitaxial wafers may be reduced to less than one-third those of SiC epitaxial wafers. If devices with low electrical resistance and low thermal resistance per unit area are developed owing to advances in device design and fabrication technology, the device price per unit current is presumed to fall even further. If they are achieved, it is expected that the manufacturing of β-Ga₂O₃ power devices will proceed and capture a large market, especially in the high voltage and high current applications. Performance at a cost reduction is quite possibly the most attractive trait of β-Ga₂O₃ due to the rampant competition in the semiconductor sector. Although continuous improvement of SiC material quality and scaling in wafer size up to 150 mm have resulted in low-cost substrates, the β-Ga₂O₃ substrate quality has also been improving in line with expanding in diameter at a rate more than twice of SiC since 2004. With time, 150 and 200 mm β-Ga₂O₃ wafers are expected to be commonplace which will offer significant cost competitive advantages for vertical FETs and Schottky barrier diodes (SBDs).

John Blevins

In this section, we examine the techniques used for growth of bulk β-Ga₂O₃ single crystals. Gallium oxide is known to form five crystalline polymorphs. The β phase is the only stable polymorph at growth temperatures above 1800 °C and 1 atm pressure. The application of melt-based growth techniques provides significant manufacturing, cost, and scalability advantages compared to vapor transport processes used for other wide bandgap single crystals, such as SiC, GaN, and AlN. β-Ga₂O₃ is the only wide bandgap semiconductor capable of crystallization from a melt utilizing industrial scale manufacturing techniques, such as Vertical Bridgman (VB),³⁴ Czochralski (CZ),³⁵ Edge-Defined Film-fed Growth (EFG),³⁶ and Float Zone (FZ).³⁷ The majority of β-Ga₂O₃ bulk growth research and development to date has focused on the CZ and EFG techniques. Presently, Novel Crystal Technology (NCT, Japan) is the only commercial provider of bulk β-Ga₂O₃ substrates utilizing the EFG technique. High quality β-Ga₂O₃ substrates of differing orientations and doping are commercially available in sizes ranging from 25 × 25 mm² for (010) and 100-mm for (⁠$2̄$01).²⁶ Kuramata et al. showed the growth of (⁠$2̄$01) oriented crystals up to 150-mm by the EFG method.³⁸ The Leibniz Institute for Crystal Growth (IKZ Germany) is a leading research institute for CZ β-Ga₂O₃, having made numerous contributions to understanding the scalability of β-Ga₂O₃ single crystals.³³ Their research clearly demonstrated the necessity of increasing the O₂ concentration in the growth atmosphere with increased crystal diameter. IKZ has grown 50-mm diameter single crystals exceeding 50-mm in length weighing up to 1 kg and are the largest grown by any method. In the U.S., Northrop-Grumman SYNOPTICS has been developing both 25 and 50 mm semi-insulating (010) CZ β-Ga₂O₃ substrates (Fig. 8) that have recently become commercially available. Typical x-ray rocking curves are <75 arc sec with surface roughness <1 nm. The prospect for growing large diameter, low cost β-Ga₂O₃ bulk crystals provides an added incentive for development of this promising next generation semiconductor material.

Impressive device results and early demonstration of large diameter single crystals has stimulated interest in this promising next generation semiconductor. The maturation of any semiconductor device technology can be accelerated by the availability and/or promise of large diameter, high quality, and low-cost native substrates. Wide bandgap semiconductors, namely, SiC, faced significant commercialization challenges due to monumental sublimation growth technology barriers. It took Cree (Wolfspeed) 20 years from the company founding to the commercial release of 100 mm substrates. Approximately 16 years transpired between the commercial availability of 25 and 100 mm SiC substrates.⁴³ Today, 100 and 150 mm SiC substrates are manufactured at a cost, quantity, and quality never thought possible. The wide bandgap semiconductor manufacturing infrastructure has evolved such that a minimum of 100 mm diameter substrates will be required to access large scale, compound semiconductor manufacturing facilities. A 2019 National Renewable Energy Laboratory (NREL) study estimated a 3× cost advantage of β-Ga₂O₃ compared to SiC substrates leading to 2× lower cost power electronic devices.⁴⁴ This study alluded to the relative ease of scaling and potential for low-cost manufacturing of β-Ga₂O₃ substrates, providing a solid foundation for rapid commercialization. Despite rapid progress with CZ and EFG growth process development, it should be recognized that specific “bulk” material requirements remain largely undefined beyond a preference for N-type or semi-insulating. Significant work remains with epitaxial and device process development before bulk crystalline requirements, such as dopant, defect density, and resistivity, are clearly understood. Semiconductor manufactures tend to be growth technology agnostic rather focusing on a combination of technical, manufacturing, and cost factors for selecting a substrate.

Fabrication and polishing of β-Ga₂O₃ merits discussion. Processing of boules and ribbons present differing challenges. The presence of two strong cleavage planes parallel to the (100) and (001) planes complicate boule fabrication and polishing. These crystal planes are highly susceptible to mechanical stress and can easily form cleaves and/or crack during fabrication (coring, grinding, and wire sawing) and polishing. EFG ribbons are typically not subjected to these mechanical processes. As such, fabricating substrates from ribbons are less susceptible to damage. However, ribbons are not the preferred method of manufacturing semiconductor substrates.

Regardless of the crystal growth technique utilized, standards for substrate parameters, such as flats, orientation, thickness, flatness, surface roughness, total thickness variation, and associated tolerances, will be required. Additionally, electrical (resistivity, doping levels) and crystalline (dislocation density and x-ray rocking curves) requirements will evolve as the device fabrication process matures. Substrates that are round and flat (bow/warp <20 μm) with FWHM <50 arc sec and “epi-ready” surfaces should be the immediate focus of the industry. Near term availability of 50 mm substrates will broaden research and development interest, but production will likely demand 100 mm or larger substrates. Both CZ and EFG appear to be well positioned to address near term substrate requirements. Regardless of the advantages melt-based crystal growth processes provide, bulk growth of β-Ga₂O₃ is not without significant technical hurdles which are further highlighted below.

Czochralski (CZ) is the de facto standard method for manufacturing a variety of large diameter single crystal boules, such as silicon, sapphire, germanium, and gallium arsenide. CZ’s primary attributes are its scalability, manufacturability, and low cost. Due to the high growth temperature (>1800 °C) of β-Ga₂O₃, crucible options are presently limited to iridium due to the high growth temperature and oxidizing environment. The use of iridium introduces significant cost and manufacturing challenges due to susceptibility to oxidation in atmospheres of only a few percent oxygen and decomposition of the melt forming metallic gallium further reacting with the iridium crucible forming eutectic or intermetallic phases.⁴⁰ Increasing the oxygen partial pressure can suppress the decomposition of the melt but will subject the iridium crucible to further oxidation. Galazka et al. showed that undoped layers have been shown to be insulating scale-up of β-Ga₂O₃ crystal size is strongly affected by the formation of metallic gallium in the melt and that scale-up to 100 mm diameter crystals may require oxygen containing atmosphere up to 100%.³³ SYNOPTICS has shown that an atmosphere of 91% CO₂ and 9% O₂ is sufficient for growth of (010) Fe-doped single crystals up to 60 mm in diameter, but crucible lifetime remains an ongoing concern.²⁸ 

• Management of growth atmosphere and melt decomposition.

• Iridium crucible cost and maintainability.

• Diameter scalability to 100 mm and larger.

• Defect identification and mitigation.

• Uniform dimensional, crystalline and electrical parameters.

• Boule and substrate yield.

Edge Defined Film Fed Growth (EFG) was originally developed by LaBelle and Mylavski for growth of sapphire ribbons. EFG remains the technology of choice for growth of large sapphire windows and complex geometries. It is not the preferred approach for large scale manufacturing of semiconductor substrates. EFG’s primary attributes are its high growth rates exceeding 10 mm/h, scalability, and manufacturability of large single or multiple ribbons. Iridium crucibles are still required but are less susceptible to oxidation and melt volatilization due to the reduced area of the exposed melt surface. NCT has successfully commercialized EFG for a variety of sizes, orientations, and dopants and demonstrated scalability of (⁠$2̄$01) substrates up to 150 mm.³⁸ 

• Scalability of (010) oriented substrates beyond 25 mm.

• Manufacturing throughput and cost.

• Defect mitigation.

• Uniform dimensional, crystalline, and electrical parameters.

The float zone method is a melt-based technique most commonly used to manufacture high resistivity silicon single crystals up to 200 mm diameter. The OFZ method is a variation of the float zone method used to grow β-Ga₂O₃. Single crystals of β-Ga₂O₃ are grown without a crucible, enabling the use of high oxygen atmosphere. A uniform polycrystalline rod is required and is readily available for silicon but not for β-Ga₂O₃. High purity β-Ga₂O₃ powders must be combined with preferred dopant and compacted and sintered to form a suitable rod. The use of an RF heat source is not an option due to the low conductivity of β-Ga₂O₃. Rather halogen lamps provide the heat source. Víllora et al. was the first to demonstrate growth of 25 mm in diameter crystals with three differing crystallographic orientations: (100), (010), and (001).³⁷ β-Ga₂O₃ single crystals were grown in the [010] direction at a growth rate of 6 mm/h. The OFZ method is not easily scalable beyond 25 mm and as such is not competitive with other melt-based techniques.

• Diameter scaling severely limited by halogen lamp heat source.

• Doping techniques.

• Industrial research and development commitment.

• Defect identification and mitigation.

• Uniform dimensional, crystalline and electrical parameters.

Vertical Bridgman and/or its variants (vertical gradient freeze) are common techniques used in manufacturing III–V single crystals up to 150 mm in diameter. This technique involves the directional solidification of the melt from the hot zone to the cold zone by controlling the movement of the crucible or hot zone. Single crystals can be grown with or without seed utilizing a Pt–Rh alloy crucible, enabling the use of high oxygen atmosphere without risk of crucible oxidation. Diameter control is unnecessary because the diameter is determined by the inner diameter of the crucible. The first application of the vertical Bridgman (VB) method to β-Ga₂O₃ was demonstrated by Hoshikawa et al., and they reported growth of 25 mm diameter (100) single crystals without a seed in ambient air, with no adhesion of the crystals to the crucible wall.³⁴ Recent efforts demonstrated 50 mm diameter Sn-doped β-Ga₂O₃ crystals with growth orientation perpendicular to the (001) plane utilizing a resistance heating furnace with platinum–rhodium alloy crucibles in ambient air.²⁹ 

• Scalability of the growth process.

• Industrial research and development commitment.

• Use of a Pt–Rh alloy crucible.

• Defect identification and mitigation.

• Uniform dimensional, crystalline and electrical parameters.

β-Ga₂O₃ is a novel ultra-wide bandgap semiconductor that combines high theoretical figure of merits with growth of single crystals with proven manufacturing techniques such as CZ and EFG. While a variety of growth techniques have been utilized to grow β-Ga₂O₃ single crystals, it is too early in the development cycle to suggest that one technique is superior to competing approaches. Until such a time that a volume application emerges, it is conceivable for multiple techniques to co-exist. Generally speaking, near term (1–3 years) availability of 50 mm β-Ga₂O₃ substrates with desired surface orientation, N⁺ or semi-insulating (>10⁸ Ω cm), good crystallinity (FWHM <50 arc sec), and low defect density (<10⁴ cm⁻²) should be a goal for the industry going forward. The availability of such substrates should sustain development for several years to follow. Ultimately, a minimum of 100 mm will be required for access and subsequent transition to commercial compound semiconductor foundries. Presently, both CZ and EFG techniques appear to be best positioned to address near term substrate requirements. The extent of research and development of these techniques exceeds other approaches. EFG substrates produced by NCT have been commercially available for several years. CZ substrates from SYNOPTICS have become commercially available in 2021. EFG is not the preferred approach for semiconductor substrate manufacturing, but it could address β-Ga₂O₃ requirements for non-(010) oriented substrates. CZ has a long history of scalability and low-cost manufacturing; there will always be a preference for CZ. However, CZ faces unique challenges not faced with other techniques. Galazka et al. showed that CZ scalability will be dictated by the ability to control the growth environment such that melt decomposition and crucible oxidation are mitigated, enabling a cost-effective manufacturing process. The recent market spike in iridium prices could impact development and manufacturing. Vertical Bridgman remains an attractive approach notwithstanding the lack of a stronger industrial developmental commitment as well as addressing the added cost Pt–Rh alloy crucibles. The commercial availability of native larger diameter β-Ga₂O₃ substrates are critical to the long-term development of this novel ultra-wide bandgap semiconductor technology.

Oliver Bierwagen

Close to a decade ago, the research field of β-Ga₂O₃-based power electronics got started by the seminal work of Higashiwaki et al.,²⁷ describing the theoretical potential of β-Ga₂O₃ coupled with the demonstration of a MESFET device with high breakdown voltage. This demonstrator device was based on a homoepitaxial, Sn-doped layer grown by molecular beam epitaxy (MBE) on a (010)-oriented, semi-insulating, Fe-doped β-Ga₂O₃ substrate. It has to be stressed that the availability of the β-Ga₂O₃ substrate from bulk growth enables the homoepitaxial growth of functional layers by MBE and other film growth techniques with highest structural quality. Living up to its pioneering role by realizing high quality layers with simpler growth chemistry than metal organic vapor phase epitaxy (MOVPE)/MOCVD, the MBE growth of β-Ga₂O₃ has evolved rapidly in the past years: homoepitaxy has been demonstrated with growth rates up to few nm/min on the available orientations [(100), (010), (001), and (⁠$2̄$01)].^45,46 Undoped layers have been shown to be insulating,⁴⁷ and the n-type conductivity has been controlled by donor doping with Sn,^31,48 Ge,⁴⁹ and Si⁵⁰ up to electron concentrations of 10²⁰ cm⁻³. Widening the bandgap⁵¹ by alloying with Al₂O₃⁵² enabled the MBE-growth of modulation-doped (Al,Ga)₂O₃/Ga₂O₃ single⁵³ and double⁵⁴ heterostructures that confine a two-dimensional electron gas (2DEG). With average breakdown fields of ∼3 MV/cm, these high-electron-mobility transistor (HEMT) structures are promising candidates for high frequency and high-power device applications.

Despite these advances, a number of challenges need to be addressed for MBE-grown layers to be used in competitive power electronics devices. Some of these challenges are specific to MBE, whereas others are universally observed.

General challenges for the epitaxy of β-Ga₂O₃ relate to extended structural defects in the film, the film morphology that deviates from a flat surface, as well as limits for the alloy composition of (Al,Ga)₂O₃ and (In,Ga)₂O₃ with consequences on band-offsets and electron confinement. The low symmetry of the monoclinic crystal structure and related anisotropy plays an important role for most of these general challenges posing the question of “the ideal” surface orientation for devices and epitaxial film growth. As mentioned earlier, this has ramifications with respect to bulk orientation preference as well. Challenges more specific to MBE concern the growth rate, as well as doping by intentional and unintentional impurities as well as possibly point defects.

In comparison to other epitaxial techniques, MBE is usually limited to comparably low growth rates, which are sufficient for horizontal devices but too small for vertical devices requiring thick (e.g., >5 μm) layers. Conventionally, the MBE growth of β-Ga₂O₃ is realized by the reaction of Ga vapor with reactive oxygen (ozone or plasma) on the heated substrate surface in a high-vacuum environment. Unlike in the MBE of GaAs or GaN, the MBE growth rate and temperature of Ga₂O₃ are strongly limited by temperature-driven desorption of the volatile suboxide Ga₂O (instead of Ga) that is formed as an intermediate reaction product on the substrate before further oxidation to Ga₂O₃.⁵⁵ The strong anisotropy of the surface free energy⁵⁶ and related bonding strength to adatoms (e.g., Ga) or ad-molecules (e.g., Ga₂O) results in a strong dependence of the growth-rate limiting suboxide desorption on surface orientation with the resulting largest growth rate (3 nm/min) and surface free energy for the (010) surface and smallest ones (0.17 nm/min) for (100) as well as a typical limit of 750 °C for the growth temperature.^31,57 Recently, an exceptionally high growth rate of 7 nm/min has been reported for the (010) surface at a growth temperature of 700 °C.⁵⁸ A catalytic growth mechanism that is based on the easy oxidation of a co-supplied catalyst vapor (i.e., In⁵⁹ or Sn⁶⁰), and subsequent thermodynamically driven exchange of the catalyst metal ion by Ga, has been identified in heteroepitaxy and has been termed metal-exchange catalysis⁵⁹ (MEXCAT) or metal–oxide catalyzed epitaxy (MOCATAXY).⁶¹ In its In-mediated variety, this mechanism has been demonstrated to enable significantly higher growth rates and temperatures than conventional MBE for the (010), (001), (⁠$2̄$01), and (100) orientations,^45,48,62 e.g., 1.5 nm/min (100)⁶² or 5 nm/min (010)⁴⁸ at temperatures up to 950 °C. Significantly higher growth rates of 25 nm/min have recently been reported for the homoepitaxy on (010) oriented substrates by suboxide-MBE (S-MBE), i.e., providing Ga₂O instead of Ga from the source, at growth temperatures as low as 550 °C.⁶³ Despite the low growth temperature, the layers had a high structural quality, which may be related to the simpler one-step growth kinetics involving just the oxidation of the supplied suboxide on the substrate. The high suboxide fluxes, required for this growth rate, are realized by a mixed Ga + Ga₂O₃ charge in the effusion cell and exceed the Ga flux from a pure Ga or Ga₂O₃ charge significantly at given cell temperature.⁶⁴ 

n-type doping has been successfully demonstrated for conventional MBE^31,57 and MOCATAXY.⁴⁸ To prove suitable for the growth of thick layers used in vertical devices, higher growth rates in MEXCAT-MBE/MOCATAXY, e.g., by scaling up the fluxes, or successful donor doping with high electron mobilities in S-MBE needs to be demonstrated.

When it comes to power electronics devices, well-defined donor concentrations are required that should be uncompensated to achieve high electron mobilities. Drift regions of vertical devices are most demanding in this respect as they require particularly low donor concentrations. These requirements translate into the need of a good control on intentional doping with simultaneous absence of unintentional doping.

Intentional donor doping of MBE-grown β-Ga₂O₃ has been demonstrated with Sn, Ge, and Si but comes with related challenges, summarized in Table III. Figure 9 summarizes published data on the Hall electron mobility as a function of Hall electron concentration categorized by dopant and flavor of MBE in comparison to the highest published mobilities from Si-doped MOCVD/MOVPE-grown films as well as the empirical mobility limit based on the highest measured Hall electron mobilities in β-Ga₂O₃.

Sn doping can be quite well controlled using the Sn or SnO₂ source material and covers the widest range of electron concentrations, but the mobilities are consistently below the empirical mobility limit, likely related to the large donor activation energy.⁴⁶ Dopant segregation, in agreement with the metal-exchange catalyzing effect of Sn,⁶⁰ compromises the controllability under standard MBE conditions but can be avoided using Sn-doping during In-catalyzed MOCATAXY at elevated growth temperature, which results in similar electron mobilities to that of standard MBE.⁴⁶ In comparison, Ge doping seems to produce higher electron mobilities, but the incorporation of the dopant was found to be strongly depending on the MBE growth conditions, compromising the controllability.⁴⁹ The highest reported electron mobilities were realized by Si-doped, MOCVD/MOVPE-grown films, suggesting Si to be the electronically best suited donor cation. The control of Si-doping in oxide MBE, however, is challenged by source oxidation resulting in drift of the Si flux, which is why only delta-doped layers have been reported historically.⁵⁰ Their electron mobilities exceed those of homogeneously doped films since the electron wavefunction spreads out into donor-free film regions, resulting in significantly decreased ionized impurity scattering. More recently, AFRL has demonstrated Si-doped homoepitaxy.⁶⁹ To complicate doping with Si, it has been found to be mediated by the formation and evaporation of the suboxide SiO instead of elemental Si from the source, resulting in a dopant flux that depends on the background oxygen pressure rather than the cell temperature.⁷⁰ Table IV can be referenced for a qualitative summary of the pros and cons of dopant type.

Unintentional doping by variety of sources has been reported for MBE-grown films. In particular, unintentional Si-doping has been identified to severely limit the lowest achievable donor concentration in MBE-growth films, possibly explaining why electron concentrations in MBE-grown layers significantly exceed the lowest one reported for an unintentionally doped MOCVD grown layer⁶⁶ [indicated as “unintentionally doped (UID)” in Fig. 9]. SiO bypassing the cell shutter of the Si source⁷¹ and Si species from the quartz cavity of the oxygen plasma source^71,72 were identified as primary sources of unintentional Si. Si accumulation at the substrate/film interface may also arise from the typically performed oxygen plasma-treatment before growth or from contaminations on the substrate surface but can be mitigated by Ga-polishing prior to growth⁵³ or intentional doping by the deep acceptor Fe.⁷³ Moreover, unintentional incorporation of N as a compensating acceptor has been associated with the use of a plasma-source⁷² but also enabled the formation of a normally off MOSFET. Another source of unintentional acceptors are the Fe-doped, semi-insulating substrates that lead to Fe segregation during MBE growth by riding the growth front.⁷⁴ Thick UID buffer layers were found to be essential in improving the performance of FETs by reducing the Fe-concentration near the channel,⁷⁵ and low growth temperatures allow reducing the surface-riding Fe by increasing its incorporation into the layer.⁷⁴ Consequently, the generally larger thickness of layers grown by MOCVD/MOVPE may also explain their often higher electron mobilities.

Future work to improve the control of Si-doping may involve the intentional use of SiO sources realized by mixtures of Si and SiO₂⁶⁴ or the direct use of the SiO source material.⁷⁶ Unintentional N and Si-doping may be further mitigated by the use of O₃ instead of O-plasma sources. The purity of the used source material—especially when oxide sources are used—should always be a concern. Successful doping in S-MBE growth is still to be realized. Intentional doping by deep acceptors may be helpful in the purposeful implementation of normally off devices or semi-insulating layers. Point defects, such as donor-like Ga-interstitials or O-vacancies as well as acceptor-like Ga-vacancies, need to be investigated and may be controlled by purposefully using Ga-rich or O-rich growth conditions. Finally, anion site doping is largely unexplored but may help increase electron mobility by placing the ionized donor on the atom that does not contribute to the conduction band minimum.

Despite the use of homoepitaxy, on some surface orientations, the low symmetry of the monoclinic structure can result in twin formation irrespective of the epitaxial method due to possible double positioning of Ga atoms and island coalescence. Such twins have been reported for the MBE growth on (100)⁷⁷ and (⁠$2̄$01)^45,78 oriented substrates. The incoherent twin boundaries forming upon island coalescence are detrimental to the electrical properties of the layers as they can trap electrons, leading to a drastically decreased electron mobility and doping efficiency.⁷⁹ The growth on (010) and (001) oriented substrates is not affected by this problem and results in layers with high structural quality.⁴⁵ 

As already demonstrated for the growth by MOVPE,⁵⁶ the use of (100)-oriented substrates off-cut into the −c-direction prevents the double positioning and twin formation through consistent nucleation at the (⁠$2̄$01)-type step also in In-mediated MEXCAT-MBE.⁶² 

On (⁠$2̄$01)-oriented substrates, a reduction of the density of twin boundaries by increasing the MBE growth temperature has been reported,⁷⁸ yet the application of a proper offcut for complete removal of such twins remains to be to determined. Heteroepitaxial Ga₂O₃(⁠$2̄$01) films free of rotational domains and with high electrical quality have been successfully grown by low-pressure chemical vapor deposition by virtue of Al₂O₃(001) substrates offcut into the ⟨110⟩ direction,⁸⁰ providing a blueprint for the homoepitaxy of untwinned β-Ga₂O₃(⁠$2̄$01) films.

Horizontal devices benefit from smooth growth surfaces that enable sharp heterointerfaces as well as delta-doping profiles through higher mobilities of the confined electrons due to reduced interface roughness scattering. Irrespective of the epitaxial technique, rough morphologies of the growth surface can arise from island coalescence and facet formation. The former one has been prevented by step-flow growth, demonstrated on (100)-oriented substrates with suitable offcut into the +c/−c direction by MBE,⁸¹ MEXCAT-MBE,⁶² or MOVPE.⁸² Similarly, a slight offcut into the +c/−c has been reported to prevent roughness from island coalescence on (010)-oriented substrates by MBE and MEXCAT-MBE.⁸³ Notwithstanding, surface faceting, typically visible as morphological features (other than monolayer steps) elongated into a particular crystalline in-plane direction, can be generally observed for epitaxial films grown on all but (100)-oriented substrates. In the case of (010) films,⁸⁴ these facets were identified to be (110) and (⁠$1̄$10) oriented, suggesting these orientations to have lower surface free energy than the (010) one. Initial growth experiments on (110)-oriented substrates⁸⁵ revealed surface roughness that could be related to island coalescence or faceting, thus calling for more in-depth growth studies on this orientation.

Future work to optimize surface and interface morphology is needed to enable step flow growth and prevent faceting on all surface orientations other than the (100) one, particularly the (001) and (010).

Low loss power devices for high frequency operation are horizontal devices with high electron mobility and high sheet electron density. Such devices are best realized by modulation-doped field-effect transistors (MODFETs) hosting a two-dimensional electron gas (2DEG) in a quantum well structure, such as that formed at a single heterointerface. The on-resistance of MODFETs depends critically on the maximum sheet electron density in the 2DEG (that can be achieved without parallel conducting channel), which is proportional to the conduction band offset (CBO) between the channel and barrier material. MODFETs have so far been realized by β-Ga₂O₃ channels and pseudomorphically strained (Al_xGa_1−x)₂O₃ barriers with the highest reported 2DEG density of 4.7 × 10¹² cm⁻² at an effective mobility of 150 cm²/V s for a barrier with Al content of x = 17% grown on (010) oriented β-Ga₂O₃ wafers.⁷³ Increasing the Al content x has been experimentally⁸⁶ and theoretically⁸⁷ shown to increase the CBO between β-Ga₂O₃ and β-(Al_xGa_1−x)₂O₃ but x has so far been practically limited by phase separation or strain relaxation to values below 20% on (010) oriented substrates.⁵² 

Harnessing the anisotropy of the β-Ga₂O₃ crystal structure and related properties provides a huge potential for increasing the CBO: For example, (100) oriented β-(Al_xGa_1−x)₂O₃/Ga₂O₃ structures have been predicted by theory to have a higher CBO⁸⁸ and sustain a higher critical thickness for layer cracking⁸⁹ than differently oriented ones at the same x. In addition, reports on MBE grown (Al_0.61Ga_0.39)₂O₃(100) layers⁹⁰ and MOCVD grown (Al_0.48Ga_0.52)₂O₃(⁠$2̄$01) layer⁸⁶ suggest that appropriate growth conditions can stabilize high Al-contents. A further increase in the CBO can be achieved by using an (In_xGa_1−x)₂O₃ channel layer whose conduction band minimum is theoretically predicted to be below that of Ga₂O₃ but whose lower bandgap⁹¹ likely comes with a decreased breakdown field. Finally, the use of double heterostructures with the channel layer sandwiched between two barrier layers allows us to increase the 2DEG density above that achievable by single heterostructures.⁵⁴ In situ growth of dielectric layers for MOSFET applications has not yet been explored.

MBE has undoubtedly pioneered β-Ga₂O₃-related power devices and may keep doing so by using its versatility. For example, the simple chemistry, involving only cations and oxygen, enables the uncomplicated exploration of new dopants, and the general ability to grow crystalline and amorphous layers enables the exploration of dielectrics for all-MBE-grown device stacks. To date, however, MOCVD/MOVPE has caught up overcoming MBE in terms of growth rate and purity, leaving the domain of lateral devices based on heterostructures requiring high precision on the layer thickness for MBE. To gain relevance for vertical devices and the related thick β-Ga₂O₃ layers, effective doping in suboxide MBE and further increased growth rates in MEXCAT-MBE/MOCATAXY would have to be demonstrated. The doping control, particularly that of Si, and the removal of unintentional dopants need to be improved. Based on the still limited number of growth studies, the optimum wafer orientation for epitaxy depends on the target application; (010) yielding the highest growth rates is preferable for (thick) vertical devices, but (001), available as large area substrates, can achieve similarly high growth rates in MEXCAT-MBE, and (100) offcut toward [00$1̄$] is theoretically superior for lateral heterostructure devices calling for further exploration.

Sriram Krishnamoorthy

Rapid advances have been made over the last few years in metal organic vapor phase epitaxy (MOVPE) homoepitaxial growth of β-Ga₂O₃ and β-(Al_xGa_1−x)₂O₃, clearly establishing the promise of the MOVPE growth technique for high performance lateral and vertical power device applications. Growth rates [(010) orientation unless otherwise specified] up to 10 µm/h,⁹² unintentional doping as low as 7.4 × 10¹⁵ cm⁻³ with a room temperature mobility of 176 cm²/V s,⁶⁶ low temperature (46 K) electron mobility exceeding 10⁴ cm²/V s,⁹³ low 10¹⁴ cm⁻³ free carrier concentration using N₂O as the oxygen precursor,⁹⁴ low temperature epitaxy with an unintentional electron concentration of 2 × 10¹⁶ cm⁻³ and a room temperature mobility of 186 cm²/V s,⁹⁵ record high electron mobility of 194 cm²/V s at an electron concentration of 8 × 10¹⁵ cm⁻³,⁶⁷ and low point defect concentrations in MOVPE-grown β-Ga₂O₃⁹⁶ have already been demonstrated. Finally, a high Hall mobility of 153 cm²/V s has been measured for the (100) orientation at a carrier concentration of 1.4 × 10¹⁷ cm⁻³, achieved via control of twins and stacking faults.⁶⁵ Controlled n-type doping with a wide range of electron concentration (10¹⁶–10²⁰ cm⁻³), with high mobility values compared to other epitaxial techniques, has been reported in homoepitaxial (010)-oriented β-Ga₂O₃ by several groups. Despite the significant early progress in MOVPE homoepitaxy, the understanding of the growth science toward achieving the ultimate limits of material quality relevant for medium voltage and high voltage vertical devices is still a very open question. In this article, we focus on β-Ga₂O₃ homoepitaxial growth to leverage the availability of bulk substrates. Some of the pertinent research challenges are discussed below.

The choice of the substrate and epilayer orientation could be very important, as the impact ionization parameters could have a dependence on the crystal orientation. Growth along the (100) orientation is particularly challenging due to the observation of independent nucleation of two-dimensional islands causing double positioning on the (100) plane leading to twin lamellae and stacking faults.⁸² In order to prevent the twinning promoted by transformation of (001)-B facets into (⁠$2̄$01) facets,⁵⁶ homoepitaxial growth on the (100) substrate has been shown to favor a 6° miscut toward [00$1̄$]⁸² but has also been demonstrated with as low as 2°.⁹⁷ The offcut angle has been reduced to 2° to conserve material during boule slicing by altering growth conditions to increase the diffusion length on the 100 surface.⁹⁷ Such defect generation has also been observed in homoepitaxial (⁠$2̄$01) β-Ga₂O₃, resulting in severe charge compensation.⁹⁸ It should be noted that (001) and (⁠$2̄$01) orientations offer the largest area substrate (up to 6 in. slabs) available currently,³⁸ but the growth along these orientations are less explored. Vicinal substrates with a specific offcut direction could play an important role in eliminating twin boundaries and achieving superior material quality, including the considerations of the anisotropic diffusion lengths and faceting. A comprehensive understanding of the growth phase diagram and the growth window is still lacking, although preliminary studies indicate a much larger growth window⁹⁵ for β-Ga₂O₃. The growth window could potentially be further expanded using approaches, such as MOCATAXY, which is currently unexplored in MOVPE growth. Epitaxy for vertical power device drift layers necessitates understanding of the growth processes and the evolution of surface morphology at high growth rates while simultaneously maintaining high material quality. Understanding of the high growth rate regime (>5 µm/h growth rate) relevant for vertical devices needs to be explored to understand and control step bunching, step meandering, and other morphological instabilities that could exacerbate growth front roughening. Growth uniformity over a large substrate area needs to be studied. An understanding of the growth processes⁹⁹ is required at the fundamental level via detailed studies of adatom adsorption, desorption, anisotropic diffusion lengths, nucleation processes, and growth velocities on various growth orientations as a function of growth conditions via in situ and ex situ characterization and quantitative kinetic growth modeling approaches.

A vertical power device with high voltage blocking capability requires low-doped drift regions. Vertical devices with high blocking voltage necessitate a high electron mobility drift layer with controlled ultra-low n-type doping with negligible acceptor compensation, minimized intrinsic defects, and external impurities. The low compensating acceptor concentration (<10¹⁴ cm⁻²) in homoepitaxial (010)-oriented β-Ga₂O₃,¹⁰⁰ even at this early stage of materials development, offers the tantalizing possibility of achieving ultra-low doped (10¹³–10¹⁵ cm⁻³) drift layers suitable for medium voltage applications. At such low doping regimes, it is critical to understand and control intentional and unintentional impurity incorporation. Currently, the unintentional doping appears to be limited by unintentional silicon incorporation.⁶⁷ However, detailed understanding of impurities and impurity incorporation is not available. The role of carbon that could incorporate from the metal–organic source is yet to be understood experimentally. The origin and the limits of unintentional donors and compensating acceptors needs to be thoroughly understood. The ultimate low-doping concentration that can be achieved will be eventually limited by the lowest possible concentration of compensating acceptors. Material purity is expected to be a strong function of the growth regime and the choice of gallium and oxygen precursors. The very low concentration regime relevant to the evaluation of material purity necessitates innovative characterization techniques.

Silicon has showed promising performance as a donor, and the other donor candidates, such as Ge, Sn, Zr, and Hf, are less explored in the context of MOVPE growth. The effect of growth conditions and precursors (metal–organic precursors vs gas sources) on dopant incorporation, segregation, and dopant substitution in crystallographically distinct sites remain to be studied in detail. While achieving appreciable hole concentration and hole conduction is an open challenge, the detailed study of Mg-doped,¹⁰¹ Fe-doped, and N-doped Ga₂O₃ epitaxial layers can enable controlled energy barriers in device structures for electric field management and current blocking capabilities. The interplay between doping and point defects remain to be explored in a comprehensive manner. It is furthermore critically important to study the doped drift layer material under high electric fields and high temperatures to understand defect formation, annihilation, and defect transport under extreme conditions.

The ability to form heterostructures in the (Al,Ga,In)₂O₃ material system sets it apart from other (U)WBG materials, such as SiC and diamond. β-(Al_xGa_1−x)₂O₃ with Al content x upto ∼26%–27% has also been demonstrated in the (010) orientation.¹⁰² A high aluminum concentration up to 52% has been reported in the case of the growth of (100)-oriented AGO,⁸⁶ with a band offset as high as 1.2 eV at the AGO/GO interface.⁸⁶ Degenerate doping of (Al_0.26Ga_0.74)₂O₃ with a resistivity as low as 2.6 mΩ cm¹⁰³ is comparable or better than the lowest resistivity achieved in ultrawide bandgap semiconductors with similar bandgap (Al_0.7Ga_0.3N).¹⁰⁴ Furthermore, delta doping with electron concentration in the range of 2–8 × 10¹² cm⁻² with a sharp apparent charge profile enabled by low temperature epitaxy and AGO/GO heterostructure channels with a room temperature sheet resistance as low as 5.3 kΩ/□ including contribution from a parallel channel in AGO has been reported.¹⁰⁵ To realize the predicted high electron mobility 2DEG channels,¹⁰⁶ it is important to achieve high quality AGO/GO heterojunctions with highest band offsets that can enable confinement of >5 × 10¹² cm⁻³ 2DEGs, which requires maximized aluminum content in the barrier. Transport properties, phase purity, and defects in films with aluminum content more than 26% have not been studied yet. Uniform doping and delta doping control in AGO, segregation of dopants, activation energy of dopants and modulation efficiency in AGO/GO heterostructures needs to be explored thoroughly to investigate the potential and limitations of GO 2DEG channels. In addition to crystalline heterojunctions, in situ MOCVD-grown dielectrics¹⁰⁷ can potentially offer the superior dielectric/β-Ga₂O₃ interface with a low density of interface trap states.

The advances in the MOVPE homoepitaxial growth of high-quality thin films and heterostructures are very impressive, considering that the efforts are fairly recent. The highest electron mobility achieved in epitaxial films, the outstanding low temperature mobility, and the low concentration of extracted compensating acceptors make MOVPE a very attractive epitaxial technique for future high-performance devices. Although early strides are being made, a comprehensive understanding of the growth phase diagram is yet to be undertaken. With the extensive exploration of the growth science and understanding of the limits of material purity and doping control, MOVPE can enable a scalable pathway toward high performance lateral and vertical diodes and transistors.

Kevin Leedy

The epitaxial growth methods of MBE and MOCVD have attracted significant interest in β-Ga₂O₃ research as discussed previously. Both techniques have yielded films with a wide range of doping control and the added benefit of being commonplace equipment sets in commercial device foundries. They are not without their limitations, however, including high deposition temperatures, slow deposition rates, and high capital equipment expense. Additional growth techniques, such as halide vapor phase epitaxy (HVPE), low pressure chemical vapor deposition (LPCVD), mist chemical vapor deposition (Mist-CVD), and pulsed laser deposition (PLD), have generated comparable epitaxial film results with compelling benefits including low deposition temperatures, large carrier concentration ranges, wide range of alloying, high deposition rates, and relatively inexpensive equipment. Although significant progress has been made in demonstrating initial epitaxial films from these deposition techniques, overall epitaxial film development remains at an early stage.

An increased understanding of epitaxial growth parameters and control of film properties is required to yield the high-quality films necessary to realize the full potential of β-Ga₂O₃ in commercial semiconductor devices. In addition, sustained implementation of consistent and high-quality material in devices is lacking. An overarching goal is to achieve control of active carrier density with maximized electron mobility. Additional key obstacles to overcome in epitaxial growth include growth rate and alloy and phase control. Driven by β-Ga₂O₃ native substrate availability with increasing substrate diameters, homoepitaxial β-Ga₂O₃ film growth has attracted the most interest associated with lowest defect densities. Indeed, homoepitaxial growth is crucial to capitalize on the superior crystal quality only achieved through growth on native substrates. Concomitant development of native substrates, including comprehensive analyses of growth surfaces, subsurface damage, cleave planes, and impurities, is essential to enable further improvements in film quality. Although a major emphasis is placed on β-Ga₂O₃ homoepitaxial film growth, heteroepitaxial β-Ga₂O₃ films and other Ga₂O₃ phases have high value and must also be thoroughly investigated to fully exploit the benefits of Ga₂O₃.

For vertical device power applications requiring thick and unintentionally doped (UID) β-Ga₂O₃ drift layers, HVPE produces some of the highest quality epitaxial films.¹⁰⁸ Low H and C impurity incorporation translates to excellent UID films. HVPE is particularly notable for fast growth rates >20 μm/h enabling thick films.^5,109 Commercially available HVPE films on 100 mm diameter substrates are available. Schottky barrier diodes were produced with 12 μm β-Ga₂O₃ capitalizing on the high material purity.³⁰ As shown in Fig. 10, films with 10¹⁵ cm⁻³ carriers have been fabricated and more recent efforts have also achieved a doping range up to 10¹⁹ cm⁻³.^5,109,110 Heteroepitaxy and growth of multiple Ga₂O₃ phases have also been demonstrated.¹⁰⁹ 

Challenges to be addressed in HVPE include high film surface roughness requiring post-deposition chemical–mechanical processing and high deposition temperatures which could allow unintentional diffusion of species between the film and substrate. HVPE also has significant issues with doping and thickness uniformity. As HVPE β-Ga₂O₃ is a Cl-based growth process, the potential incorporation of Cl in films must be considered. Prior to successful deposition, substrates require a suitably controlled miscut and have minimal subsurface damage.¹⁰⁹ Improvements in substrate chemical–mechanical polishing are likely required to achieve consistent epi-ready surfaces. In addition, HVPE is performed in custom equipment and hence requires further development to establish a multi-wafer and repeatable commercial deposition process. Low thickness uniformity across the substrate diameter is a known issue that could be addressed with improved injector nozzle designs. Finally, more widespread studies of film growth, and device integration, are vital to fully demonstrate the potential of HVPE.

LPCVD has intriguing potential to substantially impact the β-Ga₂O₃ power device community by capitalizing on several key features. First, LPCVD utilizes a simple and relatively inexpensive equipment configuration that is well understood and adopted in commercial batch reactor semiconductor device fabrication facilities. Second, LPCVD exhibits fast and tunable growth rates up to 35 μm/h although at the expense of higher rms surface roughness (3–5 nm) achieved with other epitaxial growth techniques.^5,115 The higher growth rates are conducive to fabrication of thicker films necessary for drift layers in vertical devices; Schottky barrier diodes have been demonstrated.⁵ Finally, homoepitaxial films and heteroepitaxial films on sapphire have been fabricated with Si doping to achieve carrier concentrations up to 10¹⁹ cm⁻³, as shown in Fig. 10.^5,80,112 For unintentional doped films, a homoepitaxial film with a high Hall mobility of 156 cm²/V s and 3 × 10¹⁶ cm⁻³ concentration compares quite favorably with the results from HVPE and trails only MOCVD data for the highest recorded mobility to date.¹¹² 

Challenges for LPCVD are focused on films with high film surface roughness, which may necessitate chemical–mechanical polishing prior to device fabrication, and high deposition temperatures up to 1050 °C, which may exacerbate elemental diffusion, both similar to HVPE limitations. However, the high surface roughness in ∼10 μm thick films fabricated by LPCVD and HVPE may also be expected from any deposition technique capable of producing these thicknesses. Since the overwhelming majority of β-Ga₂O₃ LPCVD results to date comes from one institution, additional studies on epitaxial film growth and properties, as well as device insertion, by others in the research community are vital to validate reproducibility and, thus, more fully realize the benefits of β-Ga₂O₃.

A variant of CVD referred to as mist-CVD has been used to deposit thin films of multiple Ga₂O₃ phases and associated alloys. While the β-Ga₂O₃ phase is the focus for power devices in this Roadmap, most of the published Ga₂O₃ work using mist-CVD centers on heteroepitaxial growth of the metastable α-Ga₂O₃ phase and numerous heterostructures with Al and In on sapphire. Heteroepitaxy studies of α-Ga₂O₃ emphasize the larger bandgap, higher breakdown strength, and utility of inexpensive, similar-lattice sapphire substrates.⁵ The α-Ga₂O₃ films are implemented in commercially available Schottky barrier diodes with a specific on-resistance of 0.1 mΩ cm².¹¹⁶ Transport results from β-Ga₂O₃ homoepitaxial films with an electron concentration range of 10¹⁸–10²⁰ cm⁻³ shown in Fig. 10 demonstrate dopant control in mist-CVD on native substrates.¹¹⁷ The atmospheric pressure, solution-based deposition process is scalable, simple, and of low cost compared to vacuum based epitaxial growth methods.

However, mist-CVD utilizes custom equipment typically associated with a newer deposition process and is far from adaptation as a commercial multi-wafer and substrate-scalable deposition capability, such as MOCVD. Heteroepitaxial growth inherently possesses higher defect densities than homoepitaxial films, the impact of which has not been thoroughly characterized by the community. High impurity concentrations and high growth temperatures are commonly associated with solution-based growth methods, such as mist-CVD.¹¹⁸ Implementation of C-free precursors has addressed contamination issues.⁵ More widespread implementation of mist-CVD is vital to achieve a more thorough understanding of the growth capabilities and film properties and to gain acceptance of the device fabrication industry.

One of the strengths of PLD is the ability to fabricate films under a wide spectrum of deposition conditions, including temperature, pressure, and gas species. Studies have demonstrated n⁺ Si doping,^113,114 as shown in Fig. 10, and Al alloying¹¹⁹ of homoepitaxial β-Ga₂O₃ films at low deposition temperatures <600 °C. Degenerate Si-doped films have been implemented as an ohmic contact regrowth layer in a β-(Al_0.14Ga_0.86)₂O₃/Ga₂O₃ modulation-doped FET achieving an extracted ohmic contact resistance of 1 Ω mm⁵ Heterostructures of β-(Al_xGa_1−x)₂O₃ with x = 0–0.37 were also achieved.¹¹⁹ 

A primary detractor to commercial utilization of the PLD method is limited scaling capabilities due to the laser energy source. As a result, PLD is typically relegated to demonstrating technology capabilities, with other deposition techniques identified that are more suitable for production. Current PLD deficiencies are also predicated on a dearth of experimental studies on doping control, alloying, and low deposition rates. Yet to be demonstrated are low to mid-range impurity doping control in PLD homoepitaxial β-Ga₂O₃ films with appreciable mobilities as already reported from MOCVD and MBE studies. Low deposition rates of 0.2 μm/h are also common with PLD, although the addition of oxygen radicals to an 800 °C deposition process prevented sublimation and the associated low deposition rate, usually observed at such temperatures.^5,119 In the future, a more extensive adaptation and exploitation of PLD capabilities to address homoepitaxial β-Ga₂O₃ film nuances is critical to enable the development of device-quality film solutions. Table V summarizes key β-Ga₂O₃ growth conditions and general limitations of the deposition methods in this section.

The numerous β-Ga₂O₃ epitaxial film studies in recent years have yielded continued improvements in film structural and electrical properties across all epitaxial deposition processes. A thorough fundamental understanding of consistent doping control, specifically translated to reproducible device operation, remains elusive. HVPE, LPCVD, mist-CVD, and PLD collectively are strategically significant epitaxial growth technologies impacting the expanding β-Ga₂O₃ field as they offer unique attributes, including high growth rates, excellent wide range doping capability, and associated high mobilities. However, substantial work remains to better understand the role of defects, incorporation and activation of carriers, substrate crystal orientation, mobility improvement, alloying, and unintentional species diffusion among others in order to optimize films required for fabrication of reliable high-performance devices for any given growth method or substrate orientation. The β-Ga₂O₃ phase has garnered the most interest in epitaxial growth primarily due to the availability of native substrates. Continued investment and technological progress in the development of commercial-scaled deposition equipment and native substrates certainly are principal drivers in this rapidly developing field. Heteroepitaxial film development also merits continued investigations to capitalize on widely available and inexpensive non-native substrates.

Aaron R. Arehart, Adam T. Neal, Shin Mou, Steven A. Ringel

Compared with most contemporary semiconductors, defect characterization of β-Ga₂O₃, specifically the characterization of electrically active defects that contribute deep levels throughout the bandgap, is at an early stage. Quantitative characterization of traps throughout the bandgap of ultrawide bandgap semiconductors (UWBGs) is a challenge, but combinations of techniques, including thermally and optically based deep level transient and optical spectroscopies (DLTS/DLOS) and admittance spectroscopy (AS), enable complete coverage of their large bandgaps. These techniques enable extraordinary trap sensitivity (∼5 orders of magnitude lower than the background doping); quantitative trap energy and concentration analysis for individual defect states; trap characterization of material test structures and devices, including application-optimized diodes and transistors using derivative techniques like constant drain current DLTS/DLOS (CI_D-DLTS/DLOS);¹²⁰ and determination of how these traps impact materials and device characteristics. Additionally, because these methods provide electronic information about each defect type, this information can be used in device simulations to show the impact of specific trap states on leakage current, dynamic on-resistance, threshold voltage instability, linearity, etc. This leads to the development of experimentally informed predictive models to guide device optimization in terms of performance, stability, and reliability.

In terms of current status, a wide range of early β-Ga₂O₃ materials, including bulk crystal substrates and epitaxial layers, have been explored^98,121–123—mostly trying to optimize material quality, assessing baseline trap spectra, identifying the physical sources of traps, and modifying techniques to handle the unique properties of β-Ga₂O₃. Figure 11 shows the trap distributions obtained from a selection of β-Ga₂O₃ materials. It is clear that traps throughout the entire bandgap exist, and several have already been linked with carrier compensation,¹²⁴ deep donors,⁹⁶ and transistor threshold voltage instability,¹²⁵ for example. It is also clear that the total trap concentrations vary by more than 20× between different growth methods and the trap distribution (i.e., dominant traps) vary as well. Getting these levels understood, identified, and mitigated are all critical to successful insertion of β-Ga₂O₃ devices.

Defect control and mitigation are critical for the future of β-Ga₂O₃-based power devices for several reasons. First, multi-kilovolt devices require extremely low doping (low-10¹⁵ cm⁻³ range maximum), with low concentrations of compensating defects, unintentional background dopants, and any other charged defects since any uncontrolled changes in these concentrations will result in an inability to adequately control the doping. Second, even relatively low concentrations of traps in transistors can cause dynamic on-resistance, threshold voltage instability, etc. This is because voltage switching in normal operation forces the quasi-Fermi levels to move through the bandgap within the device. This leads to modulation of trap occupancy; i.e., the Fermi level can swing from below a trap level to above the level, or vice versa, which, in turn, leads to trap emission or capture of charge carriers, and this changes the local charge densities that affect the transistor terminal characteristics in a time-dependent fashion. The standard response by device developers is to derate the transistor, design circuits with much wider margins, and otherwise keep the technology further away from the theoretical limits, thereby reducing the gains from the switch to UWBGs. The third reason that defect control and mitigation are critical is that defect states can lead to leakage currents or reduced mobility if concentrations reach moderate levels or if operating temperatures are sufficient to be in an ionized impurity limited regime. Hence, there is a significant drive to characterize trap by determining their energy levels in the bandgap, their individual concentrations, their physical sources, their physical locations within the device, their connection with materials growth, processing, and device design variables and to develop strategies that eliminate or mitigate each problematic trap.

With the importance of traps established, the current and future challenges become clearer. First, identification of the physical source of each trap is paramount to inform growth optimization. Second, identification of the specific traps responsible for transistor non-idealities (e.g., dynamic on-resistance, threshold voltage shift) is needed to determine the most critical traps upon which to focus. Third is the development of strategies to eliminate or mitigate critical traps created during growth and processing.

Defect studies in MBE, MOCVD, EFG, CZ, and other growth methods are already under investigation^{96,121,123,124,126} but have revealed several current challenges. The E_c − 2.0 eV trap has been shown to be a strong carrier compensation center and potentially ascribed to a 2V_Ga − Ga_i defect complex.¹²⁷ If, indeed, this is a native defect complex, and to date it is typically present even in very high quality (e.g., electron mobility >175 cm²/V s) β-Ga₂O₃ epitaxial layers having doping in the 10¹⁵–10¹⁶ cm⁻³ range,⁹⁶ this already suggests that further defect concentration reduction or mitigation strategies will be needed for controllable background doping at the required low concentrations. Figure 12 shows that the E_c − 0.8 eV Fe-related trap was limiting in early transistors, causing ∼0.3 V threshold voltage (V_T) instability for Si delta-doped MESFETs.¹²⁵ This is problematic for devices grown on Fe-doped substrates if the substrate is too close to the channel or if the surface segregation of Fe during epitaxial growth is not mitigated. Recently, the surface riding issue of Fe is being successfully addressed in ongoing studies by growing an intermediate layer at low temperature to bury the Fe.⁷⁵ However, the nearby trap at E_c −0.7 eV (Fig. 12), for which radiation experiments imply is due to a native point defect,^123,125 caused significantly more V_T instability than the E_c −0.8 eV Fe trap and might be more insidious with respect to its mitigation or removal compared with Fe.¹²² The ∼0.1 eV difference in energy levels for these states with totally different sources within a bandgap of ∼4.8 eV highlights the need for very careful defect state characterization.¹²⁵ The E_c −4.4 eV trap, also found to be a strong compensation center, had been tentatively connected to self-trapped holes in very early studies¹²⁸ but has since been observed to be sensitive to the growth technique, and initial proton radiation studies suggest that this trap may be related to native point defects. Typically, the E_c − 4.4 eV trap concentration is among the highest of all deep states in any sample and is always observed. Confirmation of its source remains a high priority challenge. Many other traps have also been observed and characterized.⁵ A prominent example of a trap that appears to influence carrier transport is the E_c −0.1 eV trap⁹⁸ 131.¹²⁹ This state is observed in Hall Effect measurements and admittance spectroscopy as a deep donor, and in some cases, it has the highest trap concentration in MOCVD-grown epitaxial layers. This defect not only causes unintentional doping in setting the lower limit of the background doping density but also degrades the device performance with its incomplete ionization at around room temperature.¹²⁹ Efforts are under way to identify the sources of all these levels leading toward growth optimization, but we are only touching on the challenges that remain for β-Ga₂O₃ electronics to be successful.

The current state-of-the-art has the best reported mobility values at nearing 200 cm²/V s at room temperature⁶⁷ and around 11 000 cm²/V s at cryogenic temperature.⁹³ While it was estimated by theory that the electron–phonon scattering limited mobility is expected to be 200 cm²/V s at room temperature, the uncertainty of the polar optical phonon (POP) energy convoluted with the ionized impurity scattering caused by defects/dopants makes it nontrivial to decide the upper limit of the mobility value at room temperature experimentally.¹³⁰ It remains to be seen how much mobility improvement we can obtain by eliminating the unwanted defects.

There are numerous long-term challenges for defect characterization that will evolve with the advancement of β-Ga₂O₃ device technology, and its importance will continue to increase. These include continued guiding of growth optimization; characterization of traps in β-(Al_xGa_1−x)₂O₃ having much wider bandgaps than β-Ga₂O₃; understanding and mitigating defect states in UWBG dielectric/AlGaO interfaces; identifying direct linkages between specific traps, device parameters, and reliability; and developing new testing protocols.

From the materials perspective, current challenges will continue that are related to defect identification in β-Ga₂O₃ due to lack of (but improving) consistency from various material sources to suppliers and growth methods. More systematic and correlative defect-growth studies that consider independent variables, including growth temperature, growth regime, choice of precursors, growth rate, and choice of dopant species, while starting to appear, are needed.

(Al_xGa_1−x)₂O₃ is almost completely unexplored in terms of defects but yet is enabling for transistors with high 2DEG concentrations and high mobility and other devices. Interface states, surface states, and bulk traps all need to be explored with techniques that may lack the range to fully characterize traps throughout the exceedingly large bandgaps. MOSFETs and other β-Ga₂O₃ transistors already show great promise, but little has been done to understand how defects in each layer or interface impact device stability (e.g., dynamic R_ON, V_T instability, and g_m changes) and performance (e.g., noise, f_T, f_max, and linearity) to this point. As seen in Ref. 131, traps can impact system level metrics in GaN. So as commercial products ready, this will need to be explored as well.

Another key challenge in the future is the development of qualification methodologies and testing protocols for both materials and devices. Having standard specifications for β-Ga₂O₃ substrates and epilayers that include the full set of properties identified as having high impact on device reliability, stability, and performance, which are beyond the current standards based on methods such as x-ray diffraction (XRD) and secondary ion mass spectroscopy (SIMS), will be needed. For example, device-critical defects, such as atomic vacancies, cannot easily be characterized, especially at their low but non-negligible concentrations. Additionally, extrinsic defects are present at concentrations often below SIMS detection and yet have already been shown to play key roles in device degradation. Fast, simple, and preferably non-contact methods to evaluate native and extrinsic defect concentrations will need to be devised for β-Ga₂O₃ power electronics that have doping in the low 10¹⁵ cm⁻³ range or less. Beyond materials qualifications, device qualification based on random part testing must consider bias, time, and environmental conditions and here would be the last chance to catch any defect or other material or fabrication issues. New protocols, which might include some variant of quantitative defect spectroscopy that are sensitive to defects with the appropriate degree of sensitivity, should significantly improve device uniformity, stability, performance, and yield for the end user.

In this chapter, the roles of defects, characterization methods, and future challenges were discussed. Overall, defect characterization, identification, and mitigation strategies are well under way where significant gains on all these fronts are occurring. However, significant challenges remain, especially in terms of physical source identification for specific traps, defects in the (Al,Ga)₂O₃ alloy system, impacts of traps on transistors, device and circuit parameters, transistor designs that minimize trapping effects, technical improvements to accommodate the even wider bandgaps of (Al,Ga)₂O₃, and development of suitable test methodologies and protocols to monitor traps throughout the material and device supply chain. With the success of this, β-Ga₂O₃ devices will greatly exceed the incumbent technology limitations at very high voltages and, with cost and other improvements, can become the next-generation high-voltage, high-power handling solution.

Avinash Kumar, Ankit Sharma, Krishnendu Ghosh, Uttam Singisetti

It is vital to fully understand the fundamental band and electron transport properties in β-Ga₂O₃ to accurately simulate and predict the device performance in power, RF, and RF switching applications. The low symmetry of the monoclinic β-Ga₂O₃ crystal structure, along with ten-atom unit cell that results in multiple polar phonon modes, provides considerable challenges to the transport calculations using the traditional approaches used for the Si, III-Vs, and III-Ns. However, exploiting the recent advances in the ab initio computation methods, several researchers correctly identified the strong polar optical phonon scattering as the limit to the room temperature low field electron mobility in β-Ga₂O₃.^132–135 Although the presence of 12 IR active polar modes makes the use of simple relaxation time approximation (RTA) for transport calculations imprecise, a good fit to experimental mobility is observed using a LO phonon energy in the range of 40–50 meV (Fig. 13). These transport calculations also provided an estimate of the non-polar deformation potential parameters,¹³⁶ which are very difficult to measure or estimate in early stages of materials development. The low field transport calculations have been validated by direct experimental measurements of the scattering times using pump–probe experiments.¹³⁷ 

The experimental room temperature mobilities (∼200 cm²/V s) have approached the theoretically calculated values. Moreover, the electronic band parameters of β-(Al_xGa_1−x)₂O₃ (AlGaO) alloys and β-(Al_xGa_1−x)₂O₃/Ga₂O₃ heterostructures were computed theoretically^87,88 and validated by experiments. The success in predicting the fundamental band and transport properties makes the ab initio based approach an indispensable tool. Additionally, high field transport in bulk β-Ga₂O₃ has also been explored, providing the saturation velocity which is an important parameter for RF devices. Despite the tremendous progress described here, there are still several challenges that we discuss below.

Even though the POP limited electron mobility is high enough in β-Ga₂O₃, both RF and power devices will benefit from increased mobility. In SiC power devices, reduced field effect channel mobility plays a major role in the device design and considerable research is dedicated to increase this mobility. Similarly, increased channel mobility will help in β-Ga₂O₃ power device performance.

For RF devices, the low field mobility will determine the effective channel velocity and hence the high frequency performance. Using heterostructures to form two-dimensional electron gas (2DEG) is an attractive way to enhance the mobility. Recent work suggests (Fig. 14) the role of plasmon–phonon coupling and dynamic screening to enhance the mobility.¹⁰⁶ Both roughness scattering and remote impurity scattering were observed to impact the mobility. Using a relatively lower Al composition AlGaO barrier layer, the authors predict that the mobility could be increased to more than twice that of bulk β-Ga₂O₃ at a 2DEG density of 5 × 10¹² cm⁻². However, the primary challenge is to achieve such high 2DEG densities with no parallel channel formation and thick enough spacer layers. The whole design space for AlGaO/β-Ga₂O₃ heterostructures has not been fully explored. It will be interesting to see how the mobility changes with even higher 2DEG densities where inter-sub-band scattering can be expected play a significant role. The accuracy of these calculations can be improved using mode-resolved non-polar scattering rates. The damping of the plasmon–phonon modes can also impact the mobility, which needs to be incorporated in the calculations. All the calculations to date have assumed an equilibrium phonon distribution. Coupled electron and phonon calculations can provide more insights into the ultimate limits to mobility. The high field velocity-field profile in AlGaO/Ga₂O₃ is not explored. It would be very informative to see if the plasmon–phonon coupling and dynamic screening have any role in the high field transport behavior.

As described previously, achieving high 2DEG density could potentially enhance the mobility in AlGaO/Ga₂O₃ heterostructures. Growth of high composition AlGaO layers will greatly help in achieving high 2DEG densities as the larger conduction band offsets will confine the 2DEG. Hence, understanding and control of AlGaO electronic properties is an important area. Peelaers and Mu et al. investigated the electronic band properties of AlGaO alloy layers from first-principles calculations.^87,88 These calculations show that the band alignment between AlGaO and Ga₂O₃ has a staggered line up (Type II alignment), which helps in the increasing the confinement of 2DEG in heterostructures. They also predict that at 50% Al composition, the AlGaO should be an ordered alloy; an ordered alloy will not have any alloy fluctuation scattering that could enhance 2DEG’s mobility. The conduction band offset in AlGaO/Ga₂O₃ heterostructures was found to be dependent on the orientation with highest offset in the (100) direction. The calculated band line up was validated recently by experiments.^86,138 It is predicted that the monoclinic phase is energetically favorable over the corundum phase up to 70% Al composition. This should not be an obstacle for high 2DEG density designs as at 70% AlGaO, the conduction band offset is sufficiently high. A rather more difficult challenge is the ability to dope the AlGaO layers that are the source of electrons in the 2DEG. Ab initio based calculation of the energetics of potential shallow dopants in AlGaO will provide valuable knowledge to both growers and device engineers. The random nature of alloy and the need to use large size supercells in these calculations provide considerable computational challenges. Additionally, the energetics of defects, defect-dopant complexes in AlGaO, and doping compensation needs to be explored.

Several groups have demonstrated the high critical field strength of β-Ga₂O₃ experimentally and the community has generally accepted the empirically extrapolated 8 MV/cm as the critical field strength in β-Ga₂O₃. However, the critical field strength has not been quantitatively determined either by theoretical calculations or measured experimentally using current multiplication in p–n diodes due to the absence of p-doping. The theoretical calculations suffer from the computational complexity arising from the multiple closely spaced valence bands in β-Ga₂O₃. Assuming a single representative flat valence band, Ghosh et al. used ab initio based scattering rates coupled with Monte Carlo simulations to obtain the ionization coefficients of electrons.¹³⁹ An interesting observation in this study is the predicted large anisotropy in the ionization coefficient of electrons (Fig. 15).

The calculated anisotropy is more than the calculated anisotropy in either mobility or saturation velocity. The calculated ionization coefficients provide first quantitative parameters for evaluating the theoretical limits of the field strength. However, the hole ionization coefficients are not calculated. The problem is further complicated by the self-trapping nature of holes, which suggest a completely new mechanism for breakdown. However, recently the hole mobility was estimated from ab initio calculations ignoring the self-trapping effect.¹³³ It will be informative to estimate the hole ionization coefficient even if the likelihood of finding a shallow acceptor is low.

In summary, ab initio based calculations have provided deep insights into the fundamental band and transport properties of β-Ga₂O₃ and related alloys. Experimental validation of the calculated parameters further emphasizes the importance of these studies. However, there are still significant knowledge gaps both in the transport and band properties of β-Ga₂O₃ and AlGaO alloys. Sustained research along with experiments will provide significant boost to the transition of β-Ga₂O₃ from academic laboratories to real world applications.

Wenshen Li

Owning to the inherently fast switching speed and low on-state voltage drop (V_ON), Schottky barrier diodes (SBDs) are indispensable for high efficiency power conversions. Since the device structure is relatively simple, vertical β-Ga₂O₃ SBD is likely among the first device types to enter commercialization, similar to SiC. The past few years have witnessed fast-paced development of β-Ga₂O₃ SBDs. High breakdown voltage up to ∼3000 V,^140,141 a Baliga’s figure-of-merit (FOM) of close to 1 GW/cm² while simultaneously maintaining a low leakage current,¹⁴¹ a high current carrying capability of over 100 A,¹⁴² high temperature operation at 500 °C,¹⁴³ fast switching,¹⁴⁴ as well as near ideal I–V characteristics under both forward and reverse bias have all been demonstrated.¹⁴⁵ 

These achievements certainly benefit from the excellent quality of β-Ga₂O₃ epitaxial layers and substrates, which exhibit not only low dislocation density <10⁴ cm⁻² but also no clear correlations between dislocations and leakage current.¹⁴⁶ In addition, early studies of barrier height¹⁴⁷ as well as ohmic contact process provide important underpinning. However, realization of on-state voltage drop and soft breakdown voltage that are comparable to or exceed those of commercial SiC power SBDs have not been demonstrated yet.

Structurally, both the trench-MOS SBD¹⁴¹ and junction-barrier Schottky (JBS)¹⁴⁸ structures have been realized for the reduction of the reverse leakage current via the reduced surface field (RESURF) effect. In particular, realization of the JBS structure made use of the p-NiO/β-Ga₂O₃ p–n heterojunction, which maybe one of the more promising options for the realization of p–n junctions needed for electric-field management.

To address the field crowding at the anode edge, various types of edge termination methods have been explored, including field plating,¹⁴⁹ implanted terminations,¹⁴⁴ junction termination extension (JTE)-like,¹⁵⁰ deeply etched mesa,¹⁴⁵ and floating metal guard rings.¹⁵¹ However, reliable soft breakdown and ideal reverse leakage have not yet been consistently achieved.

Before discussing the challenges of β-Ga₂O₃ SBDs, we first evaluate the limit of their conduction loss. For an optimum conduction loss under a given voltage rating or breakdown voltage (BV), one should minimize V_on under a given on-current density (J_ON). This is equivalent to minimizing the specific SBD on-resistance (R_on,SBD = V_on/J_on) under a given on-current density (J_ON), as given approximately by¹⁵² 

Here, E_surf is the surface electric field at BV, Ø_B is the barrier height in volts, μ is the electron mobility, ɛ_s is the dielectric constant of β-Ga₂O₃, and $R$ is the RESURF factor, which equals to unity for regular SBDs.¹⁵² Note that R_on,SBD includes the effect of the junction voltage drop (∼Ø_B/J_ON) and, thus, is different from the differential on-resistance typically used for benchmarking according to the Baliga’s FOM. Distinct from p–n diodes, the maximum E_surf in SBDs is typically limited by the reverse leakage current due to barrier tunneling and, thus, is lower than the critical electric field. By using the standard breakdown criteria of a maximum reverse leakage current (J_R,max) of 1 or 100 mA/cm², we have previously established quantitative relationships between the maximum E_surf and the barrier height in β-Ga₂O₃ SBDs,¹⁴⁵ as shown in Fig. 16. With the maximum E_surf as a function of Ø_B, R_on,SBD in Eq. (1) can be minimized by solving for the optimum Ø_B under a given BV and J_ON.

Figure 17(a) shows the calculated R_on,SBD limit as a function of BV in regular β-Ga₂O₃ SBDs under J_ON = 100 A/cm². The physical parameters used in the calculation are listed in Fig. 17(b). It can be clearly seen that the effect of the junction voltage drop (∼Ø_B) renders the R_on,SBD limit much higher than the unipolar limit, which only includes the resistive voltage drop across the drift layer, especially when BV is low.

Also shown as comparisons are the R_on,SBD limits of regular SiC and GaN SBDs. It can be seen that under the low voltage range (<100 V), there are negligible differences between these three materials. Between 100 and 2000 V, where wide-bandgap SBD market primarily resides, regular β-Ga₂O₃ SBDs have slightly higher R_on,SBD than SiC and GaN counterparts due to the lower mobility, but the difference is very small. It is worth noting that within this voltage range, the maximum E_surf in β-Ga₂O₃ SBDs under the optimum Ø_B is lower than 3 MV/cm, rendering the advantage of its high unipolar limit (Baliga’s FOM) not present in regular SBDs. In fact, this emphasizes that the major motivation for β-Ga₂O₃ based SBDs is the significant cost reduction due to scalable bulk substrates decreasing manufacturing cost as discussed in the first chapter.

Based on these results, two main strategies for β-Ga₂O₃ SBDs arise. To offset the slight disadvantage in mobility, β-Ga₂O₃ SBDs can be operated under a smaller J_ON, rendering a V_ON = J_ONR_on,SBD smaller than that of GaN and SiC SBDs. This is equivalent to enlarging the device area/chip size. Of course, the switching loss would increase due to the increase of the overall capacitance. Future studies are required to quantify the exact trade-off relationship between switching loss and conduction loss for the optimum design space. Other than being simple and straight-forward, this method also alleviates the burden on thermal engineering while taking advantage of the projected low-cost device platform.

Alternatively, one can utilize the aforementioned RESURF effect in advanced devices structures to lower R_on,SBD. With RESURF, E_surf can be smaller than the maximum electric field (E_max) in the drift layer.¹⁵² Consequently, the RESURF factor $R$ in Eq. (1) becomes larger than 1, thereby lowering R_on,SBD. Experimentally, $R∼6$ and E_max = 4.3 MV/cm have been realized in β-Ga₂O₃ trench-MOS SBDs.¹⁴¹ However, the reliability of the dielectric layer under such a high E_max is a serious issue, which needs to be addressed via the development of stronger dielectric materials or p-type shields. It is also possible to replace the MOS structures with metal or oxidized metal contacts if the barrier height is sufficiently high to support a high electric field without excessive leakage current (see Fig. 16). As for JBS structures,¹⁴⁸ it is important to ensure that the p–n heterojunction interface is of high quality such that no interface leakage current and interface charge trapping are present. In addition, the breakdown mechanism of the heterojunctions should be identified. Ideally, repeatable soft breakdown via impact ionization should be realized. This is essentially equivalent to addressing the grand challenge of p-type doping in β-Ga₂O₃.

Other than these two main strategies, it is also of great importance to employ optimized epitaxial specifications (doping concentration, thickness, and drift mobility) such that a non-punch-through design is obtained to minimize the drift layer resistance.¹⁴⁹ In addition, reduction of the substrate resistance via substrate thinning or replacement is also desirable. These methods have been generally lacking in current state-of-the-art SBDs.

No matter what the diode structure is, a robust and effective edge termination is necessary. It is well-known that the electric field at the anode edges could be several times higher than the parallel-plane or one-dimensional electric field in the device bulk if proper edge termination is not implemented. For JBS-like structures, the edge termination may need to support a parallel-plane of ∼4 MV/cm or higher.¹⁵² For regular β-Ga₂O₃ SBDs, the requirement is lessened, as the parallel-plane E_max is only about 2 MV/cm at a voltage rating of 1000 V.

In commercial SiC power SBDs, the edge termination is typically realized by JTE and guard rings. With effective native p-type doping still elusive in β-Ga₂O₃, however, realization of such termination methods would require p–n heterojunctions. Again, it comes down to the challenge of achieving a high quality junction interface. In addition, it would be desirable to have controllability over the doping level of the heteroepitaxial p-type region. Alternative structures such as N, Mg, F implanted termination, deeply etched mesa, field plates, and metal guard rings may also be effective. However, their effective and robustness await further validation.

As discussed previously, there exist optimum barrier heights in both regular SBDs and JBS-like diode structures, depending on the rated breakdown voltage. It can be shown that the optimum Ø_B lies roughly in the range of 0.7–1.4 V for regular SBDs and 0.7–1.1 V for JBS-like structures under a rated BV of <2 kV. While barrier height values above 1 V have been frequently reported and utilized,¹⁴⁷ values below 1 V have not. It should be highlighted that these low barrier heights may be necessary under certain scenarios, and much research attention is required. Thermal, electrical, and chemical stability of the barrier also need to be further established, along with scientific understanding of the pinning/de-pinning mechanisms and the associated crystallographic orientation dependence.

While a wide range of characterization is still required, realization of ultra-high barrier heights for voltage-blocking/electric-field management has made important progress, with up to 2.2–2.4 V demonstrated with oxidized metal contacts.¹⁵³ It remains to be seen, however, whether a barrier height value beyond half of the bandgap can be obtained, as required to support the critical electric field.¹⁴⁵ 

Finally, we briefly discuss the requirements on thermal management pertaining to β-Ga₂O₃ SBDs. Under normal operating condition, at least top-side thermal managements are necessary to alleviate the more severe self-heating effect than SiC SBDs.¹⁵⁴ For surge current ruggedness, more elaborate thermal solutions may be needed, such as double-side cooling via thinned or bonded substrates. As SBDs circulate the research community, it is expected that more rigorous thermal management requirements will be defined.

Due to the additional junction voltage drop, as well as the constraint on the maximum surface electric field due to reverse leakage current, optimization of the conduction loss in β-Ga₂O₃ SBDs is not simply via increasing E_max to reach a high Baliga’s FOM but rather requires multifaceted efforts involving barrier height optimization, structural innovation, and trade-off with switching loss. In this chapter, we summarized two main strategies for β-Ga₂O₃ SBDs to obtain lower power loss than SiC and GaN counterparts: by enlarging the chip size or by employing JBS-like structures. In addition, challenges and requirements on edge termination, barrier height control, and thermal managements are identified. For a successful market penetration, β-Ga₂O₃ SBDs will not only need to be competitive against SiC and GaN SBDs on performance and reliability, but they will need to see significant cost reduction as well. The interplay between these factors must be considered in the future development of β-Ga₂O₃ SBDs.

Grace Xing

All devices can take a lateral or a vertical form or a hybrid topology. Among the two-terminal devices, Schottky barrier diodes (SBDs) and photodetectors (PDs) are two popular ones due to their simplicity and commercialization potentials. While SBDs are thoroughly discussed in Sec. XI, it is worthwhile to note some primary differences between SBDs and PDs in order to appreciate the impact of device topology.

A PD needs to absorb photons first, and then generated mobile carriers can be swept under an electric field toward the electrodes. This electric field can arise from an externally applied voltage or a built-in potential in a junction. For example, employing two different SB junctions in an M–S–M photodetector can lead to non-zero photocurrent at zero external bias, i.e., power- or battery-free operation, similar to a solar-cell. The absorption coefficient of photons with an energy higher than the bandgap of β-Ga₂O₃ is about 10⁵ cm⁻¹ or higher. This implies that a β-Ga₂O₃ layer as thick as a few hundred nanometers is sufficient to absorb >90% of the above-bandgap photons. As a result, the MSM photodetector often adopts a lateral topology with an active layer of hundreds of nanometers thick to maximize photon absorption as well as take advantage of facile fabrication by printing both electrodes on the wafer surface.

On the other hand, a power device with a target voltage rating of >3 kV necessitates a drift layer with a thickness higher than about 5 μm using the single side abrupt junction approximation and a non-punch through device. Considering a vertical SBD with a 5-μm thick drift layer and a lateral SBD with a 1-μm-thick and 5-μm-long drift region, one can readily see that for the same device size on the wafer, the lateral SBDs will deliver an output current only ∼1/5 of the vertical SBDs. In this example, the current density along the current flowing direction is assumed to be the same for thermal and reliability considerations. Similar arguments can be applied to vertical vs lateral transistors; moreover, it is equally important to remember that a fin-shaped channel with sidewall gates is essential to provide efficient gating of a thick FET channel. However, the validity of these arguments starts to diminish and even reverse in high-frequency transistors since the source–drain distance in a lateral finFET optimized for high-frequency operation can become smaller than the thickness of the channel. Based on the above considerations, we limit discussions in this section on power devices employing a vertical topology with an operation frequency <1 GHz, while the RF or high-frequency power devices, often adopting a lateral topology, will be discussed in Sec. XIII.

Other than SBDs, vertical β-Ga₂O₃ devices demonstrated to date are of three types: (1) fin-shaped channel metal–insulator–semiconductor (MIS) field effect transistors (FinFETs),^7,9 also called vertical trench MOSFETs;¹⁵⁵ (2) static induction transistors (SITs)—essentially a short-gate vertical FET—the FinFETs reported in Ref. 156 were discovered to have a gate length of ∼50 nm under transmission electron microscopy, therefore appropriate to rename them as SITs; and (3) current-aperture vertical FETs (CAVETs).^152,157 This landscape is primarily limited by the fact that in β-Ga₂O₃, n-type conduction and semi-insulating properties are readily achieved, while p-type conduction in β-Ga₂O₃ faces fundamental challenges. The community is still searching for p–n heterojunctions that possess a built-in potential higher than 3 eV and enable avalanche in β-Ga₂O₃.

As of today, the experimentally demonstrated BFOM in β-Ga₂O₃ finFETs is 0.31 GW/cm² under pulsed conditions and 0.28 GW/cm² under DC (Figs. 18 and 19).⁹ These values are comparable with the BFOM achieved in state-of-the-art β-Ga₂O₃ SBDs so far; however, they still lag behind those of vertical transistors demonstrated in GaN and SiC.

In any FET, it is essential to employ the most favorable gate structure(s) in that material system. Generally, p–n junction based, metal–semiconductor (M–S), or metal–insulator–semiconductor (MIS) based gates are the three major choices.

A trench SBD and a vertical finFET both feature sidewall MIS-gated fin channels as the core building block. While the electrical performance goals are similar, geometrically they differ due to enhancement mode requirements, gate and channel lengths, and an extra ohmic top contact. Whereas trench SBDs have a Schottky contact, thus having some inherent voltage blocking capability, finFETs have an ohmic contact on top of the fin channel, thus solely relying on the potential barrier induced by the gate for voltage-blocking. As a result, vertical finFETs require a higher aspect ratio (>2) for the fin channel, i.e., a smaller fin width under the same fin height, such that drain induced barrier lowering (DIBL) is not excessive. In practice, finFETs typically have a fin width of <0.5 μm. This alleviates the electric field crowding at the fin bottom corner, which could be an issue in trench SBDs.¹⁵² However, the requirement on edge termination is no different from the case of trench SBDs, as already discussed in the SBD section.

Other than the consideration on DIBL, the design of fin channel geometry also need to weigh in the requirement on the threshold voltage (V_th). This is true for all other vertical transistors as well.

For fail-safe operations, normally off operation or V_th > 0 is desired. In the generally employed n-type doping channels, normally off operation basically relies on the full depletion of the channel charge due to the built-in potential of the gate stack. For MIS or M–S gates, this built-in potential is governed by the gate-metal work-function. As a result, it is difficult to obtain a V_th > 1.5 V, especially when considering the additional voltage drop with the gate dielectric and the channel. For a higher V_th, special work-function engineering is required. Recent observation of the high effective work function in oxidized metal may offer some benefits. Otherwise, p–n junction-based gates will be needed for a higher built-in potential. This again requires a high-quality epitaxial heterojunction interface.

Other than the control of the V_th value, its stability is equally important. For MIS gates, this is only possible with a high-quality dielectric–semiconductor interface. It is far from trivial, as slow trapping/detrapping and the related threshold voltage shifts are frequently observed in β-Ga₂O₃ MOSFETs. For any potentially promising dielectric material, a mapping of the interface states as well as its optimization is required, together with standard stability tests, such as Positive Bias Temperature Instability (PBTI).

As have already been alluded to in the SBD section, the reliability of the dielectric layer in MIS structures under very high electric field is a serious concern. It is well-known that amorphous dielectric materials exhibit time-dependent dielectric breakdown (TDDB) behaviors, which limits the maximum electric field to be well-below the ultimate dielectric breakdown strength for a sufficient device lifetime. Considering the high field operation required for the high power figure-of-merit in β-Ga₂O₃, the dielectric reliability could be a major limiting factor for the efficiency of β-Ga₂O₃ power devices. In vertical β-Ga₂O₃ devices employing MIS structures, this issue could be combated with proper design of p-type shielding, which again requires the development of proper p–n junctions. Without p-type shielding, one would need to develop stronger dielectric materials with high TDDB lifetime under a high electric field—a general grand challenge for all wide-bandgap power devices.

CAVET¹⁵⁸ offers an alternative solution to vertical Ga₂O₃ FETs. It has the advantage of the all-ion implantation based fabrication process and a fully planar surface and, thus, can be manufactured with low cost. Currently demonstrated β-Ga₂O₃ CAVETs show decent on-state performance, but a high breakdown voltage beyond 600 V is yet to be reached.¹⁵⁷ The challenge mainly resides in the voltage-blocking capability of the semi-insulating current blocking layer since it lacks mobile holes and external electrical contacts as in a vertical double-diffused MOSFET (VD-MOSFET) where the current aperture is defined by p-type regions with well-controlled fermi levels. It remains to be seen whether such a layer could provide sufficient voltage-blocking under both steady-state and dynamic operation conditions, without inducing threshold voltage instability and degradation to the on-state performance.

In a semiconductor material system with both mature n-type and p-type doping technologies, the following vertical devices are often also explored: (heterojunction) bipolar junction transistors (BJTs and HBTs), vertical junction FETs (JFETs), vertical double-diffused MOSFETs (VD-MOSFETs), trench MOSFETs, insulated gate bipolar transistors (IGBTs), thyristors, avalanche diodes, etc. By strategically placing the high-quality p–n junction capable of avalanche within the device structure (vertical and/or lateral junctions), it is possible to minimize electric-field crowding and implement RESURF schemes, thus approaching the unipolar limit of the semiconductors. Furthermore, the avalanche capability afforded in high-quality p–n junctions lend these devices the ability to survive surge events. For applications that can live with bipolar carrier-limited switching frequencies, the unipolar limit of a semiconductor is exceeded by employing superjunctions. In Si, CoolMOS is one of the most prominent examples taking advantage of superjunctions, while in SiC and GaN, superjunctions have been actively pursued. High-quality p–n homo- or heterojunctions that enable avalanche in β-Ga₂O₃ will for sure open up a plethora of opportunities for device design, thus application spaces.

Assuming an interface with zero interfacial charges due to defect states and polarization discontinuity, etc., the displacement current near the interface is the same in the two joint materials: ϵ₁E₁ = ϵ₂E₂. We can readily examine how this relationship fares for Si/SiO₂. The critical breakdown field in Si at the low doping limit is 0.3 MV/cm, while that for SiO₂ can be 10 MV/cm or slightly higher depending on the deposition method and thickness of SiO₂. However, a practical field of about 2 MV/cm in SiO₂ is chosen to ensure a higher than 10-year lifetime without serious dielectric degradation. A field of 2 MV/cm in SiO₂ translates to 0.6 MV/cm in Si, which indicates that Si can undergo avalanche before forcing SiO₂ to undertake a dangerously high field, thus an accelerated TDDB. On the other hand, for any semiconductor with a critical field higher than 2 MV/cm, the performance of a MIS structure over time is most likely determined by the insulator. Crucial effort is necessary to develop high-quality MIS structures for all wide bandgap semiconductors. Section XV on ultra-high k dielectrics is an excellent example on this topic. The ultimate choice to unleash the full potential of a wide bandgap semiconductor is its p–n junctions with avalanche capability. After all, the breakdown behavior of a p-n junction is supported collectively by the p-region and the n-region of the wide bandgap semiconductor. In fact, the critical electric field increases with the doping concentration; for instance, in SiC and GaN, the field increases from ∼2.6 MV/cm at a doping concentration of 10¹⁵ cm⁻³ to ∼4 MV/cm at a doping concentration of 10¹⁸ cm⁻³. In summary, the combination of the judicial device design and sufficiently high-quality MIS junctions and/or p–n junctions is key to enable practical and commercializable products based on (ultra)wide bandgap semiconductors, including β-Ga₂O₃.

Kelson Chabak, Kyle Liddy

Lateral β-Ga₂O₃ devices come in multiple topologies with their associated benefits. The simple Schottky junction MESFET²⁷ is a simple structure that can be used to decrease capacitance and increase gain. Inserting an oxide between the gate and channel (MOSFET)²¹ significantly reduces gate leakage. More advanced designs, such as β-(Al_xGa_1−x)₂O₃/Ga₂O₃ heterojunctions (MODFET),⁵³ localize sheet charge for increased transport properties and device gain. It should be noted that all device types are majority carrier devices as shallow acceptors are not currently known and hole transport is negligible due to self-trapping. Lateral β-Ga₂O₃ transistors are ideal for applications that involve switching—power switching, RF switching, and switch-mode power amplifiers designed to operate efficiently between on and off states.²⁵ In contrast to a vertical topology, lateral transistors uniquely offer a small capacitive (gate charge, Q_G) footprint with low on-resistance (R_on) to meet aggressive R_on Q_G targets. The ultimate β-Ga₂O₃ lateral transistor will resemble Si LDMOS with a self-aligned design to the gate and drift region made with ion implantation. Gate length (L_G) scaling can be explored by borrowing III–V epitaxial designs, such as delta-doping to support vertical scaling in pursuit of short-gate β-Ga₂O₃ devices. So far, AFRL has reported the only self-aligned gate-to-source (SAG) β-Ga₂O₃ transistor,¹⁵⁹ while Ohio State University has shown that delta-doping is a viable approach for scaling homoepitaxial lateral β-Ga₂O₃ transistors.¹⁶⁰ These devices are poised for fast-switching power converters with pervasive reach across commercial and military applications to shrink and integrate power conversion at point-of-load. The fast-switching lateral β-Ga₂O₃ transistor application space is niche and will likely require technology development of a pervasive commercial application, such as low-cost (dollars/Amp), high-performance SBDs offering SiC-like performance at a fraction of the SiC cost. In many ways, this resembles the same cycle as GaN RF technology that leaned heavily on the success of commercial GaN LEDs. Otherwise, technology maturation of lateral β-Ga₂O₃ transistors will depend largely on investments by DoD and DoE akin to the DARPA Wide Band Gap Semiconductors (WBGS)-RF program for the GaN-on-SiC RF platform.

β-Ga₂O₃ has relatively low mobility (μ) in exchange for a phenomenal ∼8 MV/cm estimated critical field strength (E_max). It is imperative to operate β-Ga₂O₃ in a high Ecrit regime to realize its high performance predicted by the various power semiconductor figures of merit. The total switching losses in a power switch trade off conduction losses (∼$Emax3$⁠) in the limit of slow switching and dynamic switching losses (∼$Emax2$⁠) for high frequency switching.²⁵ For high Ecrit operation, it is critical to design the β-Ga₂O₃ lateral transistor without source access resistance (R_S) and only enough drift region to match the estimated depletion width calculated from a one-side abrupt junction approximation.

Green et al. first demonstrated high E_max operation in 2016 using a simple lateral β-Ga₂O₃ MOSFET that achieved an average E_max > 3.8 MV/cm and peak E_max > 5.1 MV/cm.²⁰ Multiple high E_max lateral β-Ga₂O₃ transistor results followed in short order achieving 3.9¹⁶¹ and 4 MV/cm.¹⁶² These results are key as they surpassed the theoretical E_max for bulk GaN and SiC while also demonstrating ∼4× Ecrit than modern GaN HEMTs achieve with field plates (∼1 MV/cm). Figure 20 shows representative lateral β-Ga₂O₃ transistor performance from a conduction loss perspective (specific on-resistance, R_on,SP, vs breakdown voltage, V_BK), which consistently surpasses the silicon theoretical limit. Huang’s Unipolar Material FOM (HMFOM), a switch loss FOM from a Q_G perspective, is given by E_max · μ^0.5. Using the latest μ and E_max values reported in the literature, lateral β-Ga₂O₃ transistors have even edged GaN HEMT technology using the HMFOM benchmark (GaN: μ = 2000 cm²/V s, E_max = 1 MV/cm; β-Ga₂O₃: μ = 150 cm²/V s, and E_max = 4 MV/cm). Additional gains will require (1) careful optimization of R_on (higher measured E_max) and (2) epitaxial innovations to increase μ beyond current bulk values. It is important to note that Ecrit matters more than μ for power switching applications.

All high E_max β-Ga₂O₃ transistors listed above achieved this with short gate-to-drain distances compared to GaN and SiC. This feature of high E_max β-Ga₂O₃ is especially unique at lower voltages where the depletion width may be <500 nm. For example, a β-Ga₂O₃ buck converter with 28 V input to power low-voltage logic may require a lateral transistor with V_BK = 90 V breakdown voltage. At V_BK = 90 V and E_max = 8 MV/cm, the β-Ga₂O₃ drift region would be just 220 nm and require electron beam lithography to precisely define. Assuming LG would be equal or less than the drift region, an optimal high-speed lateral β-Ga₂O₃ power switch would require a source–drain distance (L_SD) < 500 nm. For GaN HEMTs, one can achieve a similar L_SD using regrowth and EBL alignment for a T-gate. For GaN, the gate placement can afford to be offset from the source because the channel sheet resistance (R_SH) is <300 Ω/□ in many cases. The opposite is true for β-Ga₂O₃ as R_SH has been typically reported in the realm of 5–10 kΩ/□ because of lower mobility. Even a small slice of β-Ga₂O₃ creates enough access resistance (R_S) to deteriorate the extrinsic transconductance (G_M) for reduced power and RF performance. The highest G_M values reported in the literature remain <50 mS/mm and are mostly limited by R_S from either high contact resistance (R_C) or non-negligible R_SH in the gate–source region. For this reason, a SAG design with implant doping and subtractive refractory metal process appears mandatory for high-speed switching. Achieving n⁺ implanted contacts with R_SH < 100 Ω/□ is a critical aspect of this. So far, low R_SH implant doping is viable and has been reported as low as 96 Ω/□.¹⁶⁴ 

First-order analytical equations illustrate the significance of R_S challenges for β-Ga₂O₃. Assume a rectangular gate structure with capacitive structure defined by ε/τ, with τ defined as the gate oxide thickness and partially depleted channel in series. The intrinsic velocity (v_int) of β-Ga₂O₃ is conservatively estimated as ∼1.1 × 10⁷ cm/s, assuming mid-high impurity doping (though it has been reported as high as ∼2 × 10⁷ cm/s for un-doped β-Ga₂O₃¹⁵⁹).¹⁶⁵ Therefore, an intrinsic transconductance (g_m) can be estimated from v_int · C_G/L_G and an upper bound for G_M can be inferred from an R_S analysis using G_M = g_m · (1 + R_S · g_m) − 1 by varying R_C and R_SH vs gate–source gap (L_GS) for a Ga₂O₃ lateral transistor. The analysis is reasonably close to the optimized device design from Xia et al. that predicts a G_M/C_G ratio with a current gain cutoff frequency (f_T) up to 24 GHz (measured 27 GHz); however, moving the T-gate from L_GS = 1.35 μm to L_GS = 0.5 μm would raise the f_T potential to ∼50 GHz.¹⁶⁶ Likewise, lower f_T samples reported by AFRL were limited by high R_C and L_GS offset. This analysis predicts f_T < 15 GHz and G_M < 35 mS/mm, which resembles most of the measured data without implanted contacts. Figure 21 illustrates the effect of R_C and L_GS on G_M (upper bound) for a representative lateral β-Ga₂O₃ delta-doped MESFET with R_SH = 7.5 kΩ/□ and delta sheet inserted 20 nm below the β-Ga₂O₃ surface. For high R_C = 20 Ω mm, G_M will not surpass 50 mS/mm, regardless of a scaled L_GS design. However, when R_C = 1 Ω mm, a G_M in excess of 100 mS/mm is possible with careful attention to L_GS. Additional gains are possible from L_G reduction that corresponds with proper vertical β-Ga₂O₃ epitaxial designs. Device performance becomes very sensitive to L_GS with an optimized R_C, and a SAG transistor design is likely required.

For lateral Ga₂O₃ power switching, μ matters less than E_max, although any improvements will propel the technology forward and be more appealing to RF applications. Obtaining a high sheet charge density confined in a two-dimensional electron gas (2DEG) with β-Ga₂O₃ will resemble the development of GaAs technology. Homoepitaxial β-Ga₂O₃ layers with a delta-doped sheet charge inserted below the surface have shown high performance just like GaAs MESFETs did early in its development cycle. Xia et al. demonstrated this with a quasi-2DEG μ = 95 cm²/V s.¹⁵⁹ Mobility improvements are expected with a MODFET design using the AlGaO/GaO structure designed like an AlGaAs/GaAs MODFET. Zhang et al. reported a (Al_xGa_1−x)₂/Ga₂O₃ with x = 0.18 MODFET with record high 2DEG electron mobility exceeding 180 cm²/V s.¹⁶⁷ The main challenge presented for MODFETs will be obtaining a large enough conduction band offset to confine a high sheet charge density. Some recent studies have shown progress with x = 0.4 with MOCVD¹⁰² and In-catalyzed MBE growth (MOCATAXY) up to x = 0.2,⁶¹ although delta doping these layers will require further development. Theoretically, Ghosh et al. predicted that room temperature 2DEG mobility in β-Ga₂O₃ could be as high as 500 cm²/V s, which has sparked many groups to explore this topic area.¹³⁶ 

The outlook for β-Ga₂O₃ transistors is promising when it comes to efficient switching and RF applications. The pace will be dictated by the development and commercialization of high-performance β-Ga₂O₃ SBDs. Like prior successful semiconductor technologies (GaAs, GaN), niche applications beyond pervasive ones, such as fast-switch point-of-load power conversion, will leverage commercial interest and require substantial DoD investments. In the meantime, device groups should continue exploring improvements in power and RF figures of merit, with the goal being to apply the most innovative device designs to breakthroughs in materials discoveries. Removing parasitic resistance, applying designs such as SAG combined with implant-doping <100 Ω/□, and patterning these device features with electron beam lithography will produce high-impact device results. Transferring device breakthroughs to vertically scaled epitaxial structures on 3 in. or greater native substrates produced by melt growth will take β-Ga₂O₃ lateral transistors to the next level.

Ahmad Islam

Integration of dielectric on any semiconductor in a MOSFET configuration has always been a challenge. MOSFET waited its commercial introduction in the late 1960s, which was almost five decades after its original inception, as integration of native silicon dioxide (SiO₂) on silicon required the discovery in terms of hydrogen passivation of the SiO₂/Si interface. It is, therefore, not surprising that the newest compound semiconductor β-Ga₂O₃ still does not have an electronic-grade dielectric. MOSCAPs and MOSFETs fabricated using different dielectrics on β-Ga₂O₃ show different degrees of hysteresis in the measured capacitance–voltage (C–V) and current–voltage (I–V) characteristics. The extracted defect densities from such hysteresis suggest a defect density of 10¹¹–10¹³ cm⁻².⁵ These defects mostly lie at the dielectric/semiconductor interface. The energy level of these defects are spread within the bandgap of β-Ga₂O₃ and these energy levels can be probed using the conductance method, Terman method, UV-assisted C–V, deep level transient spectroscopy, deep level optical spectroscopy, etc.

The ultra-wide bandgap of β-Ga₂O₃ limits the choice of dielectrics, which are mainly deposited on β-Ga₂O₃ substrates using atomic layer deposition (ALD) and sputtering.⁵ Although Al₂O₃ is the most popular among the dielectrics, dielectrics like SiO₂ have also been used to take advantage of its higher conduction band offset. Table 25.1 in Ref. 5 lists all the dielectrics that have so far been integrated on β-Ga₂O₃. (Recently, ultrahigh-κ dielectrics have been used to reduce the peak electric field in the gate–drain region. Section XIV discusses this field management idea in more detail.)

A successful dielectric integration requires low defect density. Defects are present at the interface and bulk of a dielectric and their density depends on the surface preparation steps followed before dielectric deposition, deposition temperature, and processing conditions applied after dielectric deposition. To date, negligible defect density has only been reported by depositing dielectrics, such as Al₂O₃, AlSiO, and SiO₂ + Al₂O₃, on β-Ga₂O₃ substrates that has been cleaned with piranha or ozone before dielectric deposition.^163,168,169 Some recent studies where dielectrics were deposited on (010) or (001) β-Ga₂O₃ substrates^168,169 discussed the need for an additional HF treatment for obtaining a small defect density. The universality of these approaches in reducing hysteresis for different dielectrics deposited on different β-Ga₂O₃ substrates and the role of post-dielectric deposition processes in modifying the property of these dielectrics are yet to be explored.

There are generally three requirements for having an electronic-grade integration of dielectric on an ultra-wide bandgap semiconductor like β-Ga₂O₃:

1. The dielectric should have negligible bulk defects.

2. The dielectric/semiconductor interface and the gate/dielectric interface should have negligible interface defects.

3. Both the above interfaces should have large conduction band offsets.

Any dielectric needs to have negligible bulk defects to work as an insulator in a MOS configuration. Defects within the dielectric can cause trap-assisted tunneling and can act as weak spots for inducing dielectric breakdown at voltages lower than the dielectric strength of the material. The main challenge for dielectric integration, however, comes from the requirement of having a good dielectric/semiconductor interface with a defect density of 10¹⁰–10¹¹ cm⁻². Such low defect density will ensure low hysteresis in the C–V and I–V characteristics and enable the device to have sufficient accumulation of electrons underneath the gate. Accumulation of electrons will also require a high conduction band offset at the dielectric/semiconductor interface (ΔE_C,S) to reduce carrier injection into the dielectric [Fig. 22(a)]. This carrier injection from the semiconductor into the dielectric and the movement of these carriers via the conduction band edge states can result in Frenkel–Poole conduction through the dielectric.^170–172 In addition, for interfaces with small ΔE_C,S and for cases when the electric field near the interface reaches 1 V/nm, carrier injection can occur via Fowler–Nordheim tunneling.¹⁷⁰ These conduction mechanisms through the dielectric can weaken the dielectric and eventually cause its breakdown at an electric field, which can be lower than the expected breakdown strength of the dielectric. The use of high κ dielectric having a negative valence band offset^5,172,173 can also result in higher gate leakage under deep-UV illumination.

In addition to the above-mentioned instabilities, defects present at the dielectric/semiconductor interface will reduce the mobility of electrons due to Coulomb scattering. When this interface is rough, which is typically the case for epitaxially grown films on β-Ga₂O₃ substrates,^83,85,174 there will be added concerns from surface roughness scattering affecting carrier mobility. Fermi level pinning is another concern for interfaces having high density of interface defects. Although Fermi-level pinning is routinely studied for the metal/β-Ga₂O₃ interface,¹⁷⁵ its consequence is not well studied for the gate/dielectric and the dielectric/semiconductor interfaces in β-Ga₂O₃ literature.

Along with the on-state device operation requirements discussed above, the off-state device operation (at a negative gate voltage and at a large positive drain voltage) requires the gate/dielectric interface to have a high conduction band offset (ΔE_C,M) to ensure negligible electron injection from the gate toward the dielectric [Fig. 22(b)]. As with the on-state carrier injection discussed above, a smaller band-offset at the gate/dielectric interface can cause breakdown of the dielectric at a lower applied electric field.

Figure 22(c) plots the bandgap (E_g) and ΔE_C,S for different dielectrics deposited on n-doped β-Ga₂O₃ substrates. As expected for any dielectric/semiconductor interfaces, ΔE_C,S reduces with the increase in the relative dielectric constant (ε_r). In addition, dielectrics with higher κ often have a negative valence band offset,^5,172,173 resulting in higher gate leakage under deep-UV illumination. However, these high-κ dielectrics are important for device scaling. Several recent efforts, therefore, have explored the integration of higher κ dielectrics using bilayer dielectrics with SiO₂ or Al₂O₃ as the first layer interfacing with β-Ga₂O₃.^176,177 More research on this aspect will benefit proper integration of these bilayer dielectrics. The data in Fig. 22(c) also show a large spread in E_g and ΔE_c for different dielectrics. This variation is due to the use of different techniques (e.g., REELS, XPS, and some are theoretically calculated; cf. references in Table 25.1 of Ref. 5) used for collecting data on different dielectrics deposited using different methods (ALD and sputter) by different research groups. A recent study¹⁷⁸ has observed variation in measured ΔE_c for the Al₂O₃ dielectric deposited using different methods. This suggests the need for systematic measurements using a single technique for similarly formed dielectrics to comprehend the dielectric dependence of E_g and ΔE_c and to understand their variations, if any, with variations in deposition methods, substrate orientation, annealing/processing conditions, etc.

In addition to the materials requirements discussed above, we will also need to consider the following device processing issues. Electronic-grade integration of single-layer and/or bi-layer dielectrics on β-Ga₂O₃ will require tight control of the quality of dielectric deposition by choosing appropriate dielectric deposition methods and by choosing appropriate process sequences. For example, for ALD, we can control the quality of dielectrics (thus reduce bulk defects within the dielectric) by controlling the dielectric deposition and post-deposition conditions. However, the challenge arises during surface preparation for dielectric deposition (which is required for reducing interface defects at the dielectric/β-Ga₂O₃ interface) and for gate metallization (which is required for reducing interface defects at the gate/dielectric interface). Dielectric deposition with negligible interface defects requires pristine, smooth β-Ga₂O₃ substrates prepared with appropriate surface treatment. However, pristine substrates are also beneficial for forming good contacts with a low contact resistance that needs to go through different processes to reduce contact resistance. This leads to the following two compromising situations between interface quality and contact resistance in a device:

1. We can first deposit a dielectric on a pristine β-Ga₂O₃ substrate and then form contacts by removing the dielectric from the contact areas using a wet or dry process. The contact formation will also involve ion implantation and activation annealing. Such a dielectric-first process will deposit the dielectric on a good surface with low interface defects but may have a higher contact resistance, as contacts are not formed on a pristine surface. In addition, the standard processes needed for reducing contact resistance^179,180 can adversely affect the dielectric and dielectric/semiconductor interface due to crystallization and inter-diffusion of atoms,¹⁸¹ thereby compromising dielectric integration. One can circumvent this challenge by modifying this dielectric-first process into a gate-last process,¹⁸² where one initially protects the dielectric/semiconductor interface with a dummy gate/dielectric stack and later partially or entirely removes the dummy gate/dielectric stack and replaces that with a final stack. The success of a gate-last process might have significant implication toward successful integration of a dielectric on a β-Ga₂O₃ substrate.

2. Alternately, we can form contacts on a pristine β-Ga₂O₃ substrate with appropriate ion implantation, metallization, and activation annealing and then deposit dielectrics and gate metal to complete the device. Such a dielectric-later process has never been used in the semiconductor industry, as it heavily compromises the dielectric/semiconductor interface due to the incorporation of contamination on the semiconductor surface during contact formation. For this case, the presence of contacts on the substrate excludes the possibility of a thorough cleaning of the β-Ga₂O₃ surface using, for example, piranha, which adversely affects the metal contacts and increases the contact resistance. Therefore, resultant devices have dielectrics deposited on a moderately cleaned β-Ga₂O₃ surface and have high interface defects.

An electronic-grade integration of dielectric on β-Ga₂O₃ substrate will allow us to attain high breakdown voltage for β-Ga₂O₃ devices, thereby enhancing the potential of β-Ga₂O₃ in power electronics applications. A good integration will also enable the high frequency operation of devices made with β-Ga₂O₃ as a better dielectric will enable devices to operate with a higher drive current and lower knee voltage. Moreover, the integration of the high-κ gate dielectric with sufficient conduction band offset will enable an increase in gate capacitance and hence increase the operating frequency of the device.

Siddharth Rajan

The high breakdown field of ultra-wide bandgap materials, such as gallium oxide, AlGaN, and diamond, may require new methods for field management for two-terminal diodes and field effect transistors. In the case of gallium oxide, the optimal design to minimize on-resistance losses requires channel sheet charge density. Depleting high channel charge requires high electric fields normal to the channel as well as along the channel transport direction and is expected to be significantly higher than were necessary for AlGaN/GaN high electron mobility transistors.

A figure showing the electric field profiles for a generalized field effect transistor is shown in Fig. 23. The fields normal to the channel and along the channel will lead to a peak field at the drain edge of the gate. In a simple device structure such as this, the Schottky barrier breakdown strength limits the maximum voltage achievable in the device. Assuming an optimally designed device with equal electric fields between directions normal and parallel to the channel¹⁸³ and a maximum breakdown field of F_BR ∼ 8 MV/cm, we find that each of the electric fields would need to be 5.6 MV/cm, and the optimal channel sheet charge density is ∼2.5 × 10¹³ q cm⁻². Since such high fields cannot be sustained by typical Schottky barriers, a gate dielectric becomes critical to achieve optimal device design.

One approach to improve the vertical breakdown strength normal to the channel is to use a high permittivity dielectric as the gate insulator material. Due to electrostatic boundary conditions at the interface, the electric field intensity in the high permittivity dielectric can be significantly lower than in the gallium oxide. This leads to very low electric fields within the dielectric and thereby an increase in the effect barrier width for tunneling from the metal to the semiconductor, as shown in Fig. 24. Experimental work on such interface structures recently showed that parallel plate electric fields of 5.7 MV/cm, with peak fields up to 7 MV/cm, could be sustained by the interface, showing the promise of this approach.¹⁸⁵ 

The uniformity of lateral electric fields along the channel is a key issue. At such high sheet charge densities, the electric field along the channel direction becomes highly non-uniform, with peaks at the gate edge that can greatly exceed the average electric field intensity. In conventional Si power devices, advanced techniques using reduced surface field (RESURF) layers consisting of p-type material were used. Under positive drain bias conditions, depletion of acceptors in the RESURF layer compensates the positive depletion charge in the channel and enables fields along the channel to remain uniform. Since it is currently not possible to envisage such a p-type layer with high breakdown field and mobile charge for the case of gallium oxide, other approaches, such as field plates with dielectrics or semiconductors, can be used. An alternative approach is to use high permittivity dielectrics that could enable uniform field profiles to be achieved along the channel under bias.¹⁸⁴ The dielectric polarization in these layers reduces non-uniformity in the gate–drain region and can therefore increase average electric fields. Figure 25 shows electric field distributions along the channel for structures with and without such a high-permittivity layer. Recently, experimental results have enabled high average electric fields in the gate–drain region for gallium oxide as well as AlGaN, suggesting that this approach could be viable for future device engineering. The theoretical basis for this approach and initial experimental results on gallium oxide have been promising,¹⁶² and lateral electric field strength exceeding 8 MV/cm has been achieved in devices based on AlGaN.¹⁸⁶ Finally, high permittivity materials may also provide a new approach to realize field termination structures for vertical devices.¹⁸⁷ 

Several directions for future research are promising for this direction of research and require a multi-disciplinary effort. The experimental results on integration of high permittivity dielectrics on gallium oxide were achieved using RF sputtering. A detailed investigation of the growth mechanisms, microstructure, and electronic properties, such as breakdown field, and permittivity of these films on gallium oxide by various techniques, would be very useful for device designers. The electronic defects within the films and leakage mechanisms are not well understood, and a detailed study of these is required. The impact of deposition of these films on the properties of the underlying layer is another key issue that requires further study.

Although this technique may apply to many material systems, it looks to be one of the most promising techniques for field management in the absence of a p-type layers in Ga₂O₃. Device engineering for high permittivity/semiconductor structures is at an early stage, and several opportunities exist to develop methodologies to analyze and design lateral and vertical diodes and transistors with high performance. Further analyses will help to understand the trade-offs between breakdown voltage, on-resistance, switching losses, and capacitance. Since many of these devices require detailed two-dimensional electrostatics to fully explain the phenomena, there are opportunities for innovations in device simulation coupled with intuitive analytical models. Finally, there are exciting opportunities for advanced device fabrication techniques for realizing high-performance devices for different voltage and power levels with integration of high permittivity dielectrics.

Samuel Graham, Sukwon Choi, Zhe Cheng

For all electronic devices, managing heat dissipation to limit the channel temperature and improve the component reliability is critical in their design. Such solutions must account for the thermal resistance external to the active device (i.e., at the package- and system-levels) while consideration must be also given to the internal thermal resistances within the device itself. When considering ultrawide bandgap materials such as β-Ga₂O₃, unique challenges arise from the device-level thermal resistance due to the low thermal conductivity of the material. For example, the low and anisotropic thermal conductivity of β-Ga₂O₃ (27.0, 10.9, and 14.7 W/m K in the [010], [100], and [001] crystallographic directions¹⁷⁸ and as low as 3.1 W/m K for β-(Al_xGa_1−x)₂O₃ alloys,¹⁸⁹ respectively) has been used in devices. From previous experiments and modeling, the device thermal resistance of β-Ga₂O₃ lateral transistors were shown to be several times larger than GaN-on-SiC high electron mobility transistors (HEMTs) with a similar device layout.^{11,154,189–193} The low thermal conductivity alone is not the challenge but also the architecture of the devices since thermal resistance is a function of both thermal properties and geometry. Thus, electro-thermal co-design techniques are essential to push the limits of the thermal management of β-Ga₂O₃ electronics. Ultimately, the design of thermal management solutions must be based on electro-thermal device models that can reproduce the temperature-dependent device electrical output characteristics and the self-heating behavior in response to a specified bias condition. Such device model, in turn, relies upon accurate thermal properties of the base materials that are temperature, size, and compositional (e.g., ternary alloy and superlattice) dependent. Next, cooling strategies that locate heat spreaders and efficient conduction pathways in proximity to the device heat generation region will be key to realize an effective thermal management solution. This strategy of implementation of thermal solutions must also not negatively impact device electrical performance. Therefore, modeling, manufacturing, and experimentation will be key in developing thermal management strategies for future devices.

To date, several reports have been published on the thermal management strategies for lateral and vertical β-Ga₂O₃ devices. These include thermal approaches for β-(Al_xGa_1−x)₂O₃/Ga₂O₃ modulation doped field effect transistors,¹⁸⁹ β-Ga₂O₃ MOSFETs,^{11,190,191,193} and β-Ga₂O₃ Schottky barrier diodes.¹⁵⁴ In all of these reports, it has been found that strategies involving top-side or flip-chip cooling as well as double-sided cooling may be effective for the thermal management of β-Ga₂O₃ electronics. Challenges that remain for this area of research are outlined below.

The knowledge of the thermal resistance between the heat source and heatsink in gallium oxide electronics is a critical need for modeling and designing devices. While several studies have shown that the thermal conductivity of bulk β-Ga₂O₃ is highly anisotropic,^188,194 this property is likely to be impacted by size effects,¹⁹⁵ defects (e.g., vacancies and dopants),¹⁹⁶ and chemical composition (i.e., ternary alloys),¹⁸⁹ which have not been fully characterized. The thermal conductivity of a ∼400 nm-thick (100)-oriented β-Ga₂O₃ exfoliated film was shown to have a thermal conductivity of 8.4 W/m K (∼35% lower than that of a bulk crystal), which reveals the strong thickness-dependence of the thermal conductivity.¹⁹⁷ Ternary alloys, such as (Al_xGa_1−x)₂O₃, are used to create heterostructures to be used in advanced device architectures, such as MODFETs. Such ternary alloys are expected to have much lower thermal conductivities than the binary base crystals (as was shown in Al_xGa_1−xN;¹⁹⁸). A ternary alloy (Al_xGa_1−x)₂O₃ with 19% Al composition was shown to have a thermal conductivity as low as 3.6 W/m K in the [010] direction and 3.1 W/m K in the direction perpendicular to the (010)-plane. This reduction in thermal conductivity is already an order of magnitude lower than that for bulk β-Ga₂O₃. Better understanding of the size effects, temperature dependency, and alloy composition on the thermal properties of β-Ga₂O₃ must be explored. Other strong reductions in thermal conductivity are expected to come from the creation of superlattices where strong phonon scattering from multiple interfaces will impede the heat flow. In summary, thermal property measurement that explores the material space of gallium oxide will be critical to provide accurate thermal properties for device modeling. For example, it is likely that low thermal conductivity alloy barrier layers will have an impact on any top side extraction from β-Ga₂O₃/(Al_xGa_1−x)₂O₃ MODFET.

At present, in situ optical methods, such as infrared thermography, thermoreflectance imaging, and micro-Raman thermometry, are used for thermal imaging of wide-bandgap electronic devices, such as GaN high electron mobility transistors (HEMTs).^199–203 However, these techniques are insufficient for the thermal characterization of β-Ga₂O₃ device technologies. Infrared thermography is incapable of probing both the semiconductor channel (due to its transparency to infrared radiation) and the metal electrodes (due to low emissivity) and lacks the spatial resolution. Thermoreflectance imaging of the metallization structures (e.g., gate electrode) is possible at low modulation frequencies (to account for the slow transient thermal dynamics of β-Ga₂O₃ devices). However, probing the semiconductor channel using visible to near-UV wavelength illumination sources is difficult because β-Ga₂O₃ is transparent at these wavelengths. At the time being, micro-Raman thermography techniques that make use of nanomaterials as discrete (i.e., nanoparticles¹⁸¹) or continuous (i.e., 2D layered materials²⁰⁴) surface temperature transducers are most suitable for performing quantitative thermal imaging of β-Ga₂O₃ devices. To this end, a high resolution non-invasive, non-contact method that can directly probe the surface temperature of β-Ga₂O₃ is yet to be developed.

A variety of materials need to be integrated with β-Ga₂O₃ devices to provide effective pathways for heat dissipation away from the device active region. These materials will include metal contacts, solder joints, dielectric layers, underfills, and high thermal conductivity substrates (e.g., AlN, SiC, and diamond). It has been predicted in several studies that top-side/flip-chip or double-sided cooling strategies will provide the most effective thermal management strategies.^11,191,194 However, the execution in building these architectures remains a challenge, especially in the growth and integration of high thermal conductivity dielectric layers on top of the active region of β-Ga₂O₃ devices, without compromising the device electrical performance. The development of growth techniques of high thermal conductivity dielectric materials, such as diamond, AlN, and BN polytypes, on β-Ga₂O₃ devices will be important to support top-side or double-sided cooling. Overall, the impact of cooling is expected to be seen for dielectric layers with micrometer range thickness on top of the device channel with a thermal conductivity greater than 100 W/m K.

For the bottom-side heat extraction of the device, several methods, including the integration of β-Ga₂O₃ with SiC through surface activation bonding,^205,206 fusion bonding,²⁰⁷ and direct growth,²⁰⁸ have been demonstrated. However, controlling the thermal transport across numerous interfaces from heterogeneous integration is still an active area of research. Challenges arise from phonon transport and scattering near the interfaces due to intrinsic material properties and many forms of defects (e.g., voids, amorphous layers, and impurities) that may form during the various processing steps of integration. The thermal resistances originating from these interfaces can contribute a significant fraction to the total junction-to-package thermal resistance, especially when β-Ga₂O₃ is integrated with high thermal conductivity substrates or dielectric materials. One major limitation in the pursuit of backside heat removal is the wafer thinning process. As the substrates have increased in size, they have also gotten more fragile. Ideally, the wafer can be thinned to less than 50 μm for efficient heat removal. Lapping and polishing techniques will need to be explored and developed to maintain wafer yield.

Because of the complications associated with the thermal boundary resistance (TBR) at interfaces, it is important to understand and control all the related TBR properties in β-Ga₂O₃ power devices, which involve the propagation, transmission, and reflection of different thermal energy carriers governed by different transport mechanisms. Nonetheless, a key aspect of the future of device thermal management will rely upon the success of heterogeneous integration of these heat spreading and dissipating materials with high thermal conductivities and sufficiently low TBR at interfaces with β-Ga₂O₃. The integration techniques must be solutions that can be supported by wafer scale manufacturing. In addition, additional efforts are needed in the development of high thermal conductivity dielectric underfills to help dissipate the heat from the device channel.

By definition, a power switch operates with high efficiency. The heat generated will be a function of the switch’s duty cycle. Switch analysis has yet to be studied for this material and may heavily influence implementation. If self-heating gives an upper bound to the duty cycle, it is conceivable that vertical and lateral topologies will differentiate further in applications. Some benefit will be observed by changes in device architecture to help spread out the heat generated in the active region. Moving from lateral to vertical device structures will provide opportunities to reduce thermal energy generation densities and operate at higher voltage and power levels. It has been observed that β-Ga₂O₃ will operate at high temperatures due to its wide bandgap,^21,190,209 but the intrinsic limits of performance and reliability as a function of temperature have yet to be explored. Thermally aware design optimization of the layout of device interconnects, which will play a major role in the heat dissipation pathways for top side cooling, will also be an important feature that must be optimized.

Additional methods to cool high-power β-Ga₂O₃ devices will likely involve active cooling strategies. While air cooling is desired for low cost and high reliability strategies, active liquid cooling methods are expected to significantly enhance the operational power densities achieved by these devices and may find their niche in high performance applications.

The β-Ga₂O₃ materials system offers favorable attributes in terms of creating next-frontier power electronic devices (i.e., outstanding electronic properties and low-cost substrate manufacturability). The material’s low thermal conductivity resulting in overheating has become a major bottleneck to maximize the performance of β-Ga₂O₃ device technologies. A paradigm shift in the device design process, i.e., electro-thermal co-design, is necessary to overcome the thermal impediments. In order to implement such co-design techniques, the development of novel thermal characterization and multi-physics, multi-scale device modeling schemes are necessary. These innovations in convergent research will allow the full exploitation of the promising benefits of the ultra-wide bandgap material.

Masataka Higashiwaki

As discussed in Secs. I–III, β-Ga₂O₃ has a high potential based on its extremely large bandgap as a semiconductor material following SiC and GaN for next-generation power switching and RF device applications. It is obvious that high-efficiency β-Ga₂O₃ power switching devices contributing global energy conservation will be more and more demanded. Harsh-environment β-Ga₂O₃ RF FETs operating at high temperature and/or under strong radiation would pave the way for the new field of semiconductor electronics. However, it is worth noting that β-Ga₂O₃ has two fundamental drawbacks originated from its physical properties: no hole-conductive p-type and poor thermal conductivity. Due to the lack of p-type material having reasonable hole conductivity, β-Ga₂O₃ device structures have significant design limitations. Furthermore, its low thermal conductivity that directly affects heat dissipation capacity of β-Ga₂O₃ devices is another serious issue, especially for high-power device applications. We need to accept these two shortcomings and work on developments of β-Ga₂O₃ devices in the future.

To build up more advanced β-Ga₂O₃ FET and diode technologies, there are many challenges left in all aspects of bulk melt growth, epitaxial thin-film growth, and device processing. In bulk melt growth and wafer production, it can be pointed out as a major difficulty that expensive rare metal iridium (Ir) is used as a material of crucibles. Large reduction in its amount for the crucible is required to suppress production cost of β-Ga₂O₃ bulk wafers. With respect to epitaxial growth, HVPE and MOCVD have reached to a certain level that can take future mass production into consideration but needs to be much more improved and advanced. In particular, improvement of reproducibility and reliability of the n-type doping technology and exploratory research on p-type doing technology take a high priority. Developments on epitaxial growth technologies for heterostructures using (AlGa)₂O₃ and (InGa)₂O₃ layers should also be actively pursued. In parallel with the developments on the bulk and epitaxial growth technologies, fundamental research on physical properties of β-Ga₂O₃ is important and should be conducted with the support of the academic community. In particular, more complete understanding on physical properties of point defects in β-Ga₂O₃ is highly required to put reliability and stability of β-Ga₂O₃ devices in the proper perspective. Furthermore, it can be expected that intentional manipulation of the point defects would lead to creation of novel devices with new functions.

As for device processing, there are still a variety of fundamental technologies that should be developed. Ease of ion-implantation doping is one of the big features for β-Ga₂O₃; however, the process is far from being established. The search of new elements for the ion-implantation doping and optimization of the process condition should be carried out. An etching process gains more importance for the development of vertical FETs and diodes. Currently, reactive ion etching and inductively coupled plasma etching that cause some damage on the etched surface are usually used for the β-Ga₂O₃ device fabrication. We should develop a new etching technology that can reduce the degree of the damage. Needless to say, the bandgap energy of over 4.5 eV is the most distinguishing feature of β-Ga₂O₃; however, this leads to an issue that gate dielectric materials are very limited to form a large energy barrier at a dielectric/β-Ga₂O₃ interface. In addition, the interface quality needs to be further improved, especially for normally off FETs. The poor heat dissipation capacity of β-Ga₂O₃ devices remains as a crucial issue for high-power device operation. One of the effective ways to improve it is direct bonding to a foreign substrate with good thermal and electrical conductivities.

The year 2021 marks the tenth anniversary of the ground-breaking demonstration of the world’s first single-crystal β-Ga₂O₃ FETs,²⁷ which galvanized intensive international research and development activities on Ga₂O₃ into the science and engineering. Consequently, in this decade, β-Ga₂O₃ has earned its citizenship within the semiconductor community, and many fundamental material and device technologies have been generated. However, the worldwide research and developments on β-Ga₂O₃ have mostly been conducted by universities and public research institutes, and the degree of corporate contributions has been little. Active participation of manufacturing companies in the development is indispensable to enhance not only the development speed of β-Ga₂O₃ power and RF devices but also the technology transfer from the lab to the fab. Whether β-Ga₂O₃ ends up with just a booming semiconductor material or reaches to the stage of the device practical realization and industrialization, providing valuable contributions to the global challenges and economy depends on the research and development activity in the coming decade. The community is standing at a major inflection point, and the next decade will be revolutionary for the sector.

The authors declare no conflict of interest.

The data that support the findings of this study are available from the corresponding author upon reasonable request.